Hash processor (HASH)
The HASH is a fully compliant implementation of the secure hash algorithm (SHA-1, SHA-224, SHA-256, SHA2-384, and SHA2-512), the MD5 (message-digest algorithm 5) hash algorithm, and the HMAC (keyed-hash message authentication code) algorithm. HMAC is suitable for applications requiring message.
The HASH implementation proposes a DMA mode. The HASH generates GPDMA requests allowing the user to perform single or burst GPDMA write transfers. The GPDMA request signal is used by the hardware to request a new input to be written by the GPDMA whenever the peripheral needs it. The request may be a request for either a 32-bit single data to be written, or a burst of 4 (32-bit) words to be written. The GPDMA writes the HASH_IN register. This HASH register must be accessed by with a destination source data width being 32-bit with a fixed addressing, and a burst length of 1 or 4.
The HASH implementation uses a 16-word FIFO for the HASH_IN register.
For best GPDMA performances, it is recommended to allocate one of the channels with an 8-word FIFO. If such a channel is allocated, 4-word bursts for writing to the memory can also be programmed and implemented.
If no channel with 8‑word FIFO is free, a channel with 2‑word FIFO is allocated, and programming a fixed 4‑word burst write is also recommended for higher performances. This allows the request signal hash_in_dma to be handled in hardware between the GPDMA and the HASH as a hardware burst request, and not as a single. Knowing that at least 4 AHB clock cycles must occur between two occurrences of a HASH request, the transfer rate can be higher via programmed burst. On the memory side, transfers are then performed by 32-bit single reads (due to FIFO size).
The table below summarizes the main peripheral characteristics: different hardware request signals to the GPDMA, peripheral bus on which the peripheral is connected, and corresponding peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| hash_dma/hash_in_dma | AHB3 for STM32N6 and AHB2 for others | 16-word FIFO | Write 32-bit HASH_IN | HASH input data register (HASH_IN) can be written by a single word or by a 4-word burst. |
The table below shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA destination port | GPDMA destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 01 | 32-bit | 1 or 4 |
Channel with 8‑word FIFO for burst performances if available | The default recommended setting also balances bandwidth over each port (source port 0 to write to peripheral, destination port 1 to read from memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. For improved burst performances, the channel allocation can be one of the channels with 8‑word FIFO. |
1 By default, port 0 is recommended to access peripheral register, and port 1 to access memory, if no specific requirements.
AES hardware accelerator (AES)
The AES is not available on STM32H7Rx/7Sx and STM32N6 devices.
The AES hardware accelerator encrypts/decrypts data, using an algorithm and implementation fully compliant with the advanced encryption standard (AES) defined in federal information processing standard (FIPS) publication 197.
The AES supports CTR, GCM, GMAC, CCM, ECB, and CBC chaining modes for 128- or 256-bit key size.
The AES performs 128-bit block cryptographic processing, and implements a 128-bit input buffer/FIFO and a 128‑bit output buffer/FIFO.
This peripheral is not burst capable when doing GPDMA transfer. All transfers must be handled in single data mode by the GPDMA controller, since the peripheral sends a new GPDMA request each time an input/output 32‑bit data is needed to be written/read. Then GPDMA performs a read/write access to the related 32-bit data register, with a programmed source/destination data width of 32-bit and a fixed addressing.
One of the channels with 2‑word FIFO can be allocated (as well one of the channels with 8‑word FIFO), especially if the memory to be written is an external memory.
The table below summarizes the main peripheral characteristics: different hardware request signals to the GPDMA, the peripheral bus on which the peripheral is connected, and the corresponding peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| aes_in_dma | AHB2 | 128-bit/4-word input buffer | Write 32-bit AES_DINR | Request for a new 32-bit input data to be written by the GPDMA |
| aes_out_dma | 128-bit/4-word output buffer | Read 32-bit AES_DOUTR | Request for a new 32-bit output data to be read by the GPDMA |
The table below shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/ destination port | GPDMA source/ destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 01 | 32-bit | 1 | Channels with 2‑word FIFO | The default recommended setting also balances bandwidth over each port (source port 0 to write to peripheral, destination port 1 to read from memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. For improved burst performances, the channel allocation can be one of the channels with 8‑word FIFO. |
1 By default, port 0 is recommended to access peripheral register, and port 1 to access memory, if no specific requirements.
Secure AES coprocessor (SAES)
The SAES is the secure AES version. All data described in AES hardware accelerator (AES) are valid. The only difference is the GPDMA request signal names (saes_in_dma and saes_out_dma).
Cryptographic processor (CRYP)
The cryptographic processor is available only on STM32H7Rx/7Sx and STM32N6 devices.
The cryptographic processor (CRYP) encrypts or decrypts data in compliance with the advanced encryption standard (AES) defined by NIST.
CRYP supports ECB, CBC, CTR, GCM, GMAC, and CCM chaining modes for key sizes of 128, 192, or 256 bits. CRYP has the possibility to load by hardware the key stored in SAES peripheral, under SAES control.
The peripheral supports DMA transfers for incoming and outgoing data (two DMA channels are required). CRYP also includes input and output 8‑word FIFO for better performance.
The output FIFO supports both single and burst transfers, while the input FIFO supports only burst transfers.
The table below summarizes the main peripheral characteristics: different hardware request signals to the GPDMA, the peripheral bus on which the peripheral is connected, and the corresponding peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus |
Peripheral FIFO | Peripheral register access | Comments |
|---|---|---|---|---|
| cryp_in_dma | AHB3 | 8-word input FIFO | Write 32-bit CRYP_DIN | Request for a 4-word (fixed) burst data to be written to CRYP input FIFO. |
| cryp_out_dma | 8-word output FIFO | Write 32-bit CRYP_DOUT | Request for a 4-word (fixed) burst data or a single word data to be read from CRYP output FIFO. |
The tables below show the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source port | GPDMA source burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 01 | 32-bit | 4 | Channel with 8‑word FIFO |
On write: peripheral is burst capable and burst length must be 4. 4-word burst must be DMA programmed, for any channel. DMA may issue a single word or a 2, 3 or 4-word burst. For improved burst performances, one GPDMA channel from 12 to 15 must be allocated. The default recommended setting balances bandwidth over each port (source port 0 to write to peripheral, destination port 1 to write to memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. |
| GPDMA source port | GPDMA source burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 01 | 32-bit | 1 or 4 | Channel with 2‑word FIFO |
On read: peripheral is burst capable and burst length must be 1 or 4. 1-word single or 4-word burst must be DMA programmed, for any channel. DMA may issue a single word or a 2, 3 or 4-word burst. For improved burst performances, one GPDMA channel with 8‑word FIFO must be allocated. The default recommended setting balances bandwidth over each port (source port 0 to write to peripheral, destination port 1 to write to memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. |
1 By default, port 0 is recommended to access peripheral register, and port 1 to access memory if no specific requirements.