Low-power timers (LPTIM)
The STM32 devices embed multiple low-power timers.
The low-power timers are 16-bit timers that benefit from the ultimate developments in power-consumption reduction. Thanks to their clock source diversity, the LPTIMx are able to keep running in all power modes except Standby mode.
The LPTIM is not burst capable when doing GPDMA transfer. All transfers are in single data mode.
The LPTIM4, LPTIM5 (only on STM32H7Rx/7Sx) does not provide any GPDMA request.
The LPTIM is GPDMA capable with two types of requests:
- Input capture
- From timer channel 1, lptimx_ic1_dma
- From timer channel 2, lptimx_ic2_dma
Then the GPDMA reads the 16-bit LPTIMx_CCRy (y = 1, 2) registers to get the new latched counter value in input capture mode.
- Update event
- An lptimx_ue_dma request is a GPDMA block-type request, and requires a specific hardware connection between the timer and the GPDMA to be activated by programming BREQ = 1 (and SWREQ = 0) in GPDMA_CyTR2 (y is the allocated GPDMA channel).
- The block consists of up to three single writes to the LPTIMx to update up to two of the following registers, in order to update the generation of a PWM signal: LPTIMx_CCR1 (capture compare register 1 for the duty cycle), LPTIMx_CCR2 (capture compare register 2 for the duty cycle), and LPTIMx_RCR (repetition counter register), followed by a mandatory update of the LPTIMx_ARR for the period.
Port 0 is typically allocated for the read/write timer registers access, and port 1 for the memory access to balance traffic over the two ports. One of the channels with 2‑word FIFO is allocated with a high priority to get a transfer latency as less as possible sensitive to other traffic. See GPDMA channel priority for more details, especially for time-sensitive use of the timer.
Any LPTIMx generates two output signals (lptimx_ch1 and lptimx_ch2), which are used as trigger for any GPDMA transfer and/or for a DAC conversion.
The LPTIM4 and LPTIM5 for STM32H7Rx/7Sx generates an output signal, lptim4_out, lptim5_out which are used as trigger for any GPDMA transfer and/or DAC conversion.
The table below summarizes the main peripheral characteristics: different hardware request signals to the GPDMA, the peripheral bus on which the peripheral is connected, and the corresponding peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus |
Peripheral FIFO | Peripheral register access | Comments |
|---|---|---|---|---|
| lptimx_icy_dma (x = 1, 2, 3, 5, 6 and y = 1, 2) | LPTIM2/3 on APB4 for and STM32N6 LPTIM1/3/5/6 on APB3 for STM32H5, LPTIM1/3 on APB3 for STM32U5 and LPTIM1/3 on APB3 for STM32U3 LPTIM2 on APB1 for STM32H5, STM32U5, and STM32U3 and LPTIM1 on APB1 for STM32H7Rx/7Sxand STM32N6 | None | Read 16-bit/32-bit LPTIMx_CCRy | Request to read the capture compare register on an input capture event (connected input signal). Must be a 32-bit aligned address access. |
| lptimx_ue_dma (x = 1, 2, 3, 5, 6) |
Write up to 3x 16-bit or 3x 32-bit registers among LPTIMx_CCR1, LPTIMx_CCR2, LPTIMx_RCR and mandated LPTIMx_ARR | Request to up to three writes of the LPTIMx registers on an update event. Must be a 32-bit aligned address access. |
The table below shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/ destination port | GPDMA source/ destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 01 | 16- or 32-bit | 1 | Channels with 2‑word FIFO | GPDMA1 port 0 is optimized to connect the APB1 LPTIM2 since there is a direct connection (at architecture level) from the GPDMA to the APB bridge on which the TIMx is connected. There is less latency and faster response time for a given priority level. The default recommended setting also balances bandwidth over each port (source port 0 to read from peripheral, destination port 1 to write to memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. Priority 3 is recommended if the application requires a minimized latency whatever is other concurrent traffic. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. |
1 Port 0 is selected for accessing APB1 peripheral register (direct connection), and port 1 for accessing to memory. If no specific requirements, by default, port 0 can be selected for accessing APB3 peripheral register, and port 1 for accessing to memory.
Basic timers (TIM6/7/18)
The basic timers consist of a 16-bit auto-reload upcounter driven by a programmable prescaler. They can be used as generic timers for time-base generation.
These timers are not burst capable when doing GPDMA transfer.
The timer update request to the GPDMA (timx_upd_dma with x = 6, 7 or 18), occurs when the counter overflows (when a programmed period of time elapses). The GPDMA performs a 32-bit write to TIMx_ARR (x = 6, 7 or 18 and including 4 dithering bits), in order to update the timer output period and waveform for the next counter overflow.
It is recommended to allocate:
- The port 0 for peripheral register access (direct connection to AHB/APB bridge).
- The port 1 for memory access (to balance traffic), a channel with 2‑word FIFO, and a high priority (to get a transfer latency as less as possible sensitive to other traffic).
TIM6, TIM7 and TIM18 generate a trigger signal, respectively tim6_trgo, tim7_trgo and tim18_trgo, which may be used as trigger for any GPDMA transfer and/or for a DAC conversion.
The table below summarizes the main peripheral characteristics: different hardware request signals to the GPDMA, peripheral bus on which the peripheral is connected, and corresponding peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| timx_upd_dma/timx_up_dma (x = 6, 7 or 18) | APB1 | None | Write 32-bit TIMx_ARR | Request on an update event (on a counter overflow) |
The table below shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA destination port | GPDMA destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 01 | 32-bit | 1 | Channels with 2‑word FIFO | GPDMA1 port 0 is optimized to connect the APB1/APB2 TIMx since there is a direct connection (at architecture level) from the GPDMA to the APB bridge on which the TIMx is connected. There is less latency and faster response time for a given priority level. Priority 3 is recommended if the application requires a minimized latency whatever is other concurrent traffic. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. |
1 Port 0 is selected for writing APB1 peripheral register (direct connection), and port 1 for accessing to memory.
General-purpose timers
The STM32 devices embed multiple general-purpose timers.
The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler. TIM2/3/4/5/15/16/17 can be used for various purposes such as measuring the pulse lengths of input signals (input capture), or generating output waveforms (output compare, PWM, possibly complementary PWM with dead-time insertion).
These timers are not burst capable when doing GPDMA transfer. All read/write transfers must be handled in single data mode by the GPDMA controller, since the timer sends a new GPDMA request each time a 32-bit or 16-bit data/control is needed to be written/read.
A timer request can be used for the following actions:
- A 32-bit write to TIMx_ARR in basic mode, to update the output waveform and period when counter over/underflows.
- A 32-bit read to TIMx_CCRy (y = 1 to 4), to get the latched counter value in input capture mode.
- A 32-bit write to TIMx_CRRy (y = 1 to 4), to update the output compare register in output compare mode (duty cycle).
- A 16-bit/32-bit write to TIMx_RCR (x = 15, 16, 17), in PWM output/modulation mode, to update the repetition counter while the period is given by TIMx_ARR, and duty cycle is given by TIMx_CCR.
- A 32-bit read to TIMx_CCR1, and a 32-bit read to TIMx_CCR2 in input PWM mode to get the latched counter for respectively the period and the pulse width.
- A series of 32-bit writes to the intermediate TIMx_DMAR register in timer ‘burst’ mode, or a series of 32-bit reads from the intermediate TIMx_DMAR register in timer ‘burst’ mode.
The timer supports multiple single accesses to redirect the value to/from the timer registers through one entry point. This timer capability to write multiple timer registers through a single entry-point is called ‘burst’. The GPDMA can perform the data transfers in single mode multiple times upon any programmed hardware event/request (among timx_chy_dma, timx_upd_dma, timx_trg_dma, timx_com_dma possible events). This timer ‘burst’ capability is different and must not be confused with a GPDMA burst that is defined in GPDMA burst and widely used in this document (as well as in the GPDMA section of the reference manual).
A timer request to GPDMA is quite programmable and flexible: it is related to the occurrence of a programmed event versus the real-time value of the timer counters. A timer request is not tightly coupled to write/read a specific timer register. Any timer register may be read/written depending on the application (the contrary of the other peripherals).
It is recommended to allocate:
- The port 0 for peripheral register access (direct connection to AHB/APB bridge).
- The port 1 for memory access (to balance traffic), a channel with 2‑word FIFO, and a high priority (to get a transfer latency as less as possible sensitive to other traffic).
For some application needs, a timer request to GPDMA can be used to initiate a data transfer not involving timer register read/write, but other memory-mapped location, like for memory‑to‑memory transfers. In this case, the GPDMA port allocation strategy must not be considered with respect to the timer register location, but with the source/destination locations.
TIM2 and TIM15 generate a trigger signal (respectively tim2_trgo and tim15_trgo) which can be used as trigger for any GPDMA transfer.
The table below summarizes the main peripheral characteristics: different hardware request signals to the GPDMA, peripheral bus on which the peripheral is connected, and corresponding peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| timx_chy_dma/timx_ccy_dma (x = 2 to 5 and y = 1 to 4) or (x = 15 to 17 andy = 1) |
APB1 for TIM2/3/4/5 | None |
32-bit write TIMx_ARR in basic mode or | Request on an input capture event or an output compare event |
| timx_upd_dma/timx_up (x = 2 to 5, 15 to 17) | Request on an update event | |||
| timx_trg_dma/timx_trig_dma (x = 3, 5, 15) | Request on a trigger event | |||
| tim15_com_dma | Request on a commutation event |
The table below shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/ destination port | GPDMA source/ destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 01 | 32-bit (or 16-bit for TIMx_RCR) | 1 | Channels with 2‑word FIFO | GPDMA1 port 0 is optimized to connect the APB1/APB2 TIMx since there is a direct connection (at architecture level) from the GPDMA to the APB bridge on which the TIMx is connected. There is less latency and faster response time for a given priority level. Priority 3 is recommended if the application requires a minimized latency whatever is other concurrent traffic. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. |
1 Port 0 is selected for reading/writing APB1/APB2 peripheral register (direct connection), and port 1 for accessing to memory. If the memory location to be accessed is not a timer register, this recommendation can be ignored.
Advanced-control timers (TIM1/8)
The advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. TIM1/8 (STM32H7Rx/7Sx and STM32U3 have TIM1 only) can be used for various purposes such as measuring the pulse lengths of input signals (input capture), or generating output waveforms (output compare, PWM, complementary PWM with dead‑time insertion).
These timers are not burst capable when doing GPDMA transfer. All read/write transfers must be handled in single data mode by the GPDMA controller, since the timer sends a new GPDMA request each time a 32-bit or 16-bit data/control is needed to be written/read.
A timer request can be used for the following actions:
- A 32-bit write to TIMx_ARR in basic mode, to update the output waveform and period when counter over/underflows.
- A 32-bit read to TIMx_CCRy (x = 1, 8 and y = 1 to 4), to get the latched counter value in input capture mode.
- A 32-bit write to TIMx_CRRy (x = 1, 8 and y = 1 to 4), to update the output compare register and duty cycle in output compare mode.
- A 16-bit/32-bit write to TIMx_RCR (x = 1, 8), in PWM output/modulation mode, to update the repetition counter while period is given by TIMx_ARR, and duty cycle is given by TIMx_CCR.
- A 32-bit read to TIMx_CCR1 and a 32-bit read to TIMx_CCR2, in input PWM mode, to get the latched counter for respectively the period and the pulse width.
- A series of 32-bit writes to the intermediate TIMx_DMAR register in timer ‘burst’ mode, or a series of 32-bit reads from the intermediate TIMx_DMAR register in timer ‘burst’ mode. The timer supports multiple single accesses to redirect the value to/from the timer registers through one entry point. This timer capability to write multiple timer registers through a single entry-point is called 'burst'. The GPDMA can perform the data transfers in single mode multiple times upon any programmed hardware event/request (among timx_chy_dma, timx_upd_dma, timx_trg_dma, timx_com_dma possible events). This timer ‘burst’ capability is different and must not be confused with a GPDMA burst that is defined in GPDMA burst and widely used in this document (as well as in the GPDMA section of the product reference manual).
A timer request to GPDMA is quite programmable and flexible: it is related to the occurrence of a programmed event versus the real-time value of the timer counters. A timer request is not tightly coupled to write/read a specific timer register, and any timer register can be read/written, depending on the application (the contrary of the other peripherals).
It is recommended to allocate:
- The port 0 for peripheral register access (direct connection to AHB/APB bridge)
- The port 1 for memory access (to balance traffic), a channel with 2‑word FIFO, and a high priority (to get a transfer latency as less as possible sensitive to other traffic
For some application needs, a timer request to GPDMA can be used to initiate a data transfer not involving timer registers read/write, but other memory-mapped location, like for memory‑to‑memory transfers. In this case, the GPDMA port allocation strategy must be not be considered with respect to the timer registers location, but with the source and destination locations.
The table below summarizes the main peripheral characteristics: different hardware request signals to the GPDMA, peripheral bus on which the peripheral is connected, and corresponding peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| timx_chy_dma/timx_ccy_dma (x = 1, 8 and y = 1 to 4) | APB2 | None | No tightly coupled timer register read/write Typically a 32-bit read/write to TIMx_CCRy or a 16-/32-bit read/write to TIMx_RCR or a series of 32-bit read/writes to TIMx_DMAR (x = 1, 8 and y = 1 to 4) | Request on an input capture event or an output compare event |
| timx_upd_dma/timx_up_dma (x = 1, 8) | Request on an update event | |||
| timx_trg_dma/timx_trig_dma (x = 1, 8) | Request on a trigger event | |||
| timx_com_dma (x = 1, 8) | Request on a commutation event |
The table below shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/ destination port | GPDMA source/ destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 01 | 32-bit (or 16-bit for TIMx_RCR) | 1 | Channels with 2‑word FIFO | GPDMA1 port 0 is optimized to connect the APB2 TIM1/8 since there is a direct connection (at architecture level) from the GPDMA to the APB bridge on which the TIM1/8 is connected. There is less latency and faster response time for a given priority level. Priority 3 is recommended if the application requires a minimized latency whatever is other concurrent traffic. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. |
1 Port 0 is selected for reading/writing APB2 peripheral register (direct connection), and port 1 for accessing to memory. If the memory location to be accessed is not a timer register, this recommendation can be ignored.