System performance

The microcontroller architecture needs to be understood in order to control that the different GPDMA requested transfers can be efficiently performed: transferred in due time (with an acceptable latency and completion time versus the application requirements) while optimizing the bus bandwidth efficiency, and minimizing the resource utilization/load (bus/resource utilization, bus overhead, AHB/APB frequencies).

The previous sections refined the GPDMA characteristics, and provided user guidelines to get the best performances for serving a GPDMA data transfer. The following sections describe other key points which impact this performance.

GPDMA

The GPDMA has two master ports for parallelization of AHB transfers. Simultaneous transfers via the two ports are possible. A GPDMA arbitration occurs for each port as follows:

a priority-based arbitration (see Figure 1 GPDMA arbitration policy) between the 8 possible requested FIFO-based read bursts
a priority-based arbitration (see Figure 1 GPDMA arbitration policy) between the 8 possible requested FIFO-based write bursts
a final round-robin arbitration stage between read and write

The GPDMA port 0 has a direct connection with APB1/APB2 peripherals as shown in the figure below.

Figure 2. Latency optimization (APB1/2 peripherals mapped on GPDMA port0)

The strategy and guidelines to be applied for the GPDMA port allocation and the priority assignment are detailed in GPDMA port selection and GPDMA channel priority.

Bus matrix

The multilayer AHB bus matrix allows parallel access to a number of shared AHB slaves from a number of different AHB masters. The bus matrix improves the transfer parallelism, and contributes to reduce the transfer execution time and to optimize the shared resources utilization.

AHB bus definitions

AHB master: a bus master initiates read/write AHB single/burst transfer. Only one master can get bus ownership at a given time.
AHB slave: a bus slave responds to the AHB transfer from a master. The bus slave routes signals back to the master to inform about the access success, failure or waiting states.
AHB arbiter: a bus arbiter ensures that only one master can access a slave at a given time.
AHB bus matrix: a switch matrix that interconnects AHB masters to AHB slaves. It implements a round‑robin AHB arbiter for each slave.

Bus matrix round-robin arbitration

A bus matrix arbitration is implemented for each slave in order to arbitrate its access from concurrent masters. This round-robin arbitration allows a fair distribution of the shared resource over the time (see the example in Figure 3 Example of CPU and GPDMA requesting an access to SRAM1) and a bounded latency. Round robin algorithm is implemented with the following rules:

A round-robin quantum is one AHB transfer. There is bus switching on every transfer if another master port waits for the access to a slave.
A master port has a defined default slave.
- When accessing a default slave, a master port gets:
  - 0-cycle arbitration penalty when it first accesses the default slave (provided that the bus is free/idle)
  - 0-cycle rearbitration penalty, and is immediately granted to reaccess the default slave with a back-to-back transaction, if there is no other master waiting for the shared slave
- When accessing a non-default slave, a master port gets:
  - 1-cycle arbitration penalty when it first accesses the non-default slave (provided that the bus is free/idle)
  - 1-cycle rearbitration penalty to be granted to reaccess the non-default slave if there is at least one dead clock cycle/wait state between its back-to-back transfers (even if no other master waiting for the shared slave).
  - 0-cycle rearbitration penalty to be granted to reaccess the non-default slave if there is no dead clock cycle/wait state between its back-to-back transfers (if no other master waits for the shared slave).

The figure below shows an example where both the CPU and GPDMA try to access SRAM1.

Figure 3. Example of CPU and GPDMA requesting an access to SRAM1

In case of concurrent accesses from the CPU and the GPDMA, the bus matrix arbitration rules the access to the SRAM1. If the last access is from the CPU, during the next access, the GPDMA wins the bus, and accesses SRAM1. After the CPU can again access SRAM1.

The transfer latency initiated by one master to access a slave depends on the number of other pending transfers initiated by other masters to access the same AHB slave. The figure below details another example where four masters try to access SRAM1 simultaneously.

Figure 4. Example of four master requesting an access to SRAM1

The latency associated to the GPDMA (burst) transfer to access the bus and SRAM1 in the example above, is increased by the sum of execution times of all pending requests coming from the other masters. If the DMA2D accesses the SRAM1 in burst mode for example, the GPDMA access latency is increased by the latency of the DMA2D burst.

Note:

The latency due to CPU transfers issued by LDM/STM instructions can be reduced by configuring the compiler to split load/store multiple instructions into single load/store instructions.

Bus (AHB and APB) switches

As depicted in Figure 2 Latency optimization (APB1/2 peripherals mapped on GPDMA port0), the STM32 devices embed several AHB/APB switches in order to decode/multiplex the AHB/APB signals.

A bus switch adds no cycle penalty to a transfer latency/execution time.

SRAMs

Transfer latency and execution time

The SRAM access latency is the SRAM execution time for completing a burst/single read/write access, seen from the AHB bus interface.

A GPDMA write is a non-bufferable write. In the STM32 devices, a bufferable write access is restricted to a CPU access to an external memory via the data cache.

An SRAM introduces no additional wait-state for an AHB access. An 8-,16-, or 32-bit GPDMA transfer that accesses an SRAM in read or write, as a single, takes 2 AHB clock cycles so that the access is completed (one for the address phase, one for the data phase).

For completion at the SRAM bus interface:

A GPDMA single transfer (1x NONSEQ) takes 2 cycles.
A GPDMA 4-beat incremented burst transfer (1x NONSEQ + 3x SEQ) takes 5 cycles.

At the SRAM bus interface, it takes 8 AHB clock cycles via singles versus 5 cycles via a burst to transfer 4 words in SRAM at consecutive address locations (with transfer not arbitrated and preempted by other concurrent ones in front).

The GPDMA inserts also 1 cycle between two memory accesses. The bus matrix inserts another cycle if the addressed SRAM is not the default slave (if SRAM1 is not accessed by the GPDMA port1). Consequently, for completion:

A GPDMA single read/write transfer to SRAM takes 3 to 4 cycles.
A GPDMA 4-word incremented burst read/write transfer to SRAM takes 6 to 7 cycles.

Table 59 GPDMA read/write transfer to SRAM latency (4-beat burst versus single) gives the latency for completion of a programmed (half) transfer to the SRAM, depending on the allocated channel and its FIFO size (see GPDMA channel allocation and GPDMA burst).

Table 59. GPDMA read/write transfer to SRAM latency (4-beat burst versus single)
Programmed GPDMA (half) transfer (from/to FIFO to/from SRAM)	Channel	Read/Write latency (cycles)
Single	Channel with 2‑word FIFO	3 to 4
Single	Channel with 8‑word FIFO	3 to 4
4-word incremented burst	Channel with 2‑word FIFO^¹	3 to 4^²
4-word incremented burst	Channel with 8‑word FIFO	6 to 7

If the first transfer latency is increased by 3 cycles, the latency for 4 words is decreased of 3 cycles. A buffer transfer is earlier completed by performing bursts versus singles.

¹ These channels have a 2-word FIFO. A programmed 4-word burst is implemented via four singles.

² Latency for an implemented single.

Transfer rate/throughput and bandwidth

Beside this SRAM transfer latency, it is important to consider the performance in terms of how much fast (consecutive) transfers can happen (maximum achievable data throughput).

The SRAM throughput is the number of transferred data per second. For a given AHB operating frequency, the SRAM throughput is the number of (recommended 32-bit) data transferred per AHB clock cycles.

The 32-bit AHB bus architecture consists of:

A dedicated address bus
A separated bus for read and write data
1-cycle pipelined transfers in terms of address and data (on a same clock cycle, the address of a transfer occurs meanwhile the data phase of the previous transfer)

The SRAM introduces no penalty. A transfer rate of one 32-bit read or write per cycle can then be sustained. The GPDMA and the AHB bus cannot achieve such a high throughput.

The table below provides the achieved transfer rate for copying a buffer via a GPDMA channel in memory‑to‑memory mode, when both the source buffer and the destination buffer are located in the SRAM, depending on the allocated channel and the programmed burst length.

Table 60. GPDMA in memory-to-memory mode, SRAM (read+write) transfer rate (4‑beat burst versus single)
Programmed GPDMA (half) transfer to/from SRAM	Channel	Number of cycles (per transferred data/beat)	Transfer rate with a 100 MHz AHB clock (Mtransfer/s)
single	Channel with 2‑word FIFO	3.5 to 4	25 to 28
single	Channel with 8‑word FIFO	2 to 4^¹	25 to 50
4-word incremented burst	Channel with 2‑word FIFO^²	3.5 to 4	25 to 28
4-word incremented burst	Channel with 8‑word FIFO	1.6 to 2.2	45 to 62

Table 60 GPDMA in memory-to-memory mode, SRAM (read+write) transfer rate (4‑beat burst versus single) highlights that a channel with 8‑word FIFO that is programmed with a 4‑word burst can consume only 1.6 cycles in average per transferred word/beat, versus a minimum of 3.5 cycles in average on an allocated channel with 2‑word FIFO for others and single-word transfers. Programming bursts on an allocated channel, which is burst-capable is around twice more efficient than performing singles:

For a given buffer copy, the required GPDMA traffic consumes half less the bus.
For a given bandwidth budget, the GPDMA transfer rate performance is twice higher.

The advantage of performing transfers to/from SRAM by burst transfers versus single is two-fold:

The achievable transfer rate is higher, enabling to sustain more performance.
The bus load/utilization is lower, freeing the bus (as well as bus matrix and other master ports in front) for other concurrent transfers to operate at the given frequency, or/and enabling to operate at a lower frequency for a given traffic.

For memory-to-memory GPDMA transfers to SRAM, it is recommended to allocate a GPDMA channel with 8‑word FIFO, and to program bursts (of length 4 and of 32-bit data width) as much as possible. The performances are not then limited by the peripheral side, as it is the case for peripheral-to-memory and memory‑to‑peripheral transfers.

¹ The improvement between a channel 4 and a channel 0 on single transfers (2 cycles versus 3.5) is because the 8-word FIFO is earlier ready than a 2-word FIFO to perform a next single.

² These channels have a 2-word FIFO. A programmed 4-word burst is then implemented via four singles. A throughput is the same as with single.