Peripheral synchronous slave interface (PSSI)
Only STM32H523/533/562/563/573, STM32H7Rx/7Sx, STM32N6 and STM32U5 devices embed the PSSI.
The PSSI is not burst capable when doing GPDMA transfer, even if an embedded FIFO is present. All transfers must be handled in single data mode by the GPDMA controller, since the PSSI sends a new GPDMA request each time a data is needed to be read/written, depending on the PSSI receive/transmit mode. The GPDMA performs a 32-bit aligned access to read/write from/to the PSSI_DR register. This 32-bit data register can be accessed with a programmed source/destination data width being either 8-, 16-, or 32-bit, and with a fixed addressing. It is recommended to use a 32‑bit data read/write to PSS_DR in order to optimize bus bandwidth and reduce the bus load.
The PSSI is exclusive with the DCMI since they share the same kernel except for STM32H7Rx/7Sx have only PSSI without DCMI.
No burst performance can be achieved for the read/write access to the PSSI. Channels with 2-word FIFO can be allocated, unless channels with 8-word FIFO are free/unallocated and the required performances in terms of bandwidth are significant for this AHB peripheral. Channels with 8-word FIFO may be also allocated if the accessed memory is external.
The table below summarizes the main peripheral characteristics: hardware request signal to the GPDMA, peripheral bus on which the peripheral is connected, and peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| pssi_dma | AHB5 for STM32N6 and AHB2 for others | 8-word FIFO | Read/ write 32‑bit PSSI_DR | The PSSI can transmit or receive parallel data. Must be read/write with a 32-bit aligned address, whatever is the data width. |
The table below shows the supported and recommended GPDMA settings to be used for serving the PSSI peripheral request: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/ destination port | GPDMA source/ destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 01 | 32-bit (recommended) | 1 |
Channels with 2‑word FIFO Channels with 8-word FIFO especially if remains unallocated/free channels for such AHB peripherals which may require significant bandwidth | For optimized bus utilization, it is recommended to transfer words from/to PSS_DR. The default recommended setting balances bandwidth over each port (source port 0 to read from peripheral, destination port 1 to write to memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel with linear_addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. For improved burst performances, the channel allocation can be one of the channels with 8‑word FIFO. |
1 By default, port 0 is recommended to access peripheral register, and port 1 to access memory, if no specific requirements.
Inter-integrated circuit interface (I2C)
The STM32 devices embed up to four I2C instances.
The I2C is not burst capable when doing GPDMA transfer. All transfers must be handled in single data mode by the GPDMA controller, since the I2C sends a new GPDMA request each time a byte data needs to be written/read, or a control word is needed to be written, depending on the considered GPDMA request signal. The GPDMA performs a 32‑bit aligned access to the related data or control register.
The 8-bit data receive register must be read with a programmed 8-bit source data width, with a fixed addressing, and a 32-bit aligned access.
The 8-bit data transmit register must be written with a programmed 8-bit destination data width, with a fixed addressing, and a 32-bit aligned access.
The 32-bit control word must be written with a programmed 32-bit destination data width, and with a fixed addressing (if consecutive updates are required).
One of the channels with 2‑word FIFO can be allocated (as well one of the channels with 8‑word FIFO), especially if the memory to be written is an external memory.
The table below summarizes the main peripheral characteristics: different hardware request signals to the GPDMA, the peripheral bus on which the peripheral is connected, and the corresponding peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| i2c_rx_dma |
APB1 :
APB3:
APB4: I2C4 for STM32N6 | None | Read 8-bit I2C_RXDR | Request for a new received data byte to be read by the GPDMA. Must be read with a 32-bit aligned address. |
| i2c_tx_dma | Write 8-bit I2C_TXDR | Request for a new data byte to be written by the GPDMA for transmission. Must be read with a 32-bit aligned address. | ||
| i2c_evc_dma | Write 32-bit I2C_CR2 | Request for a new command word to be written by the GPDMA. |
The table below shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/ destination port | GPDMA source/ destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 01 | i2c_tx, i2c_rx: 8‑bit i2c_evc: 32-bit | 1 | Channels with 2‑word FIFO |
GPDMA1 port 0 is optimized to connect the APB1 I2Cx since there is a direct connection (at architecture level) from the GPDMA to the APB bridge on which the I2C is connected. There is less latency and fast response time for a given priority level The default recommended setting also applies to APB3 because it balances bandwidth over each port (port 0 for peripheral access, port 1 for memory access). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. For improved burst performances, the channel allocation can be one of the channels with 8‑word FIFO. |
1 Port 0 is selected for reading/writing APB1 peripheral register (direct connection), and port 1 for accessing to memory. By default, and if no specific requirements, it can be the same for APB3 (balanced traffic over the two ports).
Improved inter-integrated circuit interface (I3C)
The STM32 devices embed up to two I3C on the APB bus
The I3C interface handles the communication between this device and others: sensors and host processor(s), connected on an I3C bus. The I3C bus is a two‑wire, serial single‑ended, multidrop bus, intended to improve a legacy I2C bus.
The I3C peripheral is not burst capable when doing GPDMA transfer. All transfers must be handled in single data mode by the GPDMA controller, since the I3C peripheral sends a new GPDMA request each time:
- Either a control word is needed to be written.
- Or a status word is needed to be read.
- Or a data byte/word is needed to be written or read depending on the considered GPDMA request signal.
The GPDMA performs a 32-bit aligned access to the related data or control register.
The 32-bit control word must be written with a programmed 32-bit destination data width, and with a fixed addressing.
The 32-bit status word must be read with a programmed 32-bit source data width, and with a fixed addressing.
The data transmit register can be accessed by bytes (via I3C_TDR) or by words (via I3C_TDWR). It must be written with a programmed respectively 8-bit or 32-bit destination data width, with a fixed addressing, and a 32-bit aligned access.
The allocated DMA channel for the data receive bytes/words must be programmed with PFREQ = 1 in DMA_CxTR2. This is to support that an external I3C device may early complete the data transmission. For the channels where the PFREQ field is present, one of these channels must be allocated.
The table below summarizes the main peripheral characteristics: different hardware request signals to the GPDMA, the peripheral bus on which the peripheral is connected, and the corresponding peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| i3cx_rx_dma1 | APB1 for I3C1 | 8‑byte RX-FIFO | Read 8‑bit I3C_RDR or 32‑bit I3C_RDWR | Received data must be read with a 32‑bit aligned address. |
| i3cx_tx_dma1 | None | 8‑byte TX-FIFO | Read 8‑bit I3C_TDR or 32‑bit I3C_TDWR | To be transmitted data must be written with a 32‑bit aligned address. |
| i3cx_tc_dma1 | 2‑word C-FIFO | Write 32‑bit I3C_CR | To be transmitted control word. | |
| i3cx_rs_dma1 | 2‑word S-FIFO | Read 32‑bit I3C_SR | Received status word |
The table below shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/destination port | GPDMA source/ destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 02 |
i3c_tx_dma/i3c_rx_dma:
i3c_tc_dma/i3c_rs_dma: | 1 | Channels with 2‑word FIFO | GPDMA port 0 is optimized to connect the APB1 I3C1 since there is a direct connection (at architecture level) from the GPDMA to the APB bridge on which the I3C is connected. There is less latency and fast response time for a given priority level. The default recommended setting also applies to APB3 because it balances bandwidth over each port (port 0 for peripheral access, port 1 for memory access). The GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. For improved burst performances, the channel allocation can be one of the channels with 8‑word FIFO. |
1 x = 1 or 2.
2 Port 0 is selected for reading/writing APB1 peripheral register (direct connection), and port 1 for accessing to memory. By default, and if no specific requirements, it can be the same for APB3 (balanced traffic over the two ports).
Universal synchronous/asynchronous/low-power receiver transmitter (USART/UART/LPUART)
The STM32 devices embed multiple USART/UART/LPUART instances. Each instance can have a GPDMA channel linked to the transmit or receive queue.
This peripheral is not burst capable when doing GPDMA transfer. All transfers must be handled in single data mode by the GPDMA controller, since the USART/UART sends a new GPDMA request each time a data needs to be written/read, depending on the considered GPDMA request signal. The GPDMA performs a 32-bit aligned access to the related data register.
The 9-bit data receive register must be read with a programmed 8-, 16-, or 32-bit source data width, with a fixed addressing, and with a 32-bit aligned access, depending on the format.
The 9-bit data transmit register must be written with a programmed 8-, 16-, or 32-bit destination data width, with a fixed addressing, and with a 32-bit aligned access, depending on the format.
One of the channels with 2‑word FIFO can be allocated (as well one of the channels with 8‑word FIFO), especially if the memory to be written is an external memory.
The USART/UART/LPUART have transmit and receive FIFO in order to avoid as much as possible overrun/underrun situation which may break the data transfer flow. Table 21 U(S)ART and LPUART peripheral information summarizes the main peripheral characteristics: the different hardware request signals to the GPDMA, the peripheral bus on which the peripheral is connected, and the corresponding peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| (lp)u(s)art_rx_dma |
APB1:
APB2:
APB3:
APB4:
| 8x 12-bit width RXFIFO (9 bits for Rx data + 3 bits for errors) 8x 9-bit width TXFIFO1 | Read USART_RDR or LPUART_RDR | Request for a new received data to be read by the GPDMA. Must be read with a 32-bit aligned address, whatever is the data width. |
| (lp)u(s)art_tx_dma | Write USART_TDR or LPUART_TDRR | Request for a new data to be written by the GPDMA for transmission. Must be written with a 32-bit aligned address, whatever is the data width. |
The table below shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/ destination port | GPDMA source/ destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 02 | 16- or 32-bit read/write in 9-bit mode and 8-, 16-, or 32-bit read/write in 8-bit and 7-bit modes | 1 | Channels with 2‑word FIFO |
GPDMA1 port 0 is optimized to connect the APB1/APB2 U(S)ART since there is a direct connection (at architecture level) from the GPDMA to the APB bridge on which the U(S)ART is connected. There is less latency and fast response time for a given priority level. The default recommended setting also applies to APB3 because it balances bandwidth over each port (port 0 for peripheral access, port 1 for memory access). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. For improved burst performances, the channel allocation can be one of channels with 8‑word FIFO. |
1 FIFO can be enabled/disabled by software.
2 Port 0 is selected for accessing APB1/APB2 peripheral register (direct connection), and port 1 for accessing to memory. By default, and if no specific requirements, it can be the same for APB3 (balanced traffic over the two ports).
Serial peripheral interface (SPI)
In STM32 devices embed multiple SPI instances. All of them can have a GPDMA channel linked to the transmit or receive queue.
The peripheral is not burst capable when doing GPDMA transfer. All transfers must be handled in single data mode by the GPDMA controller, since the peripheral sends a new GPDMA request each time a data is needed to be written/read, depending on the considered GPDMA request signal. Then GPDMA performs a 32-bit aligned access to the related data register.
The data receive register must be read with a programmed 8-, 16-, or 32-bit source data width, with a fixed addressing, and a 32-bit aligned access.
The data transmit register must be written with a programmed 8-, 16-, or 32-bit destination data width, with a fixed addressing, and a 32-bit aligned access.
The SPI has a transmit and a receive FIFO in order to avoid as much as possible overrun/ underrun situation which may break the data transfer flow.
The SPI can pack/unpack the received/to-be-transmitted byte-stream versus the written/read 32-bit word stream at the data register level. It is recommended to optimize the data transfer to reduce the overall system latency, and to decrease the bus bandwidth on the GPDMA master port (recommended port 0), which is allocated to access the SPI_TXDR/SPI_RXDR register. Decrease the load on the APB peripheral bus is also recommended when applicable. It is recommended to perform 32-bit data width access to the peripheral register to decrease by a ratio of 4 the bus traffic vs a byte-stream access on the peripheral side.
A channel with 2‑word FIFO can be allocated (as well a channel with 8‑word FIFO), especially if the memory to be written is an external memory.
The table below summarizes the main peripheral characteristics: different hardware request signals to the GPDMA, peripheral bus on which the peripheral is connected, and the corresponding peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| spiy_rx_dma1 |
STM32H5
STM32U5
STM32N6 (APB1 for SPI2/3, APB2 for SPI1/4/5, APB4 for SPI6)
STM32U3
STM32H7Rx/7Sx | 16-byte RXFIFO and TXFIFO for SPI1 and SPI2 8-byte RXFIFO and TXFIFO for SPI32 | Read SPI_RXDR | Request for a new received data to be read by the GPDMA. Must be read with a 32-bit aligned address, whatever is the data width. |
| spiy_tx_dma1 | Write SPI_TXDR | Request for a new data to be written by the GPDMA for transmission. Must be written with a 32-bit aligned address, whatever is the data width. |
Table 24 GPDMA recommendation for SPI shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/ destination port | GPDMA source/ destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 03 | 32-bit recommended. If not applicable, 8-, or 16-bit. | 1 | Channels with 2‑word FIFO |
GPDMA1 port 0 is optimized to connect the APB1 SPI since there is a direct connection (at architecture level) from the GPDMA to the APB bridge on which the SPI is connected. There is less latency and fast response time for a given priority level. The default recommended setting also applies to APB3 because it balances bandwidth over each port (port 0 for peripheral access, port 1 for memory access). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. For improved burst performances, the channel allocation can be one of channels with 8‑word FIFO. |
1 2. y = 1 to 6.
2 FIFO can be enabled/disabled by software.
3 Port 0 is selected for accessing APB1 peripheral register (direct connection), and port 1 for accessing to memory. By default, and if no specific requirements, it can be the same for APB3 (balanced traffic over the two ports).
Serial audio interface (SAI)
The STM32 devices (excluding STM32H523/533 and STM32H543/553) embed up to two SAI instances (SAI1 and SAI2) connected to APB2. Each SAI has two subblocks A and B. Each subblock has a dedicated GPMDA request, its own FIFO, and can have one GPDMA channel.
The peripheral is not burst capable when doing GPDMA transfer. All transfers must be handled in single data mode by the GPDMA controller, since the peripheral sends a new GPDMA request each time an audio data is needed to be written/read. Then GPDMA performs a read/write access to the related 32-bit data register, with a programmed source/destination data width of 32-bit and a fixed addressing.
One of the channels with 2‑word FIFO can be allocated (as well one of the channels with 8‑word FIFO), especially if the memory to be written is an external memory.
The table below summarizes the main peripheral characteristics: different hardware request signals to the GPDMA, peripheral bus on which the peripheral is connected, and the corresponding peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| saix_a_dma1 | APB2 | 8-word FIFO | Read/write 32-bit SAI_ADR | Subblock A requests for a new 32-bit data to be read/written by the GPDMA. |
| saix_b_dma1 | Read/write 32-bit SAI_BDR | Subblock B requests for a new 32-bit data to be read/written by the GPDMA. |
Table 26 GPDMA recommendation for SAI shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/ destination port | GPDMA source/ destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 02 | 32-bit | 1 | Channels with 2‑word FIFO |
GPDMA1 port 0 is optimized to connect the APB2 SAI since there is a direct connection (at architecture level) from the GPDMA to the APB bridge on which the SAI is connected. There is less latency and fast response time for a given priority level. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. For improved burst performances, the channel allocation can be one of channels with 8‑word FIFO |
1 1. X = 1 or 2.
2 Port 0 is selected for accessing APB2 peripheral register (direct connection), and port 1 for accessing to memory.
SPDIF receiver interface (SPDIFRX)
There is one instance of the SPDIFRX in the STM32H7Rx/7Sx and STM32N6 devices.
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC‑60958 and IEC‑61937. These standards support simple stereo streams up to high sample rate, and compressed multichannel surround sound, such as those defined by Dolby or DTS.
This peripheral can handle two DMA requests, handled over two DMA channels:
- A DMA channel dedicated to the transfer of audio samples
- A DMA channel dedicated to the transfer of IEC60958 channel status and user Information
The DMA mode for the data can be enabled for reception by setting the RXDMAEN bit in the SPDIFRX_CR register. In this case, as soon as the SPDIFRX_FMTx_DR is not empty, the SPDIFRX interface sends a transfer request to the DMA. The DMA reads the data received through the SPDIFRX_FMTx_DR register.
For the channel status and user information, the DMA read he SPDIFRX channel status register SPDIFRX_CSR.
The peripheral is not burst capable, and DMA must be programmed for reading 32-bit single words.
The table below summarizes the main peripheral characteristics: hardware request signal to the GPDMA, peripheral bus on which the SPDIFRX is connected, and peripheral register from/to which the GPDMA must be programmed to read or write.
| Peripheral request to GPDMA | Peripheral bus |
Peripheral FIFO | Peripheral register access | Comments |
|---|---|---|---|---|
| spdifrx_dat_dma | APB1 | None | 32-bit read to SPDIFRX_FMTx_DR | Request to read the 32-bit data register. |
| spdifrx_ctrl_dma | 32-bit read to SPDIFRX_CSR | Request to read the 32-bit channel status register. |
Table 28 GPDMA recommendation for SPDIFRX shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source port | GPDMA source burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 01 | 32-bit | 1 | Channels with 2‑word FIFO |
The default recommended setting also balances bandwidth over each port (source port 0 to read from peripheral, destination port 1 to write to memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. |
1 By default, port 0 is recommended to access peripheral register, and port 1 to access memory if no specific requirements.
USB Type-C/USB Power Delivery interface (UCPD)
There is one instance of the UCPD in the STM32H5, STM32U5, STM32N6 and STM32H7Rx/7Sx devices.
The UCPD has one GPDMA request for the transmission, and another one for the reception.
The peripheral is not burst capable when doing GPDMA transfer and does not embed any FIFO. All transfers must be handled in single data mode by the GPDMA controller, since the peripheral sends a new GPDMA request each time a data is needed to be written/read. Then GPDMA performs a read/write access to the related 32-bit data register, with a programmed source/destination data width of 8-bit and a fixed addressing at the 32-bit aligned register address.
One of the channels with 2‑word FIFO can be allocated (as well one of the channels with 8‑word FIFO), especially if the memory to be written is an external memory.
The table below summarizes the main peripheral characteristics: different hardware request signals to the GPDMA, the peripheral bus on which the peripheral is connected, and the corresponding peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| ucpd_rx_dma | APB1 | 8-word FIFO | Read 8-bit UCPD_RXDR | Request for a new received 8-bit data to be read by the GPDMA. Must be read with a 32-bit aligned address. |
| ucpd_tx_dma | Write 8-bit UCPD_TXDR | Request for a new 8-bit data to be written by the GPDMA for transmission. Must be written with a 32-bit aligned address. |
Table 30 GPDMA recommendation for UCPD shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/ destination port | GPDMA source/ destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 01 | 8-bit | 1 | Channels with 2‑word FIFO |
GPDMA1 port 0 is optimized to connect the APB1 UCPD since there is a direct connection (at architecture level) from the GPDMA to the APB bridge on which the UCPD is connected. There is less latency and fast response time for a given priority level. It is better to use with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. For improved burst performances, the channel allocation can be one of channels with 8‑word FIFO. |
1 Port 0 is selected for accessing APB1 peripheral register (direct connection), and port 1 for accessing to memory.
Audio/multi-function digital filter (ADF/MDF)
The STM32U5, STM32N6 and STM32H5Ex/5Fx devices have both ADF and MDF, while the STM32H7Rx/7Sx and STM32U3 devices have ADF only.
ADF and MDF have DMA capabilities to unload the software for the data transfer read from the peripheral and written to the memory. The MDF is an AHB1 peripheral for STM32U5 and STM32H5Ex/5Fx devices, and an AHB2 for STM32N6 and STM32H5Ex/5Fx devices. The ADF an AHB3 peripheral for STM32U5 devices and an AHB1 peripheral for STM32H7Rx/7Sx and STM32U3 devices. There is one GPDMA request per audio digital filter: one for ADF, six for MDF.
The ADF/MDF are not burst capable when doing GPDMA transfers, even if an embedded FIFO for each filter is present. All transfers need to be handled in single data mode by the GPDMA controller since the ADF/MDF sends a DMA request each time one 32-bit register data (containing one 24-bit sample) is available, or two 32-bit register data (containing two 32-bit samples) are available, depending on the programmed FIFO threshold. Then GPDMA reads the 32‑bit ADF_DFLT0DR / MDF_DFLTyDR (y = 0 to 7) digital filter 0 data register. This 32-bit data register must be accessed with a programmed source data width being 32-bit and with a fixed addressing.
The embedded FIFO is in the audio kernel clock, hence a few extra latencies is added for resynchronization with the AHB clock domain.
A channel with 2‑word FIFO can be allocated. A channel with 8‑word FIFO may also be allocated if the accessed memory is external.
The table below summarizes the main peripheral characteristics: hardware request signals to the GPDMA, peripheral bus on which the peripheral is connected, and peripheral register from/to which the GPDMA must be programmed to read.
| Peripheral request to GPDMA | Peripheral bus |
Peripheral FIFO | Peripheral register access | Comments |
|---|---|---|---|---|
| adf1_flt0_dma |
AHB3 for STM32U5 AHB1 for STM32H7Rx/7Sx and STM32U3 AHB2 for STM32N6 and STM32H5Ex/5Fx | 8x 24-bit width FIFO | Read 32-bit ADF_DFLT0DR | Request for a new received audio data from filter 0 to be read by the GPDMA |
| mdf_flt0_dma mdf_flt1_dma mdf_flt2_dma mdf_flt3_dma mdf_flt4_dma mdf_flt5_dma | AHB2 | 8x 24-bit width FIFO for each filter | Read corresponding 32-bit MDF_DFLTyDR (y = 0 to 5) | Request for a new received audio data from filter y (y = 0 to 5) to be read by the GPDMA |
The table below shows the supported and recommended GPDMA settings to be used for serving the ADF/MDF peripheral request: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source port | GPDMA source burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 0 1 | 32-bit | 1 | Channels with 2‑word FIFO |
The default recommended setting also balances bandwidth over each port (source port 0 to read from peripheral, destination port 1 to write to memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations For improved burst performances, the channel allocation can be one of channels with 8‑word FIFO. |
1 If no specific requirements, by default, port 0 is selected for reading peripheral register, and port 1 for writing to memory.
Filter math accelerator (FMAC)
The STM32H562/563/573/5Ex/5Fx/543/553 and STM32U5 devices embed one FMAC instance.
The FMAC performs 16-bit fixed-point arithmetic operations on vectors. It is GPDMA capable for read/write channels. The memory embedded in the FMAC is used to split, by user configuration, the size and the allocation of the 256 x 16-bit local memory for each buffer (X1, X2, and Y). The GPDMA requests are based on the X1 buffer free‑space availability (not full) in order to ask for vector preloading to get the data when required. This avoids stalling the calculation if the data is not yet present into the local memory.
The FMAC is not burst capable when doing GPDMA transfer, even if an embedded FIFO is present. All transfers must be handled in single data mode by the GPDMA controller, since the FMAC sends a new GPDMA request each time a 16-bit data is needed to be read/written. Then GPDMA performs a 32-bit aligned access to read/write from/to the 16-bit FMAC_RDATA/FMAC_WDATA register. This data register must be accessed with a programmed source/destination data width of 16-bit and with a fixed addressing.
No burst performance can be achieved for the read/write access to the FMAC. A channel with 2‑word FIFO can be allocated, unless a channel with 8‑word FIFO is free/unallocated and the required performances in terms of bandwidth are significant for this AHB peripheral. A channel with 8‑word FIFO may be also allocated if the accessed memory is external.
The table below summarizes the main peripheral characteristics: hardware request signal to the GPDMA, peripheral bus on which the peripheral is connected, and peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| fmac_read_dma | AHB1 | 256x 16-bit local memory shareable with X1, X2, and Y buffers1 | Read 16-bit FMAC_RDATA | Request for a new computed 16-bit output data to be read by the GPDMA. Must be read with a 32-bit aligned address. |
| fmac_write_dma | Write 16-bit FMAC_WDATA | Request for a new 16-bit input data to be written by the GPDMA for computation. Must be written with a 32-bit aligned address. |
Table 34 GPDMA recommendation for FMAC shows the supported and recommended GPDMA settings to be used for serving the FMAC peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/ destination port | GPDMA source/ destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 02 | 16-bit | 1 |
Channels with 2‑word FIFO | The default recommended setting also balances bandwidth over each port (source port 0 to read from peripheral, destination port 1 to write to memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. For improved burst performances, the channel allocation can be one of channels with 8‑word FIFO. |
1 Each partitioning is user configurable.
2 By default, port 0 is recommended to access peripheral register, and port 1 to access memory, if no specific requirements.
CORDIC coprocessor
There is one instance of the CORDIC in the STM32H5 (excluding STM32H523/533), STM32U5, and STM32H7Rx/7Sx devices.
The CORDIC provides hardware acceleration of mathematical functions commonly used in motor control, metering, signal processing, and many other tasks, with 16- or 32-bit fixed-point. The GPDMA transfers can take place in read and write mode.
The CORDIC allows multiple register read/write by the GPDMA:
- ARG1 and possibly ARG2 as input arguments (depending on NARGS in CORDIC_CSR)
If both arguments need to be input for computation, they are input through two single GPDMA requests.
- RES1 and RES2 as primary and secondary results, respectively (depending on NRES in CORDIC_CSR)
If both computed results need to be read by the GPDMA, the CORDIC asserts two GPDMA requests in single mode.
The data width can be one of the following:
- 16-bit format
The primary argument ARG1 is written to the least significant half-word whereas the secondary argument ARG2 is written to the most significant half-word. Thanks to this data packing, the argument is sent within a single GPDMA data transfer, which improves the bus bandwidth by minimizing the amount of DMA transfers to perform.
- 32-bit format
There are two GPDMA data accesses to fill the two arguments (if CORDIC configuration requires two arguments).
The table below summarizes the main peripheral characteristics: hardware request signal to the GPDMA, peripheral bus on which the peripheral is connected, and peripheral register from/to which the GPDMA must be programmed to read/write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| cordic_read_dma/cordic_rd_dma | AHB1 for all STM32 devices and AHB2 for STM32H7Rx/7Sx | None | Read CORDIC_RDATA | Request for a new computed output data to be read by the GPDMA. Must be read with a 32-bit aligned address. |
| cordic_write_dma/cordic_wr_dma | Write CORDIC_WDATA | Request for a new input data to be written by the GPDMA for computation. Must be written with a 32-bit aligned address. |
The table below shows the supported and recommended GPDMA settings to be used for serving the FMAC peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/ destination port | GPDMA source/ destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 01 | 16- or 32-bit | 1 |
Channels with 2‑word FIFO | The default recommended setting also balances bandwidth over each port (source port 0 to read from peripheral, destination port 1 to write to memory). GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. It is better to use channel with linear‑addressing mode to let the other channels free for 2D operations, memory copies, or for peripherals requesting higher internal DMA FIFO size to manage burst operations. For improved burst performances, the channel allocation can be one of channels with 8‑word FIFO. |
1 By default, port 0 is recommended to access peripheral register, and port 1 to access memory, if no specific requirements.