The general purpose I/Os (GPIO) or low-power general-purpose I/Os (LPGPIO) can also be controlled by the GPDMA, even if there is no specific hardware GPDMA request. The GPDMA in memory‑to‑memory configuration can control the I/Os (as well as the data in output for instance). For the LPGPIOs, the LPDMA can be functional even down to Stop 2 mode, to control up to 16 I/Os.
The STM32 devices embed up to three instances (OCTOSPI1 and OCTOSPI2/XSPI1, XSPI2, XSPI3) of the Octo-SPI/XSPI interfaces. Three XSPI instances are available only on STM32N6 devices.
The OCTOSPI/XSPI support most external memories, such as serial PSRAMs, serial NAND and serial NOR Flash memories, HyperRAM™ and HyperFlash™ memories.
The OCTOSPI/XSPI in Indirect mode propose a DMA mode for read/write data transfers to their peripheral registers. The OCTOSPI/XSPI are burst capable via their embedded 64-byte FIFO for XSPI and 32-byte FIFO for OCTOSPI.
The GPDMA request signal (no GPDMA request signal for STM32H7Rx/7Sx), is used by the hardware to request a new burst to be read/written by the GPDMA whenever the peripheral needs it. The GPDMA reads/writes the OCTOSPI_DR/XSPI_DR data register. This 32-bit data register can be accessed by a 32-bit word-aligned read access, with a programmed source data width being typically either 8-, 16-, or 32-bit and with a fixed addressing.
The burst is defined on the OCTOSPI/XSPI sides by programming the FIFO threshold FTHRES[4:0] in OCTOSPI_CR /XSPI_CR with a 1 to 32-byte burst size for OCTOSPI and 1 to 64-byte burst size for XSPI.
The allocated GPDMA channel is recommended to be one of the channel with 8‑word FIFO. It can perform bursts of a size equal to half of its FIFO size (up to 16-byte, 8-half-word, or 4-word bursts). This means programming a 15 decimal value on the OCTOSPI/XSPI sides (FTHRES[:0] = 15).
Using a 32-bit data width is preferred for minimizing the AHB bus load, unless the application requires a byte-level or half-word data management.
The table below summarizes the main peripheral characteristics: hardware request signal to the GPDMA, peripheral bus on which the OCTOSPI/XSPI are connected, and peripheral register from/to which the GPDMA must be programmed to read or write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
|
ospiy_dma/octospiy_dma/xspy_dma | AHB_OCTOSPI (dedicated target of bus matrix) | 32-byte FIFO | Read/Write OCTOSPI_DR | It is recommended to access OCTOSPI_DR with a programmed 4-word burst, when a 32-bit data width is applicable. |
Table 53 GPDMA recommendation for OCTOSPI shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length (only single data mode).
| GPDMA source/destination port | GPDMA source/destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 11 | 32-bit (preferred) else 8- or 16-bit | 4-word (preferred) or 8-half-word or 16-byte | Channel with 8‑word FIFO for burst performances | The default port allocation (port 0 to peripheral, port 1 to external memory) enables to balance the bandwidth over each port for memory-to-peripheral and peripheral-to-memory transfers. It also avoids bursts to memory from impacting directly the latency of a peripheral access. GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. For improved burst performances, the channel allocation can be one of the channels with 8‑word FIFO. |
There is one instance of the Hexa-SPI interface (HSPI1) in the STM32U59x/5Ax/5Fx/5Gx devices.
The HSPI supports most external memories, such as serial PSRAMs, serial NAND/NOR flash memories, HyperRAM™ and HyperFlash™ memories.
The HSPI in indirect mode proposes a DMA mode for read/write data transfers to its peripheral registers. The HSPI is burst capable via its embedded 64-byte FIFO.
The GPDMA request signal (hspi1_dma) is used by the hardware to request a new burst to be read/written by the GPDMA whenever the peripheral needs it. The GPDMA reads/writes the HSPI_DR data register. This 32-bit data register can be accessed by a 32-bit word-aligned read access, with a programmed 8-, 16-, or 32-bit source data width, and with a fixed addressing.
The burst is defined on the HSPI side by programming the FIFO threshold FTHRES[5:0] in HSPI_CR with a 1-to 64-byte burst size.
The allocated GPDMA channel is recommended to be one of the channels with 8‑word FIFO. It can then perform GPDMA bursts of a size equal to half of its FIFO size (up to 16-byte, 8-half-word, or 4-word). This means programming a 15 decimal value on the HSPISPI side (FTHRES[5:0] = 15).
Using a 32-bit data width is preferred for minimizing the AHB bus load, unless the application requires byte-level or half-word data management.
The table below summarizes the main peripheral characteristics: hardware request signal to the GPDMA, peripheral bus on which the HSPI is connected, and peripheral register from/to which the GPDMA must be programmed to read or write.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| hspi1_dma | AHB_HSPI1 (dedicated target of bus matrix) | 64-byte FIFO | Read/write HSPI_DR | It is recommended to access HSPI_DR with a programmed 4-word burst, when a 32-bit data width is applicable. |
Table 55 GPDMA recommendation for HSPI shows the supported and recommended GPDMA settings to be used for serving the different peripheral requests: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length.
| GPDMA source/destination port | GPDMA source/destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 11 | 32-bit (preferred) else 8- or 16-bit | 4-word (preferred) or 8-half-word or 16-byte | Channel with 8‑word FIFO for burst performances | The default port allocation (port 0 to peripheral, port 1 to external memory) enables to balance the bandwidth over each port for memory-to-peripheral and peripheral-to-memory transfers. It also avoids bursts to memory from impacting directly the latency of a peripheral access. GPDMA port selection for the source and the destination transfers can be changed to fit specific application needs. For improved burst performances, the channel allocation can be one of the channels with 8‑word FIFO. |
The FSMC is not available on STM32H503, STM32U535/545, STM32H543/553, STM32H5Ex/5Fx and STM32H7Rx/7Sx devices.
There is no specific request from the FMC to ask for a GPDMA transfer. The GPDMA may be configured to perform data transfer for memory‑to‑memory transfers, with the FMC being either the source memory or the destination memory.
If the external memory is asynchronous, it is recommended to configure the GPDMA to perform transfers in single data mode only, and with a data width equal to the interface bus width of the memory (8- or 16-bit). Programming bursts must be avoided for not stalling the AHB bus and the allocated GPDMA port during a long time, and for not forcing other GPDMA requests to be served with a high latency.
If the external memory is a synchronous memory, read must also be configured as single transactions of 8- or 16‑bit data width, for not stalling the AHB bus.
If the external memory is a synchronous memory, the FSMC must be written by GPDMA bursts, because the FMC implements a 16-word write FIFO. When this FIFO is full, the FSMC stalls the AHB bus and the allocated GPDMA until the burst completion. The memory must then be written by GPDMA blocks up to a size which corresponds to the write FIFO being full. The software must wait for the FSMC to have its FIFO empty before enabling another block transfer. The allocated GPDMA channel must be a channel with 8‑word FIFO, to be able to perform either 4‑word, 8‑half‑word, or 16‑byte bursts.
| Peripheral request to GPDMA | Peripheral bus | Peripheral FIFO (unit, size) | Peripheral register access | Comments |
|---|---|---|---|---|
| - | AHB_FMC (dedicated target of bus matrix) | 16-word write FIFO | - | Read/write access directly to the external FMC memory space |
Table 57 GPDMA recommendation for FMC on read shows the supported and recommended GPDMA settings to be used for serving the FMC: GPDMA port allocation, GPDMA channel allocation, and programmed GPDMA bursts in terms of data width and burst length.
| GPDMA source port | GPDMA source burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 11 | 8- or 16-bit | 1 | Channel with 2‑word FIFO | Read by single The default port allocation (port 0 to peripheral, port 1 to memory) also balances the bandwidth over each port for memory-to-peripheral and peripheral‑to‑memory transfers. GPDMA port selection for the FMC source transfer can be changed to fit specific application needs. |
| GPDMA destination port | GPDMA destination burst | GPDMA channel | Comments | |
|---|---|---|---|---|
| GPDMA data width | GPDMA burst length | |||
| Port 12 | 32-bit (preferred) else 8- or 16-bit | 4-word (preferred) or 8-half-word or 16-byte | Channel with 8‑word FIFO for write burst performances | The default port allocation (port 0 to peripheral, port 1 to memory) enables to balance the bandwidth over each port for memory‑to‑peripheral and peripheral‑to‑memory transfers. It also avoids write bursts to memory from impacting directly the latency of a peripheral access. GPDMA port selection for the FMC destination transfer can be changed to fit specific application needs. For improved write burst performances, the channel allocation can be one of the channels with 8‑word FIFO. |