AN5593 · Application noteHow to use the GPDMA for STM32 MCUs
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AHB-to-APB bridges

AHB-to-APB bridges

An APB peripheral generates a hardware request to the GPDMA. The allocated and configured GPDMA channel generates either a read transfer from the corresponding APB register (in memory-to-peripheral mode), or a write transfer to the APB register (in peripheral-to-memory mode).

Peripherals, memories, and GPDMA configuration lists the APB peripherals working in DMA mode, and their corresponding GPDMA programming. It is recommended that the GPDMA generates only single transfers (GPDMA burst of length 1) as a read or as a non‑bufferable write to an APB register.

AHB-to-APB bridge arbitration

The APB1 and APB2 peripherals can be accessed concurrently either from the GPDMA master port 0 via the direct path, or from the CPU or the GPDMA master port 1 via the AHB switch on the AHB1 output path of the bus matrix.

A concurrent access is resolved at AHB-to-APB bridge level, by a round-robin arbitration with a quantum of one APB transfer.

There is no arbitration inside the AHB-to-APB bridge in front of the APB3.

AHB-to-APB clock ratio

The transfer latency to an APB peripheral register is impacted by the clock ratio between APB and AHB clocks. The best case is achieved with a ratio of 1. When the APB clock runs lower than the AHB clock, the latency is increased.

AHB-to-APB bridge transfer latency

From the AHB interface of the AHB-to-APB bridge, a GPDMA transfer execution time/latency, as a single, to the APB peripheral register by the GPDMA is shown in the table below (when there is no concurrent/pending transfer from another master to an APB1 or APB2 peripheral).
Table 61. AHB-to-APB bridge read/write (single) transfer latency to APB register
AHB/APB clock ratioRead latency (AHB clock cycles)Write latency (AHB clock cycles)
1:144 to 5
1:25 to 6
1:49 to 12
1:817 to 24
The GPDMA adds one clock-cycle latency, and the bus arbitration may add one clock cycle. The table below details the GPDMA transfer latency for completion of a single read/write to an APB peripheral register, provided that:
  • neither another GPDMA channel, nor the CPU generates a concurrent traffic to the addressed APB1/2/3 bus
  • the APB peripheral does not insert any wait state
Table 62. GPDMA read/write transfer latency to APB register
AHB/APB clock ratioRead latency (AHB clock cycles)Write latency (AHB clock cycles)
1:15 to 6
1:26 to 8
1:410 to 14
1:818 to 26

Revision history

Table 63. Document revision history
DateVersionChanges
24-Sept-20211Initial release.
3-Dec-20212Updated the whole content of this document.
13-Dec-20213Updated Section 3.5.1 Low-power timers (LPTIM1/2/3/4).
22-Aug-20224Document scope enlarged to all devices of the STM32U5 Series

Updated:

  • Section 3.2.1 Analog-to-digital converter ADC1/ADC12
  • New Section 3.3.2 JPEG codec
  • Section 3.4.2 Inter-integrated circuit interface (I2C)
  • Section 3.4.3 Universal synchronous/asynchronous/low-power receiver transmitter (USART/UART/LPUART)
  • Section 3.8.1 Octo-SPI interface (OCTOSPI)
  • New Section 3.8.2 Hexa-SPI interface (HSPI)
  • Section 3.8.3 Flexible static memory controller (FSMC)
  • Section 4.1 System bus
14-Mar-20245Document scope enlarged to add STM32H5 series and STM32H7R3/7S3 and STM32H7R7/7S7 lines.

Updated document title and all topics.

Added:
  • Section 3.2.2: Analog-to-digital converter ADC4
  • Section 3.4.3: Improved inter-integrated circuit interface (I3C)
  • Section 3.4.7: SPDIF receiver interface (SPDIFRX)
  • Section 3.6.4: Cryptographic processor (CRYP)

Removed Section System bus.

01-Jul-20246Updated the whole document to cover the STM32H523/533 devices.
30-Jan-20257
  • Document scope enlarged to cover STM32 devices
  • Added STM32U3 series devices
  • Corrected typos
27-Feb-20268

Document scope enlarged to cover STM32N6 series.

Added configurations for STM32H5Ex/5Fx line.

Updated:
16-Jun-20269Updated: