Advanced RTC features

The following tables summarize the RTC features available on each STM32 MCU.

Table 4. Advanced features for RTC2 type
Features			STM32F0	STM32F2	STM32F3	STM32F4	STM32F7	STM32L0	STM32L1		STM32L4^¹ - STM32L4+^²	STM32H72/H73/H74/H75	STM32WB	STM32WB0
Features			STM32F0	STM32F2	STM32F3	STM32F4	STM32F7	STM32L0	Cat. 2/3/4/5/6	Cat. 1	STM32L4^¹ - STM32L4+^²	STM32H72/H73/H74/H75	STM32WB	STM32WB0
RTC clock source (LSE, LSI, HSE with prescaler)			X	X	X	X	X	X	X	X	X	X	X	X
Prescalers	Asynchronous (number of bits)		X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)
Prescalers	Synchronous (number of bits)		X (15)	X (13)	X (15)	X (15)	X (15)	X (15)	X (15)	X (13)	X (15)	X (15)	X (15)	X (15)
Calendar	Time	12 h/24 h format	X	X	X	X	X	X	X	X	X	X	X	X
		Hour, minute, second	X	X	X	X	X	X	X	X	X	X	X	X
		Subsecond	X	N/A	X	X	X	X	X	N/A	X	X	X	X
	Date		X	X	X	X	X	X	X	X	X	X	X	X
	Daylight operation		X	X	X	X	X	X	X	X	X	X	X	X
	Bypass shadow registers		X	N/A	X	X	X	X	X	N/A	X	X	X	X
	V_BAT mode		X	X	X	X	X	N/A	N/A	N/A	X	X	X	X
Alarm	Alarms available	Alarm A	X	X	X	X	X	X	X	X	X	X	X	X
	Alarms available	Alarm B	N/A	X	X	X	X	X	X	X	X	X	X	N/A
	Time	12 h/24 h format	X	X	X	X	X	X	X	X	X	X	X	X
		Hour, minute, second	X	X	X	X	X	X	X	X	X	X	X	X
		Subsecond	X	N/A	X	X	X	X	X	N/A	X	X	X	X
	Date or week day		X	X	X	X	X	X	X	X	X	X	X	X
Tamper detection	Configurable input mapping		X	X	X	X	X	X	N/A	N/A	X	X	X	X
	Configurable edge detection		X	X	X	X	X	X	X	X	X	X	X	N/A
	Configurable level detection (filtering, sampling, and precharge configuration on tamper input)		X	N/A	X	X	X	X	X	N/A	X	X	X	N/A
	Number of tamper inputs		2^³	2	2	2	3	3	3	1	3	3	3	N/A
	Number of tamper events		0	1	2	2	3	3	3	1	3	3	3	N/A
	V_BAT mode pins (inputs)		1	1	1	2	2	N/A	N/A	N/A	3	3	3	N/A
Timestamp	Configurable input mapping		X	X	X	X	X	X^⁴	N/A	N/A	X^⁴	X	X^⁴	N/A
	Time	Hour, minute, second	X	X	X	X	X	X	X	X	X	X	X	N/A
	Time	Subseconds	X	N/A	X	X	X	X	X	N/A	X	X	X	N/A
	Date (day, month)		X	X	X	X	X	X	X	X	X	X	X	N/A
	Timestamp on tamper detection event		X	X	X	X	X	X	X	X	X	X	X	N/A
	Timestamp on switch to V_BAT mode		N/A	N/A	N/A	N/A	X	N/A	N/A	N/A	X	X	X	N/A
RTC outputs	RTC_ ALARM	Alarm event	X	X	X	X	X	X	X	X	X	X	X	X
	RTC_ ALARM	Wakeup event	X	X	X	X	X	X	X	X	X	X	X	X
	RTC_ CALIB	512 Hz	X	X	X	X	X	X	X	X	X	X	X	X
	RTC_ CALIB	1 Hz	X	N/A	X	X	X	X	X	N/A	X	X	X	X
RTC calibration	Coarse calibration		N/A^⁵	X	N/A^⁵	X	N/A^⁵	N/A^⁵	X	X	N/A^⁵	N/A^⁵	N/A^⁵	N/A^⁵
RTC calibration	Smooth calibration		X	N/A	X	X	X	X	X	N/A	X	X	X	X
Synchronizing the RTC			X	N/A	X	X	X	X	X	N/A	X	X	X	X
Reference clock detection			X	X	X	X	X	X	X	X	X	X	X	X
Backup registers	Powered-on V_BAT		X	X	X	X	X	N/A	N/A	N/A	X	X	X	VDD12
	Reset on a tamper detection		X	X	X	X	X	X	X	X	X	X	X	N/A
	Reset when flash memory readout protection is disabled		X	N/A	X	N/A	X	X	X	X	X	X	X	N/A
	Number of backup registers		5	20	16	20	32	5	32^⁶	20	20^⁷	32	20	5

¹ Except STM32L41/42xxx.

² Except STM32L4P5/Q5 line.

³ 3 inputs for STM32F07/F09x.

⁴ Thanks to timestamp on tamper event.

⁵ Obsolete, replaced by smooth calibration.

⁶ Only 20 for Cat 2.

⁷ 32 for STM32L4R/4S line.

Table 5. Advanced features of RTC3 type
Features			STM32C0	STM32C5	STM32G0	STM32G4	STM32H5	STM32H7A3/7B3	STM32L41/42/4P5/4Q5	STM32L5	STM32N6	STM32H7Rx/7Sx	STM32U0	STM32U3	STM32U5	STM32WBA	STM32WL
RTC clock source (LSE, LSI, HSE with prescaler)			X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
Binary mode			N/A	X	N/A	N/A	X	N/A	N/A	N/A	X	N/A	X	X	X	X	X
Mixed mode (BCD and binary)			N/A	X	N/A	N/A	X	N/A	N/A	N/A	X	N/A	X	X	X	X	X
Prescalers	Asynchronous (number of bits)		X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)	X (7)
Prescalers	Synchronous (number of bits)		X (15)	X (15)	X (15)	X (15)	X (15)	X (15)	X (15)	X (15)	X (15)	X (15)	X (15)	X (15)	X (15)	X (15)	X (15)
Calendar	Time	12 h/24 h format	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
		Hour, minute, second	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
		Subsecond	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Date		X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Daylight operation		X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Bypass the shadow registers		X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Power optimization mode		N/A	X	N/A	N/A	X	N/A	X	X	X	X	X	X	X	X	X
Alarm	Alarms available	Alarm A	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Alarms available	Alarm B	N/A	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Time	12 h/24 h format	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
		Hour, minute, second	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
		Subsecond	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Date or week day		X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Binary mode alarm		N/A	X	N/A	N/A	X	N/A	N/A	N/A	X	X	X	X	X	X	X
Tamper detection	Tamper reactions	Backup registers erasing	N/A	X^²	X	X	X^²	X^¹	X	X^¹	X^²	X^¹	X^¹	X^²	X^²	X^²	X^¹
		Interruption	N/A	X	X	X	X	X	X	X	X	X	X	X	X	X	X
		Trigger for low-power timer	N/A	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Configurable edge detection		N/A	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Configurable level detection^³		N/A	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Number of internal tamper events		N/A	6	4	4	13	7	N/A	5	10	11	4	9	11	9	4
	Number of external tamper inputs		N/A	3	2	3	8 (11 pins)	3	3 ^⁴	8	7	8	5	5	8	6 (6 pins)	3
	V_BAT mode pins		N/A	N/A	N/A	N/A	TAMP_IN[8:1], TAMP_OUT[8:1], RTC_TS, RTC_OUT1/2	RTC_TS, RTC_OUT1/2	RTC_TAMP1/2/3, RTC_TS, RTC_OUT for STM32L441/42. RTC_TS, RTC_OUT1 for STM32L4P5/Q5	TAMP_IN1/2/3, TAMP_OUT2	TAMP_IN[4:1], TAMP_OUT[2:1], RTC_OUT1, RTC_TS	TAMP_IN[3:1], TAMP_OUT2, RTC_TS, RTC_OUT1/2	TAMP_IN[5:0], RTC_TS, RTC_OUT1	RTC_OUT1, RTC_TS, TAMP_IN[5:1]	TAMP_IN[8:1], TAMP_OUT[8:1], RTC_TS, RTC_OUT1/2	N/A	RTC_TS, RTC_OUT1
	NOERASE mode		N/A	N/A	N/A	N/A	X	N/A	X	N/A	X	N/A	N/A	X	X	X	N/A
	Independent watchdog linked to an internal tamper for false detection timeout		N/A	N/A	N/A	N/A	X	N/A	N/A	N/A	X	N/A	N/A	X	X	X	N/A
	Active tamper		N/A	N/A	N/A	N/A	X	X	N/A	X	X	X	N/A	X	X	X	N/A
	Monotonic counter		N/A	N/A	N/A	N/A	X	X	N/A	X	X	X	N/A	X	X	X	X
	LP mode effect on TAMP	Sleep	N/A	No effect
		Stop	N/A	No effect except for filtered level detection and active tamper if clock source is not LSE or LSI
		Standby	N/A
		Shutdown	N/A	X	No effect except for filtered level detection and active tamper if clock source is not LSE		N/A	No effect except for filtered level detection and active tamper if clock source is not LSE			N/A				No effect except for filtered level detection and active tamper if clock source is not LSE	No effect except for filtered level detection and active tamper if clock source is not LSE or LSI
	SAES key storage protection		N/A	N/A	N/A	N/A	X	N/A	N/A	N/A	X	N/A	N/A	X	X	X	N/A
	Secure protection modes		N/A	N/A	N/A	N/A	X^⁶	N/A	N/A	X	X	N/A	N/A	X	X	X	N/A
	Privileged protection mode		N/A	N/A	N/A	N/A	X^⁶	N/A	N/A	X	X	N/A	N/A	X	X	X	N/A
Timestamp	Configurable input mapping		X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Time	Hour, minute, second	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Time	Subsecond	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Date (day, month)		X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Timestamp on tamper detection event		N/A	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Timestamp on switch to VBAT mode		N/A	N/A	X	X	X	X	X	X	X	X	X	X	X	N/A	X
Wakeup unit	Clock source available		N/A	RTC clock divided by 2, 4, 8, 16 or RTC synchronous prescaler output
Wakeup unit	Hardware automatic flag clearing		N/A	X	N/A	N/A	X	N/A	X	X	X	X	X	X	X	X	X
RTC outputs	Number of outputs		2	2	2	2	2	2	2	2	2	2	2	X	2	2	2
	TAMP ALRM	Alarm event	X	2	X	X	X	X	X	X	X	X	X	X	X	X	X
		Wakeup event	N/A	X	X	X	X	X	X	X	X	X	X	X	X	X	X
		Tamper event	N/A	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	CALIB	512 Hz	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	CALIB	1 Hz	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
Digital calibration	Smooth calibration		X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
Digital calibration	Ultra-low-power mode		N/A	X	N/A	N/A	X	N/A	X	X	X	N/A	X	X	X	X	X
RTC synchronization			X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
Reference clock detection			X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
Backup registers	Powered on V_BAT		N/A	X	X	X	X	X	X	X	X	X	X	X	X	N/A	X
	Reset on a tamper detection		N/A	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Reset when flash memory readout protection is disabled		N/A	X	X	X	X	X	X	X	X	X	X	X	X	X	X
	Number of backup registers (size in bits)		4 (32) (within PWR)	32 (32)	5 (32)	32 or 16 (32)^⁵	32 (32)	32 (32)	32 (32)	32 (32)	32 (32)	32 (32)	9 (32)	32 (32)	32 (32)	32 (32)	20 (32)
LP mode effect on RTC	Sleep		RTC interrupts may exit sleep mode	No effect; RTC interrupts may exit Sleep mode	No effect							No effect; RTC interrupts may exit Sleep mode		No effect		No effect; RTC interrupts may exit Sleep mode	No effect
	Stop		Active if RTC is clocked by LSE or LSI	Active if RTC is clocked by LSE or LSI
	Standby		RTC powered down and must be reinitializ ed	Active if RTC is clocked by LSE or LSI
	Shutdown		N/A	N/A	Active if RTC is clocked by LSE		N/A	Active if RTC is clocked by LSE			N/A	N/A	N/A	Active if RTC is clocked by LSE		N/A	Active if RTC is clocked by LSE
RTC secure protection mode			N/A	N/A	N/A	N/A	X^⁶	N/A	N/A	X	X	N/A	N/A	X	X	X	N/A
RTC privilege protection mode			N/A	N/A	N/A	N/A	X^⁶	N/A	N/A	X	X	N/A		X	X	X	N/A

¹ Erasing part of SRAM is also possible.

² Erasing of part of SRAM, caches and cryptographic registers is also possible.

³ Filtering, sampling and precharge configuration, internal pull-up.

⁴ Only two for STM32L4 devices.

⁵ Depends on device category.

⁶ This feature is not available for STM32H503.