| 1 | Disable the RTC registers write protection. | Write 0xCA and then 0x53 into RTC_WPR. | RTC registers can be modified. |
| 2 | Enter initialization mode. | Set INIT = 1 in RTC_ISR (RTC2)/RTC_ICSR (RTC3) register | The calendar counter is stopped to allow its update. |
| 3 | Wait for the confirmation of initialization mode (clock synchronization). | Poll INITF bit of in RTC_ISR (RTC2)/RTC_ICSR (RTC3) until it is set. |
- For RTC2: It takes around two RTCCLK clock cycles due to clock synchronization.
- For RTC3: If LPCAL = 0, INITF is set around two RTCLK cycles after INIT is set. If LPCAL = 1, INITF is set up to two ck_apre cycles after INIT is set.
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| 4 | Program the prescaler values (if needed). | In RTC_PRER, write first the synchronous value, and then write the asynchronous value. For RTC3, program also BIN and BCDU in RTC_ICSR, if in binary or mixed mode. | By default (in BCD mode for RTC3), RTC_PRER is initialized to provide 1 Hz to the calendar unit (when RTCCLK = 32768 Hz). |
| 5 | Load time and date values in the shadow registers. | Set RTC_TR and RTC_DR. | - |
| 6 | Configure the time format (12 h or 24 h) | Set FMT bit in RTC_CR. | If FMT = 0, the format is 24 hour/day. If FMT = 1, the format is 12 h am/pm. |
| 7 | Exit initialization mode. | Clear INIT in RTC_ISR (RTC2)/RTC_ICSR (RTC3). | For RTC2: The current calendar counter is automatically loaded and the counting restarts after four RTCCLK clock cycles. For RTC3: If LPCAL = 0, the counting restarts after four RTCCLK clock cycles. If LPCAL = 1, the counting restarts after up to two RTCCLK + 1 ck_apre cycles. |
| 8 | Enable write protection of the RTC registers. | Write 0xFF into RTC_WPR. | The RTC registers can no longer be modified. |