Overview of LTDC controller and STM32 MCUs…

LTDC and graphic portfolio across STM32 MCUs

Table 3 STM32 MCUs embedding an LTDC and their available graphic portfolio summarizes the STM32 MCUs embedding an LTDC and details the corresponding available graphic portfolio.

Table 3. STM32 MCUs embedding an LTDC and their available graphic portfolio
Device	FLASH (bytes)	On ship SRAM (bytes)	Quad-SPI¹	Octo-SPI	Hexa-SPI	Max AHB/AXI frequency (MHz)²	Max FMC SDRAM frequency (MHz)	Max Octo‑SPI frequency (MHz)	Max Hex‑SPI frequency (MHz)	Max pixel clock (MHz)³	JPEG codec	DMA2D⁴	MIPI-DSI host⁵	Neo-Chrom (GPU2D)	Graphic libraries
STM32F429/439	Up to 2 M	256 K	No	No	No	180	90	-	-	83	No	Yes	No	No	TouchGFX embedded wizard SEGGER STemWin
STM32F469/479	Up to 2 M	384 K	Yes	No	No	180	90	-	-	83	No	Yes	Yes	No
STM32F7x6	Up to 1 M	320 K	Yes	No	No	216	100	-	-	83	No	Yes	No	No
STM32F7x7	Up to 2 M	512 K	Yes	No	No	216	100	-	-	83	Yes	Yes	No	No
STM32F7x8/9	Up to 2 M	512 K	Yes	No	No	216	100	-	-	83	Yes	Yes	Yes	No
STM32H5Ex/Fx	Up to 4 M	1.504 M	Yes	Yes	No	250	100	125	-	90	Yes	Yes	No	No
STM32H7A3/B3	Up to 2 M	1.4 M	No	Yes	No	280	110	140	-	140	Yes	Yes	No	No
STM32H7B0	128 K	1.4 M	No	Yes	No	280	110	140	-	140	Yes	Yes	No	No
STM32H742/43/45/53/55	Up to 2 M	1 M	Yes	No	No	240	110	-	-	150	Yes	Yes	No	No
STM32H747/57	Up to 2 M	1 M	Yes	No	No	240	110	-	-	150	Yes	Yes	Yes	No
STM32H750	128 K	1 M	Yes	No	No	240	110	-	-	150	Yes	Yes	No	No
STM32L4P/Q	Up to 1 M	320 K	No	Yes	No	120	60^⁶	92	-	83	No	Yes	No	No
STM32L4R/S	Up to 2 M	640 K	No	Yes	No	120	60^⁶	86	-	83	No	Yes	Yes	No
STM32H723/33/25/35	Up to 1 M	564 K	No	Yes	275	-	95	150	-	No	Yes	No	No	No
STM32H730	128 K	564 K	No	Yes	275	-	95	150	-	No	Yes	No	No	No
STM32U5Fx/5Gx	Up to 4 M	Up to 3 M	No	Yes	Yes	160	80^⁶	100	160	116	Yes	Yes	No	Yes
STM32U59x/5Ax	Up to 4 M	Up to 2.5 M	No	Yes	Yes	160	80^⁶	100	160	116	No	Yes	Yes	Yes
STM32H7R7/S7	64 K	640 K	Yes	Yes	Yes	300	100	200	200	90	Yes	Yes	No	Yes
STM32N6xx	-	Up to 4.5 M	Yes	Yes	Yes	400	166	200	200	86	Yes	Yes	No	Yes

¹ The Quad-SPI and Octo-SPI interfaces allow interfacing with external memories in order to extend the size of the application. Refer to the document AN4861_General-information.html#id_62127__entry_wzv_bky_31c and AN4861_General-information.html#id_62127__entry_psc_cky_31c for more details.

² LTDC fetches graphical data at AHB/AXI speed.

³ Maximum pixel clock value at I/O level, refer to Table 10 STM32F4x9 maximal supported pixel clock to Table 20 Example of supported display resolutions in specific STM32 hardware configurations for maximum pixel clock at system level. Pixel clock (LCD_CLK) form relevant STM32 datasheet.

⁴ Chrom-Art Accelerator

⁵ The integrated MIPI-DSI controller allows easier PCB design with fewer pins, lower EMI (electromagnetic interference) and lower power consumption. For more details on STM32 MIPI-DSI host, refer to the document AN4861_General-information.html#id_62127__entry_w1b_gjy_31c.

⁶ Max FMC PSRAM frequency (Mhz)

Overview of LTDC controller and STM32 MCUs graphical portfolio

Overview of LTDC controller and STM32 MCUs graphical portfolio

LCD-TFT display controller on STM32 MCUs

LTDC and graphic portfolio across STM32 MCUs