Creating a graphical application with LTDC

This section illustrates the different steps required before and during a graphical application development using LTDC. The user must at first determine the graphical application requirements, then check if the desired display size fits the hardware configuration. During the graphical application compatibility check phase, the existing STM32 reference boards described in AN4861_Reference-boards-with-LCD-TFT-panel.html#id_61973__table_wcq_hcr_31c can be used to evaluate his hardware and software configuration.

Determining graphical application requirements

Determining the graphical application needs is a crucial step to start from. Some of the most important parameters to be defined before starting the creation of the graphical application are display resolution, color depth, as well as the nature of the data to display (static images, text, or animation).

Once the basic parameters mentioned above are defined, the user must determine the graphical hardware architecture of the application, as well as the required hardware resources. The best-fitting STM32 package (see Table 21 STM32 packages with LTDC peripheral versus RGB interface availability) must be selected, according to the following parameters:

If an external memory is needed for the framebuffer.
The external framebuffer memory bus width
The LTDC interface: RGB565, RGB666, or RGB888 depending on the display module
If an external memory is needed to store graphic primitives (serial NOR flash, parallel NOR flash).

Checking the display size and color depth compatibility with the hardware configuration

When starting a graphic application development using an STM32 microcontroller, the user has often a defined desired display size and color depth. A key question that the user must answer before continuing the development is if such display size and color depth match a specific hardware configuration.

The following steps are needed in order to answer this question:

Determine the required framebuffer size and its location.
Check the compatibility of the display versus the framebuffer memory bandwidth requirements.
Check the compatibility of the display panel interface with the LTDC.

Framebuffer memory size requirements and location

Determining the framebuffer memory size and its location is a key parameter for the display compatibility check.

The memory space required in the RAM to support the framebuffer must be contiguous and with a minimum size equal to:

Framebuffer size = number of pixels x bits per pixel

As shown in the formula above, the required framebuffer size depends on the display resolution and on its color depth.

It is not necessary that the framebuffer color depth (bpp) is the same than the display color depth. For instance, an RGB888 display can be driven using an RGB565 framebuffer.

Note:

The required framebuffer size is doubled for double-framebuffer configuration. It is common to use a double-buffer configuration where one graphic buffer is used to store the current image, while the second buffer is used to prepare the next image.

Table 9 Framebuffer size for different screen resolutions shows the framebuffer size needed for standard screen resolutions with different pixel formats.

Table 9. Framebuffer size for different screen resolutions
Screen resolution	Number of pixels	Framebuffer size (Kbyte)¹
Screen resolution	Number of pixels	8 bpp	16 bpp	24 bpp	32 bpp
QVGA (320 x 240)	76800	75	150	225	300
Custom (480 x 272)²	130560	128	255	383	510
HVGA(480 x 320)	153600	150	300	450	600
VGA (640 x 480)	307200	300	600	900	1200
WVGA(800 x 480)	384000	375	750	1125	1500
SVGA (800 x 600)	480000	469	938	1407	1875
XGA (1024 x 768)	786432	768	1536	2304	3072
HD (1280 x 720)	921600	900	1800	2700	3600

Framebuffer location

Depending on the required framebuffer size, the framebuffer can be located either in an internal SRAM or in an external SRAM/SDRAM.

If the internal RAM is not enough for the framebuffer, the user must use either an external parallel SDRAM/SRAM/PSRAM connected to FMC or external serial SRAM/PSRAM connected to XSPI.

Consequently, the required framebuffer size determines if the use of an external memory is needed or not. The required framebuffer size depends on the display size and color depth.

Locating the framebuffer in the Internal SRAM

Depending on the framebuffer size, the framebuffer can be placed either in the internal SRAM or the external RAM.

Using an internal SRAM as a framebuffer allows the maximum performances and avoids any bandwidth limitation issues for the LTDC.

Using the internal SRAM instead of an external RAM has many advantages:

higher throughput (0 wait state access)
reduced number of required pins and PCB design complexity
reduced BOM, hence cost, since no external memory is needed

The only limitation when using the internal SRAM is its limited size (hundreds of Kbytes). When the framebuffer size exceeds the available memory, an external RAM (driven by the FMC or XSPI interface) must be used. However, when dealing with external memories, the user must be careful to avoid bandwidth limitation. For more detailed information, refer to Graphic performance optimization.

Note:

The color look-up table CLUT can be used to decrease the required framebuffer size. (For more details, refer to the STM32 MCU reference manual).

¹ The required framebuffer size is doubled for double-framebuffer configuration.

² An example of a custom 480 x 272 display is the ROCKTECH embedded on the STM32F746 discovery kit (32F746GDISCOVERY).

Checking display compatibility considering the memory bandwidth requirements

This section explains how to check a display compatibility considering the framebuffer memory bandwidth. Some important bandwidth aspects are described and this section explains how to determine the required bandwidth for the pixel clock and the LTDC. Finally, a simple method to conclude whether a desired display size is compatible with a specific hardware configuration; is detailed.

Framebuffer memory bandwidth aspects

Once the framebuffer location is fixed (either in internal or external memory), the user must check if its bandwidth can sustain the hardware configuration.

To check if the memory bandwidth can sustain the LTDC required bandwidth, the user must consider any other concurrent accesses to the memory.

In general, a small size framebuffer located in the internal RAM does not require a high bandwidth. This is because a small size framebuffer means low pixel clock, hence low LTDC required bandwidth.

A more complex use case to analyze is when the framebuffer is located in an external memory.

Framebuffer memory bus concurrency

LTDC, DMA2D, and CPU masters.
In a typical graphic application where an external RAM is used as framebuffer, two or three main AHB masters concurrently use the same memory.
The DMA2D (or the CPU) updates the next image to be displayed while the LTDC fetches and displays the actual image. The memory bus load depends mainly on the LTDC required bandwidth.
Other AHB/AXI masters.
It is common that an external RAM is shared by other masters and not only by those used for graphics. This concurrency leads to heavy bus load and may impact the graphic performances.

Figure 22 AHB masters concurrent access to SDRAM shows all the AHB masters with concurrent access to the SDRAM.

External SDRAM/SRAM memory bus width

When locating the framebuffer in an external SDRAM/SRAM, the user must consider that the external memory running frequency is around half or third of the system frequency. That is the reason why the memory bandwidth must be considered as the bottleneck of the whole graphic system.

One of the needed parameters for checking the display compatibility is the memory bus width. For SDRAM, an 8-bit, 16-bit, or 32-bit configuration can be used.

As previously stated, the most complex to analyze is the use case when the framebuffer is placed in an external memory:

The masters concurrent access on the same external memory leads to more latency and impacts its throughput.

Determining pixel clock and LTDC required bandwidth

Pixel clock computation

The pixel clock is a key parameter for checking display size compatibility with a specific hardware configuration.

To get the typical pixel clock of the display, refer to the display datasheet. The computed pixel clock need to respect the display specifications.

The pixel clock for a specific refresh rate is calculated with the following formula:
LCD_CLK (MHz) = total screen size x refresh rate
Where total screen size = total width x total height.

LTDC required bandwidth

The LTDC required bandwidth depends mainly on three factors:

Number of used LTDC layers.
LTDC layer color depth.
Pixel clock (depends on the resolution of the display panel and on the refresh rate).

The maximum required bandwidth can be calculated as described below:

If only one LTDC layer is used:
LTDC required bandwidth = LCD_CLK x BppL1
If two LTDC layers are used:
LTDC required bandwidth = LCD_CLK x (BppL1 + BppL2)

Where BppL1 and BppL2 are respectively the color depth for LTDC Layer1 and Layer2. The LTDC required bandwidth must not exceed the memory available bandwidth, otherwise, display problems may occur and the FIFO underrun flag may be set (if the FIFO underrun interrupt was enabled). Note: If the memory used to store the framebuffer is also used for other application purposes, it may impact the graphical performances of the system.

Check if the used display resolution fits the hardware configuration

The general method for checking whether a display size with a particular color depth is compatible with memory bandwidth includes the following steps:

Compute the pixel clock according to the display size or extract it from the display datasheet.
Check if the display pixel clock does not exceed the maximum system-supported pixel clock described in Table 10 STM32F4x9 maximal supported pixel clock to Table 17 STM32L4P/Q maximal supported pixel clock. The following parameters must be used to extract from Table 10 STM32F4x9 maximal supported pixel clock or Table 17 STM32L4P/Q maximal supported pixel clock the maximum-supported pixel clock corresponding to the used hardware configuration:
- Number of used LTDC layers.
- Used system clock speed HCLK/ACLK and framebuffer memory speed.
- External framebuffer memory bus width.
- Number of AHB/AXI masters accessing concurrently to external framebuffer memory.
The user must perform some tests to confirm the hardware compatibility with the desired display size and color depth. To do it, the user must monitor the LTDC FIFO underrun interrupt flag in the LTDC_ISR register.
If the FIFO underrun interrupt flag is always reset, then the user confirms that the desired display size is compatible with the hardware configuration.
If the FIFO underrun flag is set, the user must check the following points:
1. Verify if the correct maximum pixel clock is extracted, from Table 10 STM32F4x9 maximal supported pixel clock or Table 17 STM32L4P/Q maximal supported pixel clock, corresponding to the right hardware (mistake example: 16-bit SDRAM but extracted pixel clock corresponding to a 32-bit SDRAM).
2. The color framebuffer line width is not 64/128 bytes (for AHB/AXI) aligned (see Optimizing the LTDC framebuffer fetching from external memories (SDRAM or SRAM)).
3. For the STM32F7 and STM32H7 devices, the MPU is not correctly configured to avoid Cortex®-M7 speculative read accesses to the external memory (see Special recommendations for Cortex M7 (STM32F7/H7) and Cortex M55 (STM32N6)).
4. If the FIFO underrun is still set because there are more than two master concurrent accesses to the external memory, the user must relax the memory bandwidth using the below recommendations:
  - Use only one LTDC layer.
  - Use the largest possible memory bus width (32-bit instead of 16- or 8-bit SDRAM/SRAM).
  - Update the framebuffer content during the blanking period when the LTDC is not fetching.
  - Use the highest possible system clock HCLK/ACLK and the highest memory speed.
  - Decrease the images color depth (bpp).
    For more details on memory bandwidth optimization, see Graphic performance optimization.

Note:

To evaluate the STM32 graphical capability in a specific hardware configuration, the user can use the STM32 boards described in AN4861_Reference-boards-with-LCD-TFT-panel.html#id_61973__table_wcq_hcr_31c.

Figure 23 Typical graphic hardware configuration with external SDRAM shows a typical graphic hardware configuration where an external SDRAM is connected to the FMC that is used for framebuffer. The SDRAM memory bandwidth depends on the bus width and in the operating clock.

The SDRAM bus width can be 32-bit, 16-bit, or 8-bit, while the operating clock depends on the system clock HCLK and the configured prescaler (HCLK/2 or HCLK/3).

Table 10 STM32F4x9 maximal supported pixel clock to Table 20 Example of supported display resolutions in specific STM32 hardware configurations list the maximal supported pixel clock at system level for various STM32 MCUs.

Table 10. STM32F4x9 maximal supported pixel clock
Used LTDC layers	Color depth (bpp)	Maximum pixel clock (MHz)¹
		LTDC²		LTDC + DMA2D³
		FMC
		SDRAM 16-bit	SDRAM 32-bit	SDRAM 16-bit	SDRAM 32-bit
1 layer	32	38	67	22	35
	24	51	83	30	47
	16	76	83	45	70
	8	83	83	83	83
2 layers	32/32	19	33	NA	18
	32/24	22	38	13	21
	32/16	25	44	15	25
	32/8	30	53	19	30
	24/24	26	44	15	24
	24/16	31	53	18	30
	24/8	38	67	23	38
	16/16	39	67	22	37
	16/8	51	83	31	50
	8/8	78	83	46	74

Table 11. STM32F7x6/7/8/9 maximal supported pixel clock
Used LTDC layers	Color depth (bpp)	Maximum pixel clock (MHz)⁴
		LTDC⁵		LTDC + DMA2D⁶
		fmc
		SDRAM 16-bit	SDRAM 32-bit	SDRAM 16-bit	SDRAM 32-bit
1 layer	32	42	74	25	39
	24	56	83	34	52
	16	83	83	51	78
	8	83	83	83	83
2 layers	32/32	21	37	12	20
	32/24	24	42	14	23
	32/16	28	49	17	28
	32/8	34	59	21	34
	24/24	29	49	17	27
	24/16	34	59	20	33
	24/8	42	74	26	42
	16/16	43	74	25	41
	16/8	57	83	34	56
	8/8	83	83	51	82

Table 12. STM32H5Ex/H5Fx maximal supported pixel clock
Used LTDC layers	Color depth	Maximum pixel clock^⁷
		Only LTDC^⁸	LTDC + DMA2D^⁹
		OCTOSPI
		8‑bit PSRAM DDR
1 layer	32	58	24
	24	78	32
	16	90	48
	8	90	90

Table 13. STM32H742/43/45/47/53/55/57 and STM32H750 maximal supported pixel clock
Used LTDC layers	Color depth (bpp)	Maximum pixel clock¹⁰
		LTDC¹¹		LTDC + DMA2D¹²
		FMC
		SDRAM 16-bit	SDRAM 32-bit	SDRAM 16-bit	SDRAM 32-bit
1 layer	32	49	93	29	48
	24	66	124	38	64
	16	99	150	58	96
	8	150	150	116	150

Table 14. STM32H7R7/7S7 maximal supported pixel clock
Used LTDC layers	Color depth (bpp)	Maximum pixel clock¹³
		LTDC¹⁴				LTDC + DMA2D¹⁵
		XSPI		FMC		XSPI		FMC
		8‑bit PSRAM DDR	16‑bit PSRAM DDR	SDRAM 16‑bit	SDRAM 32‑bit	8‑bit PSRAM DDR	16‑bit PSRAM DDR	SDRAM 16‑bit	SDRAM 32‑bit
1 layer	32	88	88	46	84	34	38	28	50
	24	90	90	60	90	46	50	36	66
	16	90	90	90	90	68	74	54	90
	8	90	90	90	90	90	90	90	90

Table 15. STM32H7A3/B3 and STM32H7B0 maximal supported pixel clock
Used LTDC layers	Color depth (bpp)	Maximum pixel clock¹⁶
		LTDC¹⁷			LTDC + DMA2D¹⁸
		OCTOSPI	FMC		OCTOSPI	FMC
		HyperRAM™ 8-bit DDR	SDRAM 16‑bit	SDRAM 32‑bit	HyperRAM™ 8-bit DDR	SDRAM 16‑bit	SDRAM 32‑bit
1 layer	32	52	52	97	22	30	50
	24	70	70	130	29	40	66
	16	105	105	140	44	60	100
	8	140	140	140	89	121	140

Table 16. STM32L4+ maximal supported pixel clock
Used LTDC layers	Color depth (bpp)	Maximum pixel clock¹⁹
		LTDCX²⁰	LTDC + DMA2D²¹
		FSMC
		SRAM 16-bit
1 layer	32	11	-
	24	15	10
	16	23	15
	8	47	31

Table 17. STM32L4P/Q maximal supported pixel clock
Used LTDC layers	Color depth (bpp)	Maximum pixel clock²²
		LTDC²³	LTDC + DMA2D²⁴
		OCTOSPI
		8-bit PSRAM DDR
1 layer	32	27	11
	24	37	15
	16	55	23
	8	60	46

Note:

Decreasing the system clock (HCLK then LTDC) leads to a degradation of graphic performances

Table 18. STM32U59/A/F/G maximal supported pixel clock
Used LTDC layers	Color depth (bpp)	Maximum pixel clock²⁵ ²⁶
		LTDC²⁷	LTDC + DMA2D²⁸
		Hexadeca-SPI
		16-bit PSRAM DDR
1 layer	32	116	42
	24	116	48
	16	116	71
	8	116	116

Table 19. STM32N6xx maximal supported pixel clock
Used LTDC layers	Color depth (bpp)	Maximum pixel clock²⁹
		LTDC³⁰
		XSPI
		8‑bit PSRAM DDR	16‑bit PSRAM DDR
1 layer	32	88	88
	24	88	88
	16	88	88
	8	88	88

Note:

For STM32N6xx devices, the AXI QOS is set to maximum for LTDC. As a consequence, the maximal supported pixel clock is the same for both LTDC and LTDC+DMA2D tests. The values are limited by the LTDC Kernel clock at 88 MHz.

Example of supported display resolutions for STM32F4x9 and STM32F7x6/7/8/9

Table 20 Example of supported display resolutions in specific STM32 hardware configurations lists an example of some standard and custom display sizes supported by the STM32F4x9 and STM32F7x6/7/8/9, in the following conditions:

For STM32F4x9, the system clock HCLK runs @ 180 MHz and the SDRAM @ 90 MHz.
For STM32F7x6/7/8/9, the system clock HCLK runs @ 200 MHz and the SDRAM @ 100 MHz.
Only one LTDC layer is used.
Two AHB masters concurrent access to the SDRAM (LTDC + DMA2D).

Table 20. Example of supported display resolutions in specific STM32 hardware configurations
Display characteristics				STM32 LTDC configuration
Resolution	Refresh rate (Hz)	Pixel clock (MHz)	Display standard	Color depth
Resolution	Refresh rate (Hz)	Pixel clock (MHz)	Display standard	SDRAM 16-bit	SDRAM 32-bit
320 x 240 (QVGA)	60	5.6	Custom	Up to 32 bpp
480 x 272		9.5	Custom	Up to 32 bpp
640 x 480 (VGA)		25.175	Industry standard	Up to 24 bpp	Up to 32 bpp
800 x 600 (SVGA)		40.000	VESA guidelines³¹	Up to 16 bpp	Up to 24 bpp
1024 x 768 (XGA)		65	VESA guidelines³¹	8 bpp	Up to 16 bpp
1280 x 768		68.250	CVT R.B³²		Up to 16 bpp
1280 x 720 (HD)		74.25	CEA³³		Up to 16 bpp³⁴
1920 x1080	30	74.25	CEA³³		Up to 16 bpp³⁴

¹ System clock HCLK = 180 MHz, SDRAM runs at 90 MHz.

² LTDC fetches the front buffer from the external memory. Either only one LTDC layer or two layers are used. The LTDC layer color depth is 8, 16, 24, or 32 bpp.

³ LTDC fetches the front buffer from the external memory while the DMA2D transfers data from backbuffer to frontbuffer.

⁴ System clock HCLK = 200 MHz, SDRAM runs at 100 MHz.

⁵ LTDC fetches the front buffer from the external memory. Either only one LTDC layer or two layers are used. The LTDC layer color depth is 8, 16, 24, or 32 bpp.

⁶ LTDC fetches the front buffer from the external memory while the DMA2D transfers data from backbuffer to frontbuffer.

⁷ HCLK = 250 MHz, PSRAM CLK = 125 MHz.

⁸ LTDC fetches the front buffer from the external memory. The LTDC layer color depth is 8, 16, 24, or 32 bpp.

⁹ LTDC fetches the front buffer from the external memory while the DMA2D transfers data from backbuffer to frontbuffer.

¹⁰ ACLK = 240 MHz, SDRAM runs at 110 MHz.

¹¹ LTDC fetches the front buffer from the external memory. The LTDC layer color depth is 8, 16, 24, or 32 bpp.

¹² LTDC fetches the front buffer from the external memory while the DMA2D transfers data from backbuffer to frontbuffer.

¹³ ACLK = 300 MHz, PSRAM runs at 200MHz, SDRAM runs at 100 MHz

¹⁴ LTDC fetches the front buffer from the external memory. The LTDC layer color depth is 8, 16, 24, or 32 bpp.

¹⁵ When the LTDC and DMA2D have the same read QoS priority (default configuration for H7RS), the LTDC fetches the front buffer from the external memory while the DMA2D prepares the back buffer.

¹⁶ ACLK = 280 MHz, SDRAM/HyperRAM run at 110 MHz.

¹⁷ LTDC fetches the front buffer from the external memory. The LTDC layer color depth is 8, 16, 24, or 32 bpp.

¹⁸ LTDC fetches the front buffer from the external memory while the DMA2D transfers data from backbuffer to frontbuffer.

¹⁹ System clock HCLK = 120 MHz, SRAM is asynchronous.

²⁰ LTDC fetches the front buffer from the external memory. The LTDC layer color depth is 8, 16, 24, or 32 bpp.

²¹ LTDC fetches the front buffer from the external memory while the DMA2D transfers data from backbuffer to frontbuffer.

²² System clock HCLK = 120 MHz, PSRAM runs at 60 MHz.

²³ LTDC fetches the front buffer from the external memory. The LTDC layer color depth is 8, 16, 24, or 32 bpp.

²⁴ LTDC fetches the front buffer from the external memory while the DMA2D transfers data from backbuffer to frontbuffer.

²⁵ System clock HCLK = 160 MHz, PSRAM memory runs at 160 MHz.

²⁶ Limited by LTDC maximum output clock frequency, refer to the relevant product datasheet.

²⁷ LTDC fetches the front buffer from the external memory. The LTDC layer color depth is 8, 16, 24, or 32 bpp.

²⁸ LTDC fetches the front buffer from the external memory while the DMA2D transfers data from backbuffer to frontbuffer.

²⁹ ACLK = 400 MHz, PSRAM runs at 200 MHz

³⁰ LTDC fetches the front buffer from the external memory. The LTDC layer color depth is 8, 16, 24, or 32 bpp.

³¹ VESA (video electronics standards association) is a technical standards organization for computer display standards providing display monitor timing (DMT) standards.

³² CVT R.B: coordinated video timings reduced blanking standard by VESA.

³³ CEA = consumer electronics association.

³⁴ Up to 8 bpp for the STM32F4x9 microcontrollers.

Check the compatibility of the display panel interface with the LTDC

The user must choose the LCD panel depending on the application needs. The two main factors to consider when choosing the LCD panel are the resolution and the color depth. These two factors have a direct impact on the following parameters:

required GPIO number
framebuffer size and location
pixel clock of the display

When selecting a display panel, the user must:

Ensure that the display interface is compatible with the LTDC (parallel RGB with control signals).
Check if the control signals can be controlled by the LTDC (additional GPIOs are sometimes needed).
Ensure that the display signal levels are matching the LTDC interface signal levels (VDD from 1.8 V to 3.6 V).
Ensure that the display pixel clock is supported by the LTDC maximum pixel clock defined in the relevant STM32 product datasheet.
Verify that the display timings parameters are supported by the LTDC timings (see Table 6 LTDC timing registers).
Check that the display size and color depth are supported by the LTDC (refer to Checking display compatibility considering the memory bandwidth requirements).