LTDC in a smart architecture

The LTDC is a master on the AHB/AXI architecture that performs read access on internal and external memories. The LTDC has two independent layers, each one with its own FIFO enabling more flexibility of the display.

The LTDC controller autonomously fetches graphical data at the speed of the AHB/AXI bus from the framebuffer. The graphical data is then stored in one of the internal layers FIFO then driven to the display.

The system architecture allows graphics to be built and plotted to the screen without any CPU intervention. The LTDC retrieves the data belonging to an image from the framebuffer, while the DMA2D prepares the next images.

The LTDC interface is integrated in a smart architecture allowing:

LTDC autonomously fetches the graphical data from the framebuffer (can be internal memories such as internal flash, internal SRAM or external memories, such as FMC_SDRAM or Quad-SPI) and drives it to the display.
DMA2D, as an AHB/AXI master, can be used to offload the CPU from graphics intensive tasks.
LTDC is able to continue displaying graphics even in Sleep mode when the CPU does not run.
The multilayer AHB/AXI bus architecture improves memories throughput and leads to higher performance.

System architecture on STM32F429/439 and STM32F469/479 microcontrollers

The system architecture of the STM32F429/439 line and the STM32F469/479 line consists mainly of 32-bit multilayer AHB bus matrix that interconnects ten masters and nine slaves (eight slaves for the STM32F429/F439). The LTDC is one of the ten AHB masters on the AHB bus matrix.

The LTDC can autonomously access all the memory slaves on the AHB bus matrix, such as FLASH, SRAM1, SRAM2, SRAM3 FMC or Quad-SPI enabling an efficient data transfer that is ideal for graphical applications.

Figure 9 LTDC AHB master in STM32F429/439 and STM32F469/479 smart architecture. (1) SRAM1 size = 112 Kbytes for STM32F429/439 and 160 Kbytes for STM32F469/479. (2) SRAM2 size = 16 Kbytes for STM32F429/439 and 32 Kbytes for STM32F469/479. (3) SRAM3 size = 64 Kbytes for STM32F429/439 and 128 Kbytes for STM32F469/479. (4) Dual Quad-SPI interface is only available for STM32F469/479. shows the LTDC interconnection in the STM32F429/439 and STM32F469/479 lines systems.

System architecture on STM32F7x6, STM32F7x7, STM32F7x8, and STM32F7x9

The system architecture of the STM32F7x6, STM32F7x7, STM32F7x8, and STM32F7x9 consists mainly of 32-bit multilayer AHB bus matrix that interconnects twelve masters and eight slaves. The LTDC is one of the twelve AHB masters on the AHB bus matrix.

The LTDC can autonomously access all the memory slaves on the AHB bus matrix, such as FLASH, SRAM1, SRAM2, FMC, or Quad-SPI enabling an efficient data transfer that is ideal for graphical applications. Figure 10 LTDC AHB master in STM32F7x6, STM32F7x7, STM32F7x8, and STM32F7x9 smart architecture. (1) I/D Cache size = 4 Kbytes for STM32F7x6. I/D Cache size = 16 Kbytes for STM32F7x7, STM32F7x8, and STM32F7x9. (2) DTCM RAM size = 64 Kbytes for STM32F7x6. DTCM RAM size = 128 Kbytes for STM32F7x7, STM32F7x8, and STM32F7x9. (3) ITCM RAM size = 16 Kbytes for STM32F7x6, STM32F7x7, STM32F7x8, and STM32F7x9. (4) SRAM1 size = 240 Kbytes for STM32F7x6. SRAM1 size = 368 Kbytes for STM32F7x7, STM32F7x8, and STM32F7x9. (5) SRAM2 size = 16 Kbytes for STM32F7x6, STM32F7x7, STM32F7x8, and STM32F7x9. shows the LTDC interconnection in the STM32F7x6, STM32F7x7, STM32F7x8, and STM32F7x9 systems.

Figure 10. LTDC AHB master in STM32F7x6, STM32F7x7, STM32F7x8, and STM32F7x9 smart architecture.
(1) I/D Cache size = 4 Kbytes for STM32F7x6.
I/D Cache size = 16 Kbytes for STM32F7x7, STM32F7x8, and STM32F7x9.
(2) DTCM RAM size = 64 Kbytes for STM32F7x6.
DTCM RAM size = 128 Kbytes for STM32F7x7, STM32F7x8, and STM32F7x9.
(3) ITCM RAM size = 16 Kbytes for STM32F7x6, STM32F7x7, STM32F7x8, and STM32F7x9.
(4) SRAM1 size = 240 Kbytes for STM32F7x6.
SRAM1 size = 368 Kbytes for STM32F7x7, STM32F7x8, and STM32F7x9.
(5) SRAM2 size = 16 Kbytes for STM32F7x6, STM32F7x7, STM32F7x8, and STM32F7x9.

System architecture on STM32H7Rx/7Sx

The system architecture of the STM32H7Rx/7Sx primarily consists of a 64-bit AXI, a 32-bit multilayer AHB bus matrix, and bus bridges that allow interconnection of bus masters with bus slaves. The AXI bus matrix connects 11 masters and 10 slaves. The LTDC is one of the 11 AXI masters on the AXI bus matrix. The LTDC can autonomously access all the memory slaves on the AXI bus matrix, such as FLASH, AXI SRAM1, AXI SRAM2, AXI SRAM3, AXI SRAM4, FMC, or XSPI, enabling efficient data transfer ideal for graphical applications.

Figure 11. LTDC AXI master in STM32H7Rx/7Sx

Advantages of using an STM32 LTDC controller

Table 4 Advantages of using STM32 MCUs LTDC controller summarizes the major advantages of using the STM32 embedded LTDC interface.

Table 4. Advantages of using STM32 MCUs LTDC controller
Advantage	Comments
Cost savings	Compared to other DBI interfaces (SPI, Motorola 6800 or Intel 8080), the LTDC allows a connection to any low-cost display module with no display controller nor GRAM.
CPU offloaded	The LTDC is an AHB/AXI master with its own DMA, that fetches data autonomously from any AHB/AXI memory without any CPU intervention.
No need for extra applicative layer	The LTDC hardware fully manages the data fetching, the RGB outputting and the signals control, so no need for extra applicative layer.
Fully programmable resolution supporting custom and standard displays	Fully programmable resolution with: Total width of up to 4096 pixels. Total height of up to 2048 lines. Device specific maximum pixel clock specified in Table 3 STM32 MCUs embedding an LTDC and their available graphic portfolio. Support of custom and standard resolutions (QVGA, VGA, SVGA, WVGA, XGA, HD, and others).
Flexible color format	Each LTDC layer can be configured to fetch the framebuffer in the desired pixel format (see Programmable layer: color framebuffer).
Flexible parallel RGB interface	The flexible parallel RGB interface allows to drive 16-bit, 18-bit and 24-bit displays.
Ideal for low-power and mobile applications such as smart watches.	The LTDC is able to continue graphic data fetching and display driving while the CPU is in Sleep mode.

LCD-TFT (LTDC) display controller description

The LTDC is a controller that reads the data of images in a line per line fashion. Its memory access mode is 64/128-byte (for AHB/AXI) length, but when the end of a line is reached and less than 64/128 bytes (for AHB/AXI) are left, the LTDC fetches the remaining data.

Functional description

On every pixel clock-raising edge or clock-falling edge and within the screen active area, the LTDC layer retrieves one pixel data from its FIFO, converts it to the internal ARGB8888 pixel format and blends it with the background and/or with the other layer pixel color. The resulting pixel, coded in the RGB888 format, goes through the dithering unit and is driven into the RGB interface. The pixel is then displayed on the screen.

LTDC clock domains

The LCD-TFT controller peripheral uses three clock domains:

AHB/AXI clock domain (HCLK/ACLK): used to transfer data from the memories to the FIFO layer and the frame-buffer configuration registers.
APB clock domain (PCLK): this domain contains the global configuration registers and the interrupt register.
Pixel clock domain (LCD_CLK): used to generate the LCD-TFT interface signals and contains the layer configuration registers.
The LCD_CLK output need to be configured following the panel requirements through the PLL.

LTDC reset

The LTDC is reset by setting the LTDCRST bit in the RCC_APBxRSTR register.

Flexible timings and hardware interface

Thanks to its timings and hardware interface flexibility, the LCD-TFT controller is able to drive several monitors with different resolutions and signal polarities.

LCD-TFT pins and signal interface

To drive LCD-TFT displays, the LTDC provides up to 28 signals using simple 3.3 V signaling including:

Pixel clock LCD_CLK
Data enable LCD_DE
Synchronization signals (LCD_HSYNC and LCD_VSYNC)
Pixel data RGB888

Note:

The LTDC controller may support other display technologies if their interface is compatible.

The LTDC interface output signals are illustrated in Table 5 LTDC interface output signals

Table 5. LTDC interface output signals
LCD-TFT signal	Description
LCD_CLK	The LCD_CLK acts as the data valid signal for the LCD-TFT. The data is considered by the display only on the LCD_CLK rising or falling edge.
LCD_HSYNC	The line synchronization signal (LCD_HSYNC) manages horizontal line scanning and acts as line display strobe.
LCD_VSYNC	The frame synchronization signal (LCD_VSYNC) manages vertical scanning and acts as a frame update strobe.
LCD_DE	The DE signal, indicates to the LCD-TFT that the data in the RGB bus is valid and must be latched to be drawn.
Pixel RGB data	The LTDC interface can be configured to output more than one color depth. It can use up to 24 data lines (RGB888) as display interface bus.

Other signals

It is usual that display panel interfaces include other signals that are not part of the LTDC signals described in Table 5 LTDC interface output signals. These additional signals are required for a display module to be fully functional. The LTDC controller is able to drive only signals described in Table 5 LTDC interface output signals.

The signals that are not part of the LTDC, may be managed using GPIOs and other peripherals and may need specific circuits.

The display panels usually embed a backlight unit that requires an additional backlight control circuit and a GPIO.

Some display panels need a reset signal and also a serial interface such as I²C or SPI. These interfaces are used in general for the display initialization commands or for the touch panel control.

Figure 13 LTDC signal interface shows a display panel connected to an STM32 MCU, using the LTDC interface signals illustrated in Table 5 LTDC interface output signals.

The LTDC can output data according to the following parallel formats: RGB565, RGB666, and RGB888. So, 16‑bit RGB565, 18-bit RGB666 or 24-bit RGB888 display can be connected.

LTDC signals programmable polarity

The LTDC control signals polarity is programmable allowing the STM32 microcontroller to drive any RGB parallel display. The control signals (HSYNC, VSYNC, and data enable DE) as well as the pixel clock (LCD_CLK) can be defined to be active high or active low through the LTDC_GCR register.

Fully programmable timings for different display sizes

Thanks to its “timings flexibility”, the LTDC peripheral can support any display size that respects the maximal programmable timing parameters in the registers and the maximal supported pixel clock described in Table 3 STM32 MCUs embedding an LTDC and their available graphic portfolio and Table 10 STM32F4x9 maximal supported pixel clock to Table 19 STM32N6xx maximal supported pixel clock.

The user must consider the timings registers described in Table 6 LTDC timing registers when programming as the LTDC timings and synchronization signals must be programmed to match the display specification.

Table 6 LTDC timing registers summarizes the timings registers supported by the LTDC.

Table 6. LTDC timing registers
Register		Timing parameter	Value to be programmed
LTDC_SSCR¹	HSW[11:0]	HSYNC width - 1	From 1 to 4096 pixels
LTDC_SSCR¹	VSH[11:0]	VSYNC height - 1	From 1 to 2048 lines
LTDC_BPCR	AHBP[11:0]	HSYNC width + HBP - 1	From 1 to 4096 pixels
LTDC_BPCR	AVBP[10:0]	VSYNC height + VBP - 1	From 1 to 2048 lines
LTDC_AWCR	AAW[11:0]	HSYNC width + HBP + active width - 1	From 1 to 4096 pixels
LTDC_AWCR	AAH[10:0]	VSYNC height + BVBP + active height - 1	From 1 to 2048 lines
LTDC_TWCR	TOTALW[11:0]	HSYNC width + HBP + active width + HFP - 1	From 1 to 4096 pixels
LTDC_TWCR	TOTALH[10:0]	VSYNC height + BVBP + active height + VFP - 1	From 1 to 2048 lines

Example of a typical LTDC display frame

Figure 14 Typical LTDC display frame (active width = 480 pixels) shows an example of a typical LTDC display frame showing the timing parameters described in Table 6 LTDC timing registers.

LTDC flexible timings

The LTDC peripheral allows the user to interface with any display size with total width of up to 4096 pixels and total height of up to 2048 lines (refer to Table 6 LTDC timing registers).

Figure 15 Fully programmable timings and resolutions illustrates fully programmable timings and resolutions.

CAUTION: Any display resolution belonging to the maximal total area in 4096 x 2048 as described in Figure 15 Fully programmable timings and resolutions is supported by the LTDC only if the following conditions are met:

The display panel pixel clock must not exceed the maximal LTDC pixel clock in Table 3 STM32 MCUs embedding an LTDC and their available graphic portfolio.
The display panel pixel clock must not exceed the maximal STM32 pixel clock respecting the framebuffer bandwidth (see Checking the display size and color depth compatibility with the hardware configuration).

Figure 16 LTDC fully programmable display resolution with total width up to 4096 pixels and total height up to 2048 lines. Only the active display area is shown in this figure. shows some custom and standard resolutions belonging to the maximal 4096 x 2048 supported by the LTDC.

¹ Setting HSYNC to 0 in HSW[11:0] gives one pulse width of one LCD_CLK. Setting VSYNC to 0 in VSW[11:0] gives one total line period.