Supported display panels

The display controller embeds a very flexible interface that provides the features below that allow the STM32 MCUs to support multiple-parallel display panels (such as LCD-TFT and OLED displays) available in the market:

Different signal polarities
Programmable timings and resolutions

The display panel pixel clock (as indicated in the manufacturer datasheet) must not be higher than the STM32 maximal pixel clock. The user must refer to the display datasheet to ensure that the panel running clock is lower than the maximum pixel clock.

Frequently asked questions

This section summarizes the most frequently asked questions regarding the LTDC usage and configurations.

Table 26. Frequently asked questions
Question	Answer
What is the LTDC maximum supported resolution?	There is no absolute maximum resolution since it depends on several parameters such as: color depth used SDRAM bus width system operating speed (HCLK) number of AHB masters accessing concurrently to memory used for framebuffer See Checking display compatibility considering the memory bandwidth requirements.
Does the STM32F4 or the STM32F7 support a 1280 x 720p 60 Hz resolution?	Yes, see examples in Checking display compatibility considering the memory bandwidth requirements.
Which SDRAM bus width must be used for a specific resolution?	There is not an exact specific bus width, it depends on the resolution, the color depth and whether the SDRAM is shared with other AHB masters or not. The higher the SDRAM bus width, the better. An SDRAM 32-bit provides the best possible performance.
How to get the maximal supported resolution for a specific hardware?	Refer to Checking display compatibility considering the memory bandwidth requirements.
Does LTDC support OLED displays?	Yes, if the OLED display has a parallel RGB interface.
Does LTDC support STN displays?	No, STN displays are not supported by LTDC.
Why the image is displayed with Red and Blue colors swapped?	This is because the image is not stored into memory respecting the configured pixel input format (see Converting images to C files).
Does LTDC support gray scale?	Yes, it is possible by using the L8 mode and using a correct CLUT (R=G=B).
Why is the display bad (displaying bad visual effects)?	Many factors can lead to a bad visual effect. The user can perform the following checks: Check if the used display is correctly initialized / configured (some displays need an initialization / configuration sequence). Check if the LTDC timings and layer parameters are correctly set (see example in LTDC peripheral configuration). Display an image directly from the internal flash (see example in Display an image from the internal flash). Check if there is a nonsynchronization between the LTDC and the framebuffer update (by DMA2D or CPU), see Checking display compatibility considering the memory bandwidth requirements.

Conclusion

The STM32 MCUs provide a very flexible display controller, used to interface with a wide range of displays at a lower cost and offering high performances.

Thanks to its integration in a smart architecture, the LTDC autonomously fetches the graphical data from the framebuffer and drives them to the display without any CPU intervention.

The LTDC can continue fetching the graphical data and driving the display while the CPU is in Sleep mode, which is ideal for low-power and mobile applications such as smart watches.

This application note described the STM32 graphical capabilities and presented some considerations and recommendations to take fully advantage of the smart system architecture.

Revision history

Table 27. Document revision history
Date	Revision	Changes
10-Feb-2017	1	Initial release.
10-Feb-2017	2	Updated code on SDRAM and Quad-SPI MPU configuration example
10-Jul-2020	3	Updated: Introduction Product list extended in Table 1 and in the whole doc Table 3: STM32 MCUs embedding an LTDC and their available graphic portfolio Table 10 and Table 11 New Table 13 to Table 15 Section 6.2.6: FMC SDRAM configuration Figure 52: FMC SDRAM MPU configuration example Code in SDRAM and Quad-SPI MPU configuration example
13-Mar-2023	4	Updated Section: Introduction and Section Table 1.: Applicable products to add STM32U5 information. Updated the information in Section Table 15.: STM32L4P/Q maximal supported pixel clock. Edited the whole document to apply minor changes. Added Section Table 16.: STM32U59/A/F/G maximal supported pixel clock
08-Mar-2024	5	Added STM32H7Rx/7Sx lines Updated document title
07-Feb-2025	6	Updated: Introduction LTDC and graphic portfolio across STM32 MCUs LTDC in a smart architecture Checking display compatibility considering the memory bandwidth requirements STM32 package selection guide
13-Feb-2026	7	Replaced AHB with AHB/AXI and HCLK with HCLK/ACLK wherever applicable throughout the document. Updated: Table 1 Reference documents Table 2 Display interfaces supported by STM32 MCUs Table 3 STM32 MCUs embedding an LTDC and their available graphic portfolio LTDC in a smart architecture Figure 11 LTDC AXI master in STM32H7Rx/7Sx Table 4 Advantages of using STM32 MCUs LTDC controller Figure 12 LTDC block diagram LTDC clock domains LTDC reset Fully programmable timings for different display sizes Programmable layer: color framebuffer Low-power modes Determining graphical application requirements Framebuffer memory size requirements and location Checking display compatibility considering the memory bandwidth requirements Table 12 STM32H5Ex/H5Fx maximal supported pixel clock Table 14 STM32H7R7/7S7 maximal supported pixel clock Table 21 STM32 packages with LTDC peripheral versus RGB interface availability Optimizing the LTDC framebuffer fetching from external memories (SDRAM or SRAM) Special recommendations for Cortex M7 (STM32F7/H7) and Cortex M55 (STM32N6) Storing graphic primitives Hardware considerations Check if a 480 x 272 resolution with 24 bpp fits the SDRAM 16-bit configuration Table 25 STM32 reference boards embedding LTDC and featuring an on-board LCD-TFT panel