ST72681
USB 2.0 high-speed Flash drive controller
Features
USB 2.0 interface compatible with mass storage device class Integrated USB 2.0 PHYSupports USB high speed and full speed Suspend and Resume operations Mass storage controller interface (MSCI) Suppor ts all types of NAND Flash devices including ST, Hynix, Samsung, Toshiba, Micron, Renesas Reed-Solomon encoder/decoder on-the-fly correction (4 bytes of a 512-byte block) Flash identification support Up to 12 MB/s for read and 8 MB/s for write operations in single channel Up to 4 NAND devices supported in a single channel Embedded ST7 8-bit MCU Supply management 3.3 V operation Integrated 3.3-1.8 V voltage regulator USB 2.0 low-power device compliant Less than 100 mA during write operation with two NAND Flash devices Less than 500 A in suspend mode AutoRun CDROM partition support Bootability support (HDD mode) Device summary
TQFP48 7x7
Clock management Integrated PLL for generating core and USB 2.0 clock sources using an external 12 MHz crystal oscillator Data protection Write protect switch control Public/private partitions support Production tool device configurability: USB vendor ID/product ID (VID/PID), serial number and USB strings with foreign language support SCSI strings One or two LED outputs Adjustable NAND Flash bus frequency to reach highest performance Code update in the NAND Flash memory TQFP48 7x7 ECOPACK package Development support Complete reference design including schematics, BOM and gerber files Supports Windows (Vista, XP, 2000, ME), Linux and MacOS. Drivers available for Windows 98 SE
Orderable part numbers
Table 1.
Features ST72681/R20 USB interface Number of NAND devices supported R/W speed Operating voltage Operating temperature Package
1. Number of NAND devices supported in a single channel.
(1)
ST72681/R21 USB 2.0 high speed
up to 1 11MB/s and 7MB/s 3.0 to 3.6 V 0 to +70 C TQFP48 7x7 / Die form
up to 4 12MB/s and 8MB/s
August 2007
Rev 5
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www.st.com 1
Contents
ST72681
Contents
1 2 3 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 NAND interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 4.2 NAND support table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 NAND error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.1 4.2.2 Hardware error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Firmware error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bad block identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bad block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Late fail block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LUT usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3
Management of bad NAND blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3.1 4.3.2 4.3.3
4.4 4.5
Wear levelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4.1
NAND interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Mass storage implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 5.2 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 BOT / SCSI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1 5.2.2 5.2.3 BOT specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SCSI specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bootability specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Public drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Private drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Additional drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CD-ROM considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3
Multi-LUN device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.1 5.3.2 5.3.3 5.3.4
5.4
Mass storage interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
Human interface implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 6.2 LED behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read only switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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ST72681
Contents
7.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 RUN and SUSPEND modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Cr ystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Functional EMS (electro magnetic susceptibility) . . . . . . . . . . . . . . . . . 20 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 21 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MSCI parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Universal serial bus interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2.1 7.2.2 7.2.3
7.3 7.4
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.3.1 7.4.1 7.4.2
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.5
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.5.1 7.5.2
7.6
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.6.1 7.6.2 7.6.3
7.7
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.7.1 7.7.2
7.8 7.9
Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8.1 7.9.1 7.9.2
Other communication interface characteristics . . . . . . . . . . . . . . . . . . . . 26
8 9 10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Introduction
ST72681
1
Introduction
The ST72681 is a USB 2.0 high-speed Flash drive controller. The USB 2.0 high-speed interface including PHY and function supports USB 2.0 mass storage device class. The mass storage controller interface (MSCI) combined with the Reed-Solomon encoder/decoder on-the-fly correction (4-byte on 512-byte data blocks) provides a flexible, high transfer rate solution for interfacing a wide of range NAND Flash memory device types. The internal 60 MHz PLL driven by the 12 MHz oscillator is used to generate the 480 MHz frequency for the USB 2.0 PHY. The ST7 8-bit CPU runs the application program from the internal ROM and RAM. USB data and patch code are stored in internal RAM. I/O ports provide functions for EEPROM connection, LEDs and write protect switch control. The internal 3.3 to 1.8 V voltage regulator provides the 1.8 V supply voltage to the digital part of the circuit. Figure 1. Device block diagram
12 MHz OSC
8-bit C PU
ROM
R AM
USB 2.0 USB 2.0 Function PHY
Mass Storage Controller Interface
ReedSolomon Error Correction
N A ND I/F
3.3 V to 1.8 V voltage regulator
GPIO
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ST72681
Pin description
2
Pin description
Figure 2 shows the TQFP48 package pinout, while Table 2, Table 3, Table 4, and Table 5 give the pin description. The legend and abbreviations used in these tables are the following:
Type I = input O = output S = supply
Input level: A = Dedicated analog input In/Output level CT = CMOS 0.3VDD/0.7VDD with input trigger TT= TTL 0.8V / 2V with Schmitt trigger D8 = 8mA drive D4 = 4mA drive D2 = 2mA drive 48-pin TQFP package pinout
Output level
Figure 2.
VDDA OSCIN OSCOUT VSSA RREF VSSC VDDC VDD3 USBDP USBDM VSSBL VDDBL
48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
VSS_1 VDD33_1 NC(1) NAND D[0] NAND D[1] NAND D[2] NAND D[3] NAND D[4] NAND D[5] NAND D[6] NAND D[7] NAND RnB
ST72681
NAND WP READ ONLY EEPROM SCL VSS_2 VDD33_2 NC(1) NC(1) RESET LED2 LED1 NAND ALE/EEPROM SDA VSS_3
1. Must remain NOT connected in the application.
VDDOUSB VSS_4 VDD33_4 NAND CE4 NAND CE3 NAND CE2 NAND CE1 NAND RE NAND WE NAND CLE NC(1) VDD33_3
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Pin description Table 2.
Pin 48 47 33 32 25 24 14 15 13
ST72681 Power supply
Pin name VSS_1 VDD33_1 VSS_2 VDD33_2 VSS_3 VDD33_3 VSS_4 VDD33_4 VDDOUSB Type Description Ground I/Os and regulator supply voltage Ground I/Os and regulator supply voltage Ground I/Os and regulator supply voltage Ground I/Os and regulator supply voltage USB2 PHY, OSC and PLL power supply output (1.8 V)
S S S S S S S S S
Table 3.
Pin 12 11 10 9 8 7 6 5
USB 2.0 interface
Pin name VDDBL VSSBL USBDM USBDP VDD3 VDDC VSSC RREF Type Description Supply voltage for buffers and deserialization flip flops (1.8 V) Ground for buffers and deserialization flip flops (1.8 V)
S S
I/O USB2 DATA I/O USB2 DATA + S S S I/O Supply voltage for the FS compliance (3.3 V) Supply voltage for DLL & XOR tree (1.8 V) Ground for DLL & XOR tree (1.8 V) Ref. resistor for integrated impedance process adaptation (11.3 kOhms 1% pull down)
Table 4.
Pin 4 3 2 1
USB 2.0 and core clock system
Pin name VSSA OSCOUT OSCIN VDDA Type Description Ground for osc & PLL (1.8 V) 12 MHz oscillator output 12 MHz oscillator input Supply voltage for osc & PLL (1.8 V)
S O I S
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ST72681 Table 5. General Purpose I/O Ports / Mass Storage I/Os
Level Type Input Pin name Outputs Main function (after reset) Pin
Pin description
45 44 43 42 41 40 39 38 26 22 21 20 19 18 17 16 37 36 35 34 28 27
NAND D[0] NAND D[1] NAND D[2] NAND D[3] NAND D[4] NAND D[5] NAND D[6] NAND D[7] NAND ALE NAND CLE NAND WE NAND RE NAND CE1 NAND CE2 NAND CE3 NAND CE4 NAND RnB NAND WP READ ONLY EEPROM SCL LED2 LED1
I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O I O I O O O
TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT
D4 NAND Data [0] D4 NAND Data [1] D4 NAND Data [2] D4 NAND Data [3] D4 NAND Data [4] D4 NAND Data [5] D4 NAND Data [6] D4 NAND Data [7] D8 NAND Address Latch Enable D8 NAND Command Latch Enable D8 NAND WRite Enable D8 NAND read enable D4 NAND Chip Enable 1 D4 NAND Chip Enable 2 D4 NAND Chip Enable 3 D4 NAND Chip Enable 4 D2 NAND Ready/Busy D2 NAND Write Protect D2 Read -only switch ("0": Read/Write; "1": Read only) D2 EEPROM serial clock D8 Green LED (USB access) D8 Red LED (NAND memory access)
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Application schematics
ST72681
3
Application schematics
Figure 3.
U SB_V5
U1
Application schematic
V33
On BoardFlash1
Vout 5 4
C3 10nF + C4 4. uF 7
D7 D6 D5 D4
On BoardFlash2
V33
D7 D6 D5 D4 D3 D2 D1 D0
1 2 3
Vi n GND
I H IBIT BYPASS N
LD3985M33R_SOT23-L 5
V33
C5 220nF
D3 D2 D1 D0
UU1
Decouplng capacior t be l cat d cl s t U2,U3, U4 & U5 V33 i put i tso oe oe o ns
Vout
1
N C / R ES # NC NC NC NC NC NC RB4 IO 7 / RB3 G N D / B2 R IO 6 / IO 5 / #R / B IO 4 / #R E NC #C E #C E 2 NC P NC N C/ RE V CC V CC V SS V SS NC #C E 3 NC #C E 4 C LE NC IO 3 / A LE IO 2 / #W E IO 1 #W P / NC / IO 0 NC NC NC NC NC NC NC NC
Vi n
GND C18 100nF C19 100nF C20 100nF C21 100nF
AM E8800_SO T23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
N A N D _C E 3 N A N D _C E 4 N A N D _C L E N A N D _A L E N A N D _W E N A N D _W P
N A N D _R nB 2 N A N D _R nB N A N D _R E
N A N D _R nB N A N D _R E N A N D _C E 1 N A N D _C E 2
N AN D _W P R_Toshiba_config N AN D _RnB2 R7 0
N AN D _W P
N A N D _C E 4
V33
R_Multi_CE_config R8 0
V33
R_Single_CE_config N AN D _CE2 R9 0
R_Dual_CE_config N AN D _CE3 R10
D [ .0] 7.
0
V33
D ecouplng capacior t be l cat d cl s t U1 V33 i put i tso oe oe o ns
V33
On BoardFlash3
R3 4. K 7
On BoardFlash4
V33
D3 D2 D1 D0
C6 10nF
C7 10nF
C8 10nF
C9 10nF
C10 10nF N AN D _RnB
D7 D6 D5 D4
V33
D3 D2 D1 D0 D7 D6 D5 D4
V33
D0 D1 D2 D3 D4 D5 D6 D7
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
V18_U SB
XT1 C15 18pF
V18_U SB
48 47 46 45 44 43 42 41 40 39 38 37
N A N D _W P
R4 U? ST72681_QF48 P 10K
NC # N C / R ES NC NC NC NC RB4 NC RB3 IO 7 / G N D / B2 IO 6 R / #R / B IO 5 / #R E IO 4 / NC #C E #C E 2 NC NC N C/ RE P V CC V CC V SS V SS #C E 3 NC NC #C E 4 C LE NC A LE IO 3 / #W E IO 2 / #W P IO 1 / NC IO 0 / NC NC NC NC NC NC NC NC
N A N D _FL A SH _T SO P48
N C / R ES # NC NC NC NC NC NC RB4 RB3 IO 7 / G N D / B2 R IO 6 / #R / B IO 5 / #R E IO 4 / #C E NC NC #C E 2 NC N C/ RE P V CC V CC V SS V SS NC #C E 3 #C E 4 NC NC C LE A LE IO 3 / #W E IO 2 / #W P IO 1 / NC IO 0 / NC NC NC NC NC NC NC NC
U4
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
U5
N A N D _FL A SH _T SO P48
4 3
2 1
C16 18pF
NAND NAND NAND NAND NAND NAND NAND NAND NAND
V SS_1 V D D 33_1 NC D[ ] 0 D[ ] 1 D[ ] 2 D[ ] 3 D[ ] 4 D[ ] 5 D[ ] 6 D[ ] 7 R nB
S1 RO Read Onl y
CRYSTAL 12M H _N X4025D A R6 500 R5 11. K 1% 3
U SB_V5
DP DM
V33
1 2 3 4 5 6 7 8 9 10 11 12
V D D O U SB V SS_4 V D D 33_4 N A N D C E4 N A N D C E3 N A N D C E2 N A N D C E1 N A N D RE NAND W E N A N D C LE NC V D D 33_3
VDDA O SCIN OSCOUT VSSA RREF VSSC VDDC VD D 3 U SBD P USBDM VSSBL VD D BL
N AN D W P READ ONL Y EEPRO M SCL VSS_2 VD D 33_2 NC NC RESET LED 2 LED 1 N AN D AL E VSS_3
36 35 34 33 32 31 30 29 28 27 26 25
N A N D _A L E
V33
C17 RESET 100nF R1 LED 2 220 GREEN L ED LED2 N AN D _W P LED 1
N AN D _W P
V33
V33
C1 100nF
C2 1uF
LED 1
R2 220
V33
RED LED
13 14 15 16 17 18 19 20 21 22 23 24
V18_U SB
J 1
On Board Flash 2-4 only available on ST72681 /R21
C14 10nF C13 10nF C12 10nF C11 470nF
VBU S DD+ GND
U SB CON
1 2 3 4
V33
N A N D _C E 4 N A N D _C E 3 N A N D _C E 2 N A N D _C E 1 N A N D _R E N A N D _W E N A N D _C L E
V33
ST72681/R20 only supports single NAND Flash Chip Enable configuration (one NAND device with one Chip Enable signal). Note that pins NAND_RnB2, NAND_CE2, NAND_CE3 and NAND_CE4 should remain unconnected. ST72681/R21 can support up to four NAND Flash Chip Enable signals. The application can use one of the following configurations:
One NAND device with four Chip Enable signals; NAND_CE1, NAND_CE2, NAND_CE3 and NAND_CE4 are used. One NAND device with two Chip Enable signals; NAND_CE1 and NAND_CE2 are used. One NAND device with one Chip Enable signal; only NAND_CE1 is used. Two NAND devices with two Chip Enable signals; NAND_CE1 and NAND_CE2 are used to select the first NAND device and NAND_CE3 and NAND_CE4 to select the second NAND device. Two NAND devices with one Chip Enable signal; NAND_CE1 and NAND_CE2 are used to select is used to select the first NAND device and the 2nd NAND device, respectively. 4 NAND devices with 1Chip Enable signal; NAND_CE1 selects the first NAND device, NAND_CE2 the 2nd NAND device, NAND_CE3 to select the third, and NAND_CE4 to select the fourth NAND device.
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N A N D _C L E N A N D _A L E N A N D _W E N A N D _W P
N A N D _C L E N A N D _A L E N A N D _W E N A N D _W P
N A N D _R nB N A N D _R E N A N D _C E 4
N A N D _R nB N A N D _R E N A N D _C E 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
N A N D _C L E N A N D _A L E N A N D _W E N A N D _W P
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
N A N D _FL A SH _T SO P48
N A N D _FL A SH _T SO P48
V33
NC N C / R ES # NC NC NC NC RB4 NC IO 7 / RB3 IO 6 / G N D / B2 R IO 5 / #R / B #R E IO 4 / #C E NC NC #C E 2 NC N C/ RE P V CC V CC V SS V SS #C E 3 NC #C E 4 NC NC C LE IO 3 / A LE #W E IO 2 / IO 1 #W P / IO 0 / NC NC NC NC NC NC NC NC NC
3
2
U2
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
U3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
ST72681
NAND interface
4
4.1
NAND interface
NAND support table
Table 6. Known NAND compatibility guide for R20 and R21 devices
NAND size (Mbytes or Gbytes) and type 128 MB; SLC2K; Single CE 256 MB; SLC2K; Single CE 512 MB; SLC2K; Single CE 512 MB; SLC2K; Single CE 512 MB; SLC2K; Dual CE 1 GB; SLC2K; Single CE 1 GB; SLC2K; Dual CE 2 GB; SLC2K; Dual CE 4 GB; SLC2K; Quad CE 512 MB; MLC2K; Single CE 1 GB; MLC2K; Single CE 2 GB; MLC2K; Dual CE 4 GB; MLC2K; Quad CE 128 MB; SLC2K; Single CE 256 MB; SLC2K; Single CE 512 MB; SLC2K; Single CE 256 MB; MLC2K; Single CE 512 MB; MLC2K; Single CE 1 GB; MLC2K; Single CE 128 MB; SLC2K; Single CE 256 MB; SLC2K; Single CE 512 MB; SLC2K; Single CE 1 GB; SLC2K; Single CE 512 MB; MLC2K; Single CE 128 MB; SLC2K; Single CE 256 MB; SLC2K; Single CE 512 MB; SLC2K; Single CE 512 MB; SLC2K; Dual CE 1 GB; SLC2K; Single CE 512 MB; MLC2K; Single CE 1 GB; MLC2K; Dual CE 256 MB; SLC2K; Single CE 512 MB; SLC2K; Single CE 1 GB; SLC2K; Dual CE Number of NAND devices supported R20 device Samsung K9F1G08U Samsung K9F2G08U Samsung K9F4G08U Samsung K9K4G08U Samsung K9W4G08U Samsung K9K8G08U Samsung K9W8G08U Samsung K9WAG08U Samsung K9NBG08U Samsung K9G4G08U Samsung K9L8G08U Samsung K9HAG08U Samsung K9MBG08U Toshiba TH58NVG0S3 Toshiba TH58NVG1S3 Toshiba TH58NVG2S3 Toshiba TH58NVG1D4 Toshiba TH58NVG2D4 Toshiba TH58NVG3D4 ST NAND01GW3B ST NAND02GW3B ST NAND04GW3B ST NAND08GW3B ST NAND04GW3C Hynix HY27UF081G2M Hynix HY27UG082G2M Hynix HY27UG084G2M Hynix HY27UH084G5M Hynix HY27UH088G2M Hynix HY27UT084G2M Hynix HY27UU088G5M Micron 29F2G08AA Micron 29F4G08BA Micron 29F8G08FA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R21 device 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1 or 2 1, 2, 3 or 4 1 or 2 1 or 2 1 1, 2, 3 or 4 1, 2, 3 or 4 1 or 2 1 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1, 2, 3 or 4 1 or 2 1, 2, 3 or 4 1, 2, 3 or 4 1 or 2 1, 2, 3 or 4 1, 2, 3 or 4 1 or 2
NAND name
Note:
This list is provided as a guide only as it is not possible to automatically guarantee support for all the additions and updates across the listed ranges of manufacturers' devices.
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NAND interface
ST72681
4.2
NAND error correction
No NAND Flash memory arrays are guaranteed by manufacturers to be error-free. Error occurrence depends on the Flash cell type (MLC or SLC). The ST72681 embeds hardware and firmware mechanisms to correct the errors.
4.2.1
Hardware error correction
The ST72681 embeds a Reed-Solomon algorithm-based hardware cell. This cell directly manages 512-byte data packets on the NAND I/O system. Based on a data packet contents, the cell generates an 80-bit Error Correction Code (ECC) consisting of 8 words each containing 10 bits. During write operations to NAND memory, the 512-bytes of data and the ECC are stored together in the same page. The ECC is stored in the corresponding Redundant Area (RA), using 10 bytes. During read operations, the 512-bytes of data and the 8 ECC words are read back and are passed through the Reed-Solomon cell for decoding. The cell allows the correction of 4 symbols in this 520-symbol packet (512 symbols from data + 8 symbols from ECC). The hardware cell gives 3 possible results:
No error detected: the data packet can be used as it is. Correctable error detected: the corrected data are available in a specific 512-byte buffer in the Reed-Solomon cell and are ready to use. Uncorrectable error detected: data corruption is not repairable.
4.2.2
Firmware error management
The firmware defines the error correction possibilities with the corrected data packet. When data is not repairable, the block is considered as bad and replaced by another one. See below for further information.
4.3
Management of bad NAND blocks
NAND device manufacturers deliver their products with factory-marked bad blocks. This marking depends on the manufacturer and the NAND type (page size, memory technology, etc.). The ST72681 supports all bad block markings currently available on the market.
4.3.1
Bad block identification
During firmware initialization, the MCU scans the entire NAND configuration to identify bad blocks. A bad block is defined as follows:
5 different Block Status bytes are considered: 4 Status bytes from page 0 and 1 from an other page (page 127 for MLC NAND; page 1 for SLC NAND). The considered block is declared bad if 1 of these 5 bytes contains 4 bits or more at 0.
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ST72681
NAND interface
4.3.2
Bad block replacement
The firmware works with groups of 1024 blocks, called zones. A complete NAND configuration can contain several zones. Each zone is described in a Look Up Table (LUT) containing 1024 entries. A LUT is composed of 3 parts: used blocks, free blocks and bad blocks.
The "bad blocks" part contains as many entries as the number of bad blocks identified in that zone. The "used blocks" part can have a size of 1000, 900 or 500 entries. This size is configurable and also depends on the number of identified bad blocks. The "free blocks" part contains the remaining entries.
The used blocks part is used to do a correspondence between NAND blocks and logical address ranges. This system allows all bad blocks to be masked from the Host. As a result, bad blocks are never seen. Only a range of logical addresses are visible which correspond to the sum of the used blocks part of all zones.
4.3.3
Late fail block
During normal application life, defects can appear in the NAND memory. Under certain conditions, these defects are not correctable and the corresponding block is declared as "bad". In this case, new bad blocks are identified in the bad blocks part of the LUT and replaced by new blocks from the "free blocks" part.
4.4
Wear levelling
During normal application life, the NAND is written and erased (by block) many times. The NAND device is guaranteed for a limited number of writes (about 100 000 cycles). As a consequence, the controller must keep write/erase operations to a minimum for any individual block. A method to limit these cycles is to use a "Wear Levelling" scheme between all NAND blocks.
4.4.1
LUT usage
The LUT is used for transfers between a logical address range and a block. It contains free blocks which are used in the "wear levelling" scheme. During write command treatment, the firmware calculates the zones, blocks and pages for data write access. In a block write operation, the firmware applies the following scheme to avoid block wearing:
The least recently-used block is chosen from the free block part of the LUT. Valid data from the old block is copied to the new block. New data from the write command is written to the new block. The old block is erased. The LUT is updated after identifying the new block in the used block part and the old block in the free block part.
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NAND interface
ST72681
Using this scheme, a logical address range doesn't correspond to a constant block. A write command repeated several times to the same logical address writes physically into different blocks. This method shares the wearing evenly across all blocks of the concerned zone.
4.5
NAND interface configuration
Applications based on ST72681 can be configured through a dedicated PC software tool. The NAND RE and WE signals frequencies can be independently configured to 30 MHz, 20 MHz, 15 MHz, 12 MHz and 10 MHz. The logical size reduction factor can be configured to 90% or 50% in the event of having too many bad blocks. this option resizes the used blocks part of the LUT to 900 or 500.
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ST72681
Mass storage implementation
5
5.1
Mass storage implementation
USB characteristics
The ST72681 is compliant with USB 2.0 specification. It is able to operate in both high speed and full speed modes using a bidirectional control endpoint 0 and a bidirectional bulk endpoint 2. It automatically recognizes the speed to use on the bus by a process of negotiation with USB Host.
5.2
5.2.1
BOT / SCSI implementation
BOT specification
The USB Mass Storage Class Bulk Only Transport (BOT) specification version 1.0 is implemented. It allows the device to be recognized by the host as a mass-storage USB device.
5.2.2
SCSI specification
Moreover, inside BOT transfers, SCSI commands are encapsulated for mass storage operations. The related specifications are SBC-2 revision 10 (SCSI Block Commands 2) and SPC-4 revision 7a (SCSI Primary Commands 4).
5.2.3
Bootability specification
The USB Mass Storage Specification for Bootability revision 1.0 is implemented. It allows the PC host to boot the operating system from the USB mass storage application. In this case, the Host uses BOT LUN 0 (logical unit number). A specific tool must be used to format the logical drive in order to make it bootable by programming the correct information.
5.3
Multi-LUN device characteristics
The application can be configured with a dedicated PC software tool as a multi-LUN device. In this case, up to 3 different drives are available: public drive, additional drive and private drive. Public and additional drives can be configured as removable drive, hard disk drive or CDROM drive.
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Mass storage implementation
ST72681
5.3.1
Public drive
The public drive is the default configuration in a mono-LUN mode. In this default case, it is declared as a removable drive. The public drive is mandatory and can not be removed from the configuration. By customization (using PC software), it can be declared as a removable drive, a CD-ROM drive or a hard disk drive. This drive is the LUN 0 in BOT commands.
5.3.2
Private drive
The Private drive is optional. Its type is "removable drive" and is not configurable. This drive is protected by password and cannot be directly accessed through the PC operating system. A PC software tool is necessary to send a command with the password to unlock the device. The device is then open and accessible by the PC operating system until reset or reception of a new command to lock the drive. This drive is the LUN 1 in BOT commands.
5.3.3
Additional drive
The additional drive is optional. Its type can be "removable drive", "hard disk drive" or "CDROM drive". This drive is LUN 1 in BOT commands if the private drive option is not active, and is LUN 2 if the private drive option is active.
5.3.4
CD-ROM considerations
When a drive is declared as CD-ROM, the ST72681/R21 manages this drive with a logical block size of 2 Kbytes. To be correctly recognized by the host, it is preferable to build a CDFS partition on this CD-ROM. See the `ST7268x Production Tool User Manual' for more information. Note that the ST72681/R20 doesn't consider the CD-ROM partition as a specific case. The logical block size is 512 bytes and any file system can be used. In both cases, the CD-ROM partition allows the use of the autorun operating system feature. During device connection, the CD-ROM partition is recognized and the host tries to run the application corresponding to the `autorun.inf' file present into this CD-ROM partition.
5.4
Mass storage interface configuration
In addition to the parameters already described as configurable in the previous chapters, additional customizable information includes:
USB parameters: VID, PID, all string information SCSI parameters: strings for inquiry commands
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ST72681
Human interface implementation
6
6.1
Human interface implementation
LED behavior
The application is designed to manage 2 LEDs. This behavior is configurable through PC dedicated software: `ST7268x Production Tool'. By default, LED 1 responds to NAND access activity and LED 2 responds to USB activity. Use of LED 1 is optional. When this option is not active, LED 2 reacts to both USB and NAND activity.
6.2
Read only switch
The READ ONLY pin of the ST72681 is an input pin to be connected to VDD or GND depending on the behavior of the device.
When this pin is connected to GND, no limitations are applied on the PC command received. When this pin is connected to VDD or unconnected, the firmware filters all accesses to the NAND which modify the NAND state (write, erase, etc.) and returns an error to the PC.
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Electrical characteristics
ST72681
7
7.1
7.1.1
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the Devices with an ambient temperature at TA = 25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3).
7.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25C and VDD33 = 3.3V. They are given only as design guidelines and are not tested.
7.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
7.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 4. Figure 4. Pin loading conditions
DEVICE PIN
CL
7.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 5. Figure 5. Pin input voltage
DEVICE PIN
V IN
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ST72681
Electrical characteristics
7.2
Absolute maximum ratings
Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the Device. This is a stress rating only and functional operation of the Device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
7.2.1
Voltage characteristics
Table 7.
Symbol VDD33 - VSS VIN (1) (2) VESD(HBM) VESD(MM) Supply voltage Input voltage on any other pin
Voltage characteristics
Ratings Maximum value 4.0 VSS - 0.3 to VDD33 + 0.3 Unit V V
Electro-static discharge voltage (Human Body Model) See Section 7.6.3 on page 21 Electro-static discharge voltage (Machine Model)
1. Directly connecting the RESET and I/O pins to VDD33 or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for RESET, 10k for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD33 or VSS. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN > VDD33 while a negative injection is induced by VIN < VSS.
7.2.2
Current characteristics
Table 8.
Symbol IVDD33 IVSS
Current characteristics
Ratings Total current into VDD33 power lines (source) (1) Total current out of VSS ground lines (sink) Output current sunk by any I/O (type D2)
(1)
Maximum value 200 200 25
Unit
mA IIO
(2)
Output current sunk by any I/O (type D4) Output current sunk by any I/O (type D8) Output current source by any I/Os and control pin
35 50 -2 5
1. All power supply (VDD33) and ground (VSS) lines must always be connected to the external supply. 2. Refer to Table 5: General Purpose I/O Ports / Mass Storage I/Os for the output drive capability of each of the I/Os.
7.2.3
Thermal characteristics
Table 9.
Symbol TSTG TJMAX
Thermal characteristics
Ratings Storage temperature range Maximum junction temperature Value -65 to +150 120 Unit C C
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Electrical characteristics
ST72681
7.3
7.3.1
Operating conditions
General operating conditions
Table 10.
Symbol f CPU VDD33 TA
General operating conditions
Parameter Internal clock frequency Power supply Ambient temperature range Conditions Min 0 3.0 0 Max 30 3.6 70 Unit MHz V C
Figure 6.
Guaranteed functionality range
fCPU [MHz] FUNCTIONALITY GUARANTEED IN THIS AREA
30 FUNCTIONALITY NOT GUARANTEED 15 IN THIS AREA 6 3 0 2.0 2.5 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE [VDD33]
7.4
7.4.1
Supply current characteristics
RUN and SUSPEND modes
Table 11.
Symbol IDD
RUN and SUSPEND modes
Parameter Supply current in RUN mode Conditions fOSC = 12 MHz Min. 15 60 Typ. 25 90 Max. Unit 35 190 mA A
Supply current in SUSPEND mode VDD33 = 3.3V, TA = +25C
7.4.2
Supply and clock managers
Table 12.
Symbol IDD(CK)
Supply and clock managers
Parameter Supply current of crystal oscillator (3) Conditions Typ. (1) 1000 Max. (2) 2000 Unit A
1. Typical data are based on TA = 25C and fCPU = 12 MHz. 2. Not tested in production, guaranteed by characterization. 3. Data based on characterization results done with the external components specified in Section 7.5.2: Crystal oscillator, not tested in production.
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ST72681
Electrical characteristics
7.5
Clock and timing characteristics
Subject to general operating conditions for VDD33, fOSC, and TA.
7.5.1
General timings
Table 13.
Symbol tc(INST) tv(IT)
General timing characteristics
Parameter Instruction cycle time Interrupt reaction time tv(IT) = tc(INST) + 10
(2)
Conditions
Min. 2
Typ. (1) 3 200
Max. 12 800 22 1.466
Unit t CPU ns t CPU s
fCPU = 15 MHz fCPU = 12 MHz
133 10 0.666
1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles required to finish executing the current instruction.
7.5.2
Crystal oscillator
The ST72681 internal clock is supplied from a crystal oscillator. All the information given in this paragraph are based on characterization results with specified typical external components. In the application the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal manufacturer for more details (frequency, package, accuracy...). Table 14.
Symbol fOSC CKACC OSC
Crystal oscillator characteristics
Parameter Oscillator frequency Total crystal oscillator accuracy abs. value + temp + aging Crystal oscillator duty cycle (1) 45 50 Conditions Min. Typ. 12 60 55 Max. Unit MHz ppm %
1. The crystal oscillator duty cycle has to be adjusted through the two CL capacitors. Refer to the crystal manufacturer for more details.
Figure 7.
Typical application with a crystal oscillator
VDDA
CL OSCIN CRYSTAL CL OSCOUT RsOscout (1)
Device
1. Depending on the crystal oscillator power dissipation, a serial resistor RsOscout may be added. Refer to the crystal oscillator manufacturer for more details.
Table 15.
Typical CL and RS values by crystal oscillator
Supplier NDK Typical crystal oscillator AT51 or AT41 CL (pF) 16 RsOscout () 560
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Electrical characteristics
ST72681
7.6
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
7.6.1
Functional EMS (electro magnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD33 and VSS33 through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:
Corrupted program counter Unexpected reset Critical Data corruption (control registers...)
Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 16.
Symbol
EMC characterization and optimization values
Parameter Conditions Level/ Class 4B
VFESD
VDD33 = 3.3V, TA = +25C, fOSC = 12 MHz Voltage limits to be applied on any I/O complies with IEC 1000-4-2 pin to induce a functional disturbance specifications Fast transient voltage burst limits to be VDD33 = 3.3V, TA = +25C, fOSC = 12 MHz applied through 100pF on VDD33 and complies with IEC 1000-4-4 VSS33 pins to induce a functional specifications disturbance
VFFTB
4A
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ST72681
Electrical characteristics
7.6.2
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Table 17.
Symbol
Electromagnetic interference
Parameter Conditions(1) Monitored Frequency Band Max vs. [fOSC@12 MHz] 20 25 25 4 dBV Unit
SEMI
Peak level
0.1 MHz to 30 MHz VDD33 = 3.3V, TA = +25C, 30 MHz to 130 MHz complies with SAE J 1752/3 130 MHz to 1 GHz specifications SAE EMI Level
1. Refer to Application Note AN1709 for data on other package types.
7.6.3
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.
Electro-static discharge (ESD)
Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. Table 18.
Symbol
Absolute Maximum Ratings
Ratings Conditions Max.(1) Unit 2000 V
VESD(HBM) Electro-static discharge voltage (Human Body Model) TA = +25C
1. Data based on characterization results, not tested in production.
Static and dynamic latch-up
LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test complies with EIA/JESD 78 IC latch-up specifications. For more details, refer to the application note AN1181. DLU: Electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test complies with IEC1000-4-2 and SAEJ1752/3 specifications. For more details, refer to the application note AN1181.
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Electrical characteristics Table 19.
Symbol LU DLU
ST72681
Electrical sensitivity values
Parameter Static latch-up class Dynamic latch-up class TA = +25C VDD33 = 3.3V, fOSC = 12 MHz, TA = +25C Conditions Class (1) A A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard).
7.7
7.7.1
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD33, fOSC, and TA unless otherwise specified. Table 20.
Symbol VIL VIH Vhys IL IL5V RPU
General I/O port pin characteristics
Parameter Input low level voltage Input high level voltage Schmitt trigger voltage hysteresis (1) Input leakage current VSS VIN VDD33, standard I/Os VSS VIN VDD33 VIN = 5V, 25C Weak pull-up equivalent resistor (2) VIN = VSS VDD33 = 3.3V 32 30 50 75 k TTL ports 0.85 x VDD33 400 1 10 mV A Conditions Min. Typ. Max. 0.16 x VDD33 Unit
V
5V tolerant input leakage current
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. 2. The RPU pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, tested in production at VDD33 max.
Figure 8.
Typical VIL and VIH standard I/Os
Vil/ Vi h (V)
2.5 2
Vil/Vih (V)
1.5 1 0.5 0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Vdd (V)
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ST72681 Figure 9. Typical RPU vs. VDD33 with VIN=VSS
60 55 50 45 40 35 30 2.7 2.8 2.9 3 3.1 3.2 Vdd (V) 3.3 3.4 3.5 3.6
Electrical characteristics
I/Os pullup resistance
Figure 10. Two typical Applications with unused I/O Pin
VDD33
10k
Device
10k UNUSED I/O PORT UNUSED I/O SED I/O PORT UNU PORT 10k
I/Os pullup resistance (kOhms)
DeviceDevice
7.7.2
Output driving current
Subject to general operating conditions for VDD33, fOSC, and TA unless otherwise specified. Table 21.
Symbol
Output driving current
Parameter Output low level voltage for a D2 I/O pin when 8 pins are sunk at same time (see Figure 11) Conditions IIO = 2 mA IIO = 4 mA
VDD33 = 3.3V
Min.
Max. 300 400 500 600 600 600
Unit
VOL (1)
Output low level voltage for a D4 I/O pin when 8 pins are sunk at same time (see Figure 12) Output low level voltage for a D8 I/O pin when 8 pins are sunk at same time (see Figure 13 ) Output high level voltage for a D2 I/O pin when 8 pins are sourced at same time (see Figure 14)
mV
IIO = 8 mA IIO = 2 mA IIO = 4 mA IIO = 8 mA
VDD33VOH (2)
Output high level voltage for a D4 I/O pin when 8 pins are sourced at same time (see Figure 15 ) Output high level voltage for a D8 I/O pin when 8 pins are sourced at same time (see Figure 16)
mV
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 7.2.2: Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 7.2.2: Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVDD33. True open drain I/O pins do not have VOH.
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Electrical characteristics Figure 11. Typical VOL at VDD33 = 3.3V (I/O D2)
140 120
ST72681
Vol 2mA (mV)
100 80 60 40 20 0 0 1 2 3 4
Iol (mA)
Figure 12. Typical VOL at VDD33 = 3.3V (I/O D4)
140 120 100 80 60 40 20 0 0 1 2 3 4 5 6
Vol 4mA (mV)
Iol (mA)
Figure 13. Typical VOL at VDD33 = 3.3V (I/O D8)
140 120
Vol 8mA (mV)
100 80 60 40 20 0 0 2 4 6 8 10
Iol (mA)
Figure 14. Typical VDD33-VOH vs. VDD33 (I/O D2)
200
Voh 2mA (mV)
150 100 50 0 0 1 2 3 4
Ioh (mA)
Figure 15. Typical VDD33-VOH vs. VDD33 (I/O D4)
180 160 140 120 100 80 60 40 20 0 0 1 2 3 4 5 6
Voh 4mA (mV)
Ioh (mA)
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ST72681 Figure 16. Typical VDD33-VOH vs. VDD33 (I/O D8)
180 160 140 120 100 80 60 40 20 0 0 2 4 6 8 10
Electrical characteristics
Voh 8mA (mV)
Ioh (mA)
7.8
7.8.1
Control pin characteristics
Asynchronous RESET pin
TA = 0 to +55 C unless otherwise specified. Table 22.
Symbol VIL VIH Vhys RON teh(RSTL) tg(RSTL) tew(RSTL) tiw(RSTL)
RESET pin characteristics
Parameter Input low level voltage (1) Input high level voltage Schmitt trigger voltage hysteresis1) Pull-up equivalent resistor External reset pulse hold time (2) Filtered glitch duration External reset pulse
(3)
Conditions
Min.
Typ.
Max. 0.16 x VDD33
Unit
0.85 x VDD33 450 VDD33 = 3.3V VDD33 = 2V 2.5 200 500 2 20 40 100 80
V
mV k s ns s t CPU
duration (4)
Internal reset pulse duration
1. The level on the RESET pin must be free to go below the VIL max. level specified in Section 7.8.1: Asynchronous RESET pin. Otherwise the reset will not be taken into account internally. 2. To guarantee the reset of the Device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below teh(RSTL) can be ignored. Not tested in production, guaranteed by design. 3. The reset network protects the device against parasitic resets. 4. The external reset duration must respect this timing to guarantee a correct start-up of the internal regulator at power-up. Not tested in production, guaranteed by design.
Figure 17. Typical RON on RESET pin
100
NRESET pullup (kOhms)
90 80 70 60 50 40 2 2.5 3 3.5
Vdd (V)
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Electrical characteristics
ST72681
7.9
7.9.1
Other communication interface characteristics
MSCI parallel interface
Figure 18. Timing diagrams for input mode (with max load on CTRL signal = 50 pF)
CTRL
external
DATA
ext device
DATA(i)
DATA(i+1)
tDS tDS is the setup time for data sampling
Figure 19. Timing diagrams for output mode (with max CTRL signal = 50 pF, DATA)
CTRL
external
DATA
external
DATA(i)
DATA(i+1)
tDO tDO is the data output time for data sampling
Table 23.
Symbol tDS tDO CCTRL CDATA
MSCI Parallel Interface: DC Characteristics
Parameter Data Setup Time Data Output time CTRL line capacitance Data line capacitance Conditions Min. Typ. (1) 11 6 50 50 Max. Unit ns ns pF pF
1. Data based on design simulation and not tested in production.
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ST72681
Electrical characteristics
7.9.2
Universal serial bus interface (USB)
Table 24.
Symbol IDDsuspend RPU
DC characteristics
Parameter Suspend current Pull-up resistor (2) Conditions VDD33 = 3.3V, Powerdown mode, 25C (1) Min. 60 Typ. 90 1.5 Max. 190 Unit uA k
Full speed mode VTERM VOH VOL VCRS Termination voltage High level output voltage Low level output voltage Crossover voltage 1.3 0.8 2.8 2.0 3.6 0.8 2.0 V V V V
High speed mode VHSOH VHSOL HS data signalling high HS data signalling low 400 5 mV mV
1. The values provided do not take into account the current through both the 1.5k pull-up resistor (on the device-side) and the 15k pull-down resistor (on the host-side). 2. Not tested in production, guaranteed by characterization.
Table 25.
Symbol
Timing characteristics
Parameter Conditions Min. Max. Unit
Full speed mode tF R tFF Rise time Fall time CL= 50 pF CL= 50 pF 4 4 20 20 ns ns
High speed mode tHSR t HSF tHSDRAT Rise time Fall time HS data rate 479.76 500 (1) 500 (1) 480.24 ps ps Mb/s
1. Not tested in production, guaranteed by characterization.
Table 26.
USB High Speed Transmit Waveform requirements
Voltage Level (DP - DN) Time 2.082 to 2.084 ns 5% UI 95% UI 35% UI 65% UI 35% UI 65% UI 475 mV -475 mV 0V 0V 300 mV 300 mV -300 mV -300 mV
Unit Interval (UI) Level 1 Level 2 Point 1 Point 2 Point 3 Point 4 Point 5 Point 6
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Electrical characteristics Figure 20. USB signal eye diagram
ST72681
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ST72681
Package mechanical data
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 21. 48-pin low profile quad flat package outline
D D1 A1 b A A2
E1
E
e
L1 L
c
Table 27.
Dim.
48-pin low profile quad flat package dimensions
mm Min. Typ. Max. 1.60 0.05 1.35 0.17 0.09 9.00 7.00 9.00 7.00 0.50 0 0.45 3.5 0.60 1.00 Number of Pins 48 7 0.75 0 0.018 1.40 0.22 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 0.354 0.276 0.354 0.276 0.020 3.5 0.024 0.039 7 0.030 0.055 0.009 Min. inches(1) Typ. Max. 0.063 0.006 0.057 0.011 0.008
A A1 A2 b C D D1 E E1 e L L1 N
1. Values in inches are converted from mm and rounded to 3 decimal digits.
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Device ordering information
ST72681
9
Device ordering information
Table 28. Feature comparison table
Description Firmware revision R21 upgrades the number of supported NAND Flash devices from 1 to 4 in a single channel. AutoRun runs a program when the USB Flash Drive is inserted into a computer.
Features added in the ST72681/R21 versus ST72681/R20 Suppor t for up to 4 NAND Flash devices
Continued AutoRun CDROM partition support
Table 29.
Ordering information
Part number Package TQFP48 7x7mm TQFP48 7x7mm Operating voltage 3.0V to 3.6V 3.0V to 3.6V Temperature range 0C to +70C 0C to +70C
ST72681/R20 ST72681/R21 (latest firmware revision)
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ST72681
Revision history
10
Revision history
Table 30.
Date
Document revision history
Revision Changes Changed status of the document Changed description on 1st page Removed unconnected pins in Table 5 on page 7 Changed Table 4 on page 6 Changed pin 5 description in Table 3 on page 6 Changed section 3 on page 7 Changed Figure 3 on page 8 and Figure 4 Electrical Characteristics section added, Section 4 on page 9 Additional features listed on front page Status of document changed to Datasheet Application schematics modified, Figure 4 removed Section 4.6 (Memory Characteristics) removed VDDOUSB marked as O (output) in Table 2 on page 6 Additional features listed on front page Application schematics modified, Figure 3 on page 8 Feature comparison table added for R20 firmware update, Table 28 Figure 3 on page 8 updated, with note added Additional features listed on front page related to firmware release R21. Application schematics updated for R21, Figure 3 on page 8 Feature comparison table added for R21 firmware update, Table 28 IDDsuspend values and note updated, Table 24 Updated information in Table 6: Known NAND compatibility guide for R20 and R21 devices on page 9. Added Section 4.2: NAND error correction on page 10, Section 4.3: Management of bad NAND blocks on page 10, Section 4.4: Wear levelling on page 11 and Section 4.5: NAND interface configuration on page 12. Added Section 5: Mass storage implementation on page 13 and Section 6: Human interface implementation on page 15. Added internal clock frequency (fCPU) value in Table 10: General operating conditions on page 18.
27-May-2005
1.0
18-Nov-2005
2.0
06-Feb-2006
3.0
09-Jan-2007
4.0
30-Aug-2007
5.0
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ST72681
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