SG3524
REGULATING PULSE WIDTH MODULATORS
COMPLETE PWM POWER CONTROL CIRCUITRY UNCOMMITTED OUTPUTS FOR SINGLEENDED OR PUSH PULL APPLICATIONS LOW STANDBY CURRENT 8mA TYPICAL OPERATION UP TO 300KHz 1% MAXIMUM TEMPERATURE VARIATION OF REFERENCE VOLTAGE DESCRIPTION The SG3524 incorporates on a single monolithic chip all the function required for the construction of regulating power suppies inverters or switching regulators. They can also be used as the control element for high power-output applications. The SG3524 family was designed for switching regulators of either polarity, transformer-coupled dcto-dc converters, transformerless voltage doublers and polarity converter applications employing fixed-frequency, pulse-width modulation techniques. The dual alternating outputs allows either single-ended or push-pull applications. BLOCK DIAGRAM
DIP16 SO16
ORDERING NUMBERS: SG3524N (DIP16) SG3524P (SO16)
Each device includes an on-ship reference, error amplifier, programmable oscillator, pulse-steering flip flop, two uncommitted output transistors, a high-gain comparator, and current-limiting and shut-down circuitry.
July 2000
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
SG3524
ABSOLUTE MAXIMUM RATINGS
Symbol VIN IC IR IT Ptot Tstg Top Supply Voltage Collector Output Current Reference Output Current Current Through CT Terminal Total Power Dissipation at Tamb = 70C Storage Temperature Range Operating Ambient Temperature Range: Parameter Value 40 100 50 5 1000 65 to 150 0 to 70 Unit V mA mA mA mW C C
PIN CONNECTION (Top view)
THERMAL DATA
Symbol Rth j-amb Rth j-alumina Parameter Thermal Resistance Junction-ambient Thermal Resistance Junction-alumina (*) Max. Max. DIP16 80 SO16 50 Unit C/W C/W
(*) Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 x 20mm; 0.65mm thickness with infinite heatsink.
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SG3524
ELECTRICAL CHARACTERISTICS (unless otherwise stated, these specifications apply for Tj = 0 to 70C, VIN = 20V, and f = 20KHz).
Symbol VREF VREF VREF Parameter Output Voltage Line Regulation Load Regulation Ripple Rejection VREF/T VREF fMAX Short Circuit Current Limit Temperature Stability Long Term Stability Maximum Frequency Initial Accuracy f/T Voltage Stability Temperature Stability Output Amplitude Output Pulse Width ERROR AMPLIFIER SECTION VOS Ib GV CMV CMR B VO Input Offset Voltage Input Bias Current Open Loop Voltage Gain Common Mode Voltage Common Mode Rejection Small Signal Bandwidth Output Voltage Duty-cycle VIT Input Threshold Tj = 25C Tj = 25C AV = 0dB, Tj = 25C Tj = 25C % Each Output On Zero Duty-cycle Maximum Duty-cycle VCM = 2.5V 60 1.8 70 3 0.5 0 1 3.5 1 Pin 9 = 2V with Error Amp. Set for Max. Out. Tj = 25C 180 200 220 3.8 45 2 2 80 10 10 3.4 mV A dB V dB MHz V % V V A mV VIN = 8 to 40V IL = 0 to 20mA f = 120Hz, Tj = 25C VREF = 0, Tj = 25C Over Operating Temperature range Tj = 125C, t = 1000Hrs CT = 0.001F, RT = 2K RT and CT Constant VIN = 8 to 40V, Tj = 25C Over Operating Temperature Range Pin 3, Tj = 25C CT = 0.01F, Tj = 25C 3.5 0.5 Test Condition Min. 4.6 Typ. 5 10 20 66 100 0.3 20 300 5 1 2 1 Max. 5.4 30 50 Unit V mV mV dB mA % mV KHz % % % V s REFERENCE SECTION
OSCILLATOR SECTION
COMPARATOR SECTION
Input Bias Current Ib CURRENT LIMITING SECTION Sense Voltage
CMV
Sense Voltage T.C. Common Mode Voltage Collector-emitter Voltage Collector Leackage Curr. Saturation Voltage Emitter Output Voltage VCE = 40V IC = 50mA VIN = 20V RC = 2K, Tj = 25C RC = 2K, Tj = 25C VIN = 40V
0.2 1 40 0.1 17 1 18 0.2 0.1 8 10 50 2 1
mV/C
OUTPUT SECTION(each output) V A V V s s mA
tr tf Iq (*)
Rise Time Fall Time Total Standby Current
(*) Excluding oscillator charging current, error and current limit dividers, and with outputs open.
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SG3524
Figure 1: Open-loop Voltage Amplification of Error Amplifier vs. Frequency Figure 2: Oscillator Frequency vs. Timing Components.
Figure 3: Output Dead Time vs. Timing Capacitance Value.
Figure 4: Output Saturation Voltage vs. load Current.
Figure 5: Open Loop Test Circuit.
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SG3524
PRINCIPLES OF OPERATION The SG3524 is a fixed frequency pulse-withmodulation voltage regulator control circuit. The regulator operates at a frequency that is programmed by one timing resistor (RT) and one timing capacitor (CT). RT established a constant charging current for CT. This results in a linear voltage ramp at CT, which is fed to the comparator providing linear control of the output pulse width by the error amplifier. the SG3524 contains, an on-board 5V regulator that serves as a reference as well as powering the SG3524's internal control circuitry and is also useful in supplying external support functions. This reference voltage is lowered externally by a resistor divider to provide a reference within the common mode range the error amplifier or an external reference may be used. The power supply output is sensed by a second resistor divider network to generale a feedback signal to error amplifier. The amplifier output voltage is then compared to the linear voltage ramp at CT. The resulting modulated pulse out of the high-gain comparator is then steered to the appropriate output pass transistors (QA or QB) by the pulse-steering flip-flop, which is synchronously toggled by the oscillator output. The oscillator output pulse also serves as a blanking pulse to assure both output are never on simultaneously during the transition times. The width of the blanking pulse is controlled by the value of CT. The outputs may be applied in a push-pull configuration in which their frequency is half that of the base oscillator, or paralleled for single-ended applications in which the frequency is equal to that of the oscillator. The output of the error amplifier shares a common input to the comparator with the current limiting at shutdown circuitry and can be overridden by signals from either of these inputs. This common point is also available externally and may be employed to control the gain of, or to compensate, the error amplifier, or to provide additional control to the regulator. RECOMMENDED OPERATING CONDITIONS
Supply voltage VIN Reference Output Current Current trough CT Terminal Timing Resistor, RT Timing Capacitor, CT 8 to 40V 0 to 20mA - 0.03 to -2mA 1.8 to 100K 0.001 to 0.1F
cording to the approximate formula: f= 1.18 RT CT
where: RT is in K CT is in F f is in KHz Pratical values of CT fall between 0.001 and 0.1F. Pratical values of RT fall between 1.8 and 100K. This results in a frequency range typically from 120Hz to to 500KHz. BLANKING The output pulse of oscillator is used as a blanking pulse at the output. This pulse width is controlled by the value of CT.If small values of CT are required for frequency control, the oscillator output pulse width may still be increased by applying a shunt capacitance of up to 100pF from pin 3 to ground. If still greater dead-time is required, it should be accomplished by limiting the maximum duty cycle by clamping the output of the error amplifier. This can easily be done with the circuit below: Figure 6.
TYPICAL APPLICATIONS DATA OSCILLATOR The oscillator controls the frequency of the SG3524 and is programmed by RT and CT ac-
SYNCRONOUS OPERATION When an external clock is desired, a clock pulse of approximately 3V can be applied directly to the oscillator output terminal. The impedance to ground at this point is approximately 2K. In this configuration RT CT must be selected for a clock period slightly greater than that the external clock. If two more SG2524 regulators are to be operated synchronously, all oscillator output terminals should be tied together, all CT terminals connected to a single timing capacitor, and timing resistor connected to a single RT terminal. The other RT terminals can be left open or shorted to VREF. Minimum lead lengths should be used between the CT terminals.
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SG3524
Figure 7: Flyback Converter Circuit.
Figure 8: PUSH-PULL Transformer-coupled circuit.
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SG3524
DIM. MIN. a1 B b b1 D E e e3 F I L Z 0.51 0.77
mm TYP. MAX. MIN. 0.020 1.65 0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27 0.030
inch TYP. MAX.
OUTLINE AND MECHANICAL DATA
0.065 0.020 0.010 0.787 0.335 0.100 0.700 0.280 0.201 0.130
DIP16
0.050
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SG3524
mm MIN. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S 3.8 4.6 0.4 9.8 5.8 1.27 8.89 4 5.3 1.27 0.62 8(max.) 0.150 0.181 0.016 0.35 0.19 0.5 45 (typ.) 10 6.2 0.386 0.228 0.050 0.350 0.157 0.209 0.050 0.024 0.394 0.244 0.1 TYP. MAX. 1.75 0.25 1.6 0.46 0.25 0.014 0.007 0.020 0.004 MIN. inch TYP. MAX. 0.069 0.009 0.063 0.018 0.010
DIM.
OUTLINE AND MECHANICAL DATA
SO16 Narrow
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
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SG3524
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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