TS555
Low power single CMOS timer
Features
Very low power consumption: 110 A typ at VCC = 5 V 90 a typ at VCC = 3 V High maximum astable frequency of 2.7 MHz Pin-to-pin functionally-compatible with bipolar NE555 Wide voltage range: +2 V to +16 V Supply current spikes reduced during output transitions High input impedance: 1012 Output compatible with TTL, CMOS and logic MOS D SO8 (Plastic micropackage) N DIP8 (Plastic package)
Description
The TS555 is a single CMOS timer with a very low consumption: (Icc(TYP) TS555 = 110 A at VCC = +5 V versus Icc(TYP) NE555 = 3 mA), and high frequency: (ff(max.) TS555 = 2.7 MHz versus f(max) NE555 = 0.1 MHz). Timing remains accurate in both monostable and astable mode. The TS555 provides reduced supply current spikes during output transitions, which enable the use of lower decoupling capacitors compared to those required by bipolar NE555. With the high input impedance (1012), timing capacitors can also be minimized.
P TSSOP8 (Thin shrink small outline package)
Pin connections (top view)
GND Trigger Output Reset
1 2 3 4
8 7 6 5
VCC Discharge Threshold Control Voltage
November 2008
Rev 2
1/20
www.st.com 20
Absolute maximum ratings and operating conditions
TS555
1
Absolute maximum ratings and operating conditions
Table 1.
Symbol VCC IOUT Supply voltage Output current Thermal resistance junction to ambient DIP8 (1) SO8 (2) TSSOP8 (2) Thermal resistance junction to case DIP8 (1) SO8 (2) TSSOP8 (2) Junction temperature Storage temperature range Human body model (HBM) ESD Machine model (MM)(4)
(5) (3)
Absolute maximum ratings
Parameter Value +18 100 85 125 120 41 40 37 +150 -65 to +150 1500 200 1000 V Unit V mA
Rthja
C/W
Rthjc
C/W
Tj Tstg
C C
Charged device model (CDM)
1. Short-circuits can cause excessive heating. These values are typical and specified for a single layer PCB. 2. Short-circuits can cause excessive heating. These values are typical and specified for a four layers PCB. 3. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5k resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. 4. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 ). This is done for all couples of connected pin combinations while the other pins remain floating. 5. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to the ground.
Table 2.
Symbol VCC IOUT
Operating conditions
Parameter Supply voltage Output sink current Output source current Operating free air temperature range TS555C TS555I TS555M Value 2 to 16 10 50 0 to +70 -40 to +125 -55 to +125 Unit V mA
Toper
C
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2
Figure 1.
TS555
V CC
R1 1 21 20 26 27 30 31 11 2 10 12 1 3
50 k
Schematic diagram
R2
Schematic diagrams
50 k R7 Threshol d 8 9 4 25
34
Control Voltage
R3
50 k Outpu t Trigger 14 18 7 2 3 24 19 28 29 3 2 D isch arge 35
R4
5 0k 5 6
R5
50 k
R6 15 1 6
17 22 3 3
5 0k
GND
RESET
Schematic diagrams
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Schematic diagrams Figure 2. Block diagram
VC C
8
TS555
Reset
4 TS555
R R1 Threshold 6 Control 5 Voltage R
+ +
Q R A S
3
Output
-
Trigger 2 R
-
B
7
Discharge
1
Ground
Table 3.
Functions table
Reset Low High High High Trigger x Low High High Threshold x x High Low Output Low High Low Previous state
Note:
LOW: level voltage minimum voltage specified. HIGH: level voltage maximum voltage specified. x: irrelevant.
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TS555
Electrical characteristics
3
Electrical characteristics
Table 4.
Symbol IC C VCL VDIS IDIS VOL VOH VTRIG ITRIG ITH VRESET IRESET
Static electrical characteristics VCC = +2 V, Tamb = +25 C, Reset to VCC (unless otherwise specified)
Parameter Supply current (no load, high and low states) Tmin. Tamb Tmax Control voltage level Tmin. Tamb Tmax Discharge saturation voltage (Idis = 1 mA) Tmin. Tamb Tmax Discharge pin leakage current Low level output voltage (Isink = 1 mA) Tmin. Tamb Tmax High level output voltage (Isource = -0.3 mA) Tmin. Tamb Tmax Trigger voltage Tmin. Tamb Tmax Trigger current Threshold current Reset voltage Tmin. Tamb Tmax Reset current 0.4 0.3 1.5 1.5 0.4 0.3 1.2 1.1 Min. Typ. 65 1.3 0.05 1 0.1 1.9 0.67 10 10 1.1 10 1.5 2.0 0.95 1.05 Max. 200 200 1.4 1.5 0.2 0.25 100 0.3 0.35 Unit A V V nA V V V pA pA V pA
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Electrical characteristics Table 5.
Symbol IC C VCL VDIS IDIS VOL VOH VTRIG ITRIG ITH VRESET IRESET
TS555
Static electrical characteristics VCC = +3 V, Tamb = +25 C, Reset to VCC (unless otherwise specified)
Parameter Supply current (no load, high and low states) Tmin. Tamb Tmax Control voltage level Tmin. Tamb Tmax Discharge saturation voltage (Idis = 1 mA) Tmin. Tamb Tmax Discharge pin leakage current Low level output voltage (Isink = 1 mA) Tmin. Tamb Tmax High level output voltage (Isource = -0.3 mA) Tmin. Tamb Tmax Trigger voltage Tmin. Tamb Tmax Trigger current Threshold current Reset voltage Tmin. Tamb Tmax Reset current 0.4 0.3 2.5 2.5 0.9 0.8 1.8 1.7 Min. Typ. 90 2 0.05 1 0.1 2.9 1 10 10 1.1 10 1.5 2.0 1.1 1.2 Max. 230 230 2.2 2.3 0.2 0.25 100 0.3 0.35 Unit A V V nA V V V pA pA V pA
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TS555 Table 6.
Symbol
Electrical characteristics Dynamic electrical characteristics VCC = +3 V, Tamb = +25 C, Reset to VCC (unless otherwise specified)
Parameter Timing accuracy (monostable)(1) R = 10 k C = 0.1 F , VCC = 2 V VCC = 3 V Timing shift with supply voltage variations (monostable) R = 10 k C = 0.1 F, VCC = 3 V 0.3 V (1) , Timing shift with temperature (1) Tmin. Tamb Tmax.5 fmax Maximum astable frequency (2) RA = 470 RB = 200 C = 200 pF , , Astable frequency accuracy RA = RB = 1 k to 100 k C = 0.1 F , Timing shift with supply voltage variations (astable mode) (2) RA = RB = 1 k to 100 k C = 0.1 F, , VCC = 3 to 5 V
tR tF
Min.
Typ.
Max.
Unit
1 1
%
0.5 75 2 5
%/V
ppm/C MHz %
(2)
0.5 25 20 100 350 -
%/V ns ns ns ns
Output rise time (Cload = 10 pF) Output fall time (Cload = 10 pF) Trigger propagation delay Minimum reset pulse width (Vtrig = 3 V)
tPD
tRPW
1. See Figure 4. 2. See Figure 6.
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Electrical characteristics Table 7.
Symbol IC C VCL VDIS IDIS VOL VOH VTRIG ITRIG ITH VRESET IRESET
TS555
Static electrical characteristics VCC = +5 V, Tamb = +25 C, Reset to VCC (unless otherwise specified)
Parameter Supply current (no load, high and low states) Tmin. Tamb Tmax Control voltage level Tmin.Tamb Tmax Discharge saturation voltage (Idis = 10 mA) Tmin. TambTmax Discharge pin leakage current Low level output voltage (Isink = 8 mA) Tmin. Tamb Tmax High level output voltage (Isource = -2 mA) Tmin. Tamb Tmax Trigger voltage Tmin. Tamb Tmax Trigger current Threshold current Reset voltage Tmin. Tamb Tmax Reset current 0.4 0.3 4.4 4.4 1.36 1.26 2.9 2.8 Min. Typ. 110 3.3 0.2 1 0.3 4.6 Max. 250 250 3.8 3.9 0.3 0.35 100 0.6 0.8 Unit A V V nA V V 1.96 2.06 V pA pA 1.5 2.0 V pA
1.67 10 10 1.1 10
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TS555 Table 8.
Symbol
m
Electrical characteristics Dynamic electrical characteristics VCC = +5 V, Tamb = +25 C, Reset to VCC (unless otherwise specified)
Parameter Timing accuracy (monostable) (1) R = 10 k C = 0.1 F , Timing shift with supply voltage variations (monostable) (1) R = 10 k C = 0.1 F,VCC = 5 V 1 V , Timing shift with temperature (1) Tmin. Tamb Tmax5 fmax Maximum astable frequency RA = 470 RB = 200 C = 200 pF , , Astable frequency accuracy (2) RA = RB = 1 k to 100 k C = 0.1 F , Timing shift with supply voltage variations (astable mode) (2) RA = RB = 10 k C = 0.1 F, VCC = 5 to 12 V ,
tR tF
Min.
Typ.
Max.
Unit
2
%
0.38 75 2.7 3
%/V ppm/C MHz %
(2)
0.1 25 20 100 350 -
%/V ns ns ns ns
Output rise time (Cload = 10 pF) Output fall time (Cload = 10 pF) Trigger propagation delay Minimum reset pulse width (Vtrig = 5 V)
tPD
tRPW
1. See Figure 4. 2. See Figure 6.
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Electrical characteristics Table 9.
Symbol IC C VCL VDIS IDIS VOL VOH VTRIG ITRIG ITH VRESET IRESET
TS555
Static electrical characteristics VCC = +12 V, Tamb = +25 C, Reset to VCC (unless otherwise specified)
Parameter Supply current (no load, high and low states) Tmin. Tamb Tmax Control voltage level Tmin. Tamb Tmax Discharge saturation voltage (Idis = 80 mA) Tmin. Tamb Tmax Discharge pin leakage current Low level output voltage (Isink = 50 mA) Tmin. Tamb Tmax High level output voltage (Isource = -10 mA) Tmin. Tamb Tmax Trigger voltage Tmin. Tamb Tmax Trigger current Threshold current Reset Voltage Tmin. Tamb Tmax Reset current 0.4 0.3 10.5 10.5 3.2 3.1 7.4 7.3 Min. Typ. 170 8 0.09 1 1.2 11 4 10 10 1.1 10 1.5 2.0 4.8 4.9 Max. 400 400 8.6 8.7 1.5 2.0 100 2 2.8 Unit A V V nA V V V pA pA V pA
Table 10.
Symbol
Dynamic electrical characteristics VCC = +12 V, Tamb = +25 C, Reset to VCC (unless otherwise specified)
Parameter Timing accuracy (monostable) (1) R = 10 k C = 0.1 F, VCC = +12 V , Timing shift with supply voltage variations (monostable) (1) R = 10 k C = 0.1 F, VCC = +5 V 1 V , Timing shift with temperature Tmin. Tamb Tmax., VCC = +5 V Min. Typ. Max. Unit
4
%
0.38
%/V
75 2.7
ppm/C MHz
f max
Maximum astable frequency RA = 470 RB = 200 C = 200 pF, VCC = +5 V , , Astable frequency accuracy RA = RB = 1 k to 100 k C = 0.1 F, , VCC = +12 V Timing shift with supply voltage variations (astable mode) , RA = RB = 1 k to 100 k C = 0.1 F, VCC = 5 to +12 V
(2)
3
%
0.1
%/V
1. See Figure 4. 2. See Figure 6.
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TS555 Figure 3.
Electrical characteristics Supply current (per timer) versus supply voltage
300
SUPPL Y CURRENT, ICC (A)
200
100
0
4
8
12
16
SUPPLY VOLTAGE, V CC (V)
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Application information
TS555
4
4.1
Application information
Monostable operation
In monostable mode, the timer operates like a one-shot generator. The external capacitor is initially held discharged by a transistor inside the timer, as shown in Figure 4. Figure 4. Application schematic
VC C Reset R 4 Trigger 2 8 7
TS555
Out 3 1
6
C
5 Control Voltage 0.01F
The circuit triggers on a negative-going input signal when the level reaches 1/3 VCC. Once triggered, the circuit remains in this state until the set time has elapsed, even if it is triggered again during this interval. The duration of the output HIGH state is given by t = 1.1 R x C. Since the charge rate and threshold level of the comparator are both directly proportional to the supply voltage, the timing interval is independent of the supply. Applying a negative pulse simultaneously to the Reset terminal (pin 4) and the Trigger terminal (pin 2) during the timing cycle discharges the external capacitor and causes the cycle to start over. The timing cycle then starts on the positive edge of the reset pulse. While the reset pulse is applied, the output is driven to the LOW state. When a negative trigger pulse is applied to pin 2, the flip-flop is set, releasing the short circuit across the external capacitor and driving the output HIGH. The voltage across the capacitor increases exponentially with the time constant = R x C. When the voltage across the capacitor equals 2/3 VCC, the comparator resets the flip-flop which then discharges the capacitor rapidly and drives the output to its LOW state. Figure 5 shows the actual waveforms generated in this mode of operation. When Reset is not used, it should be tied high to avoid any false triggering. Figure 5. Timing diagram
t = 0.1 ms / div INPUT = 2.0V/div
OUTPUT VOLTAGE = 5.0V/div
CAPACITOR VOLTAGE = 2.0V/div R = 9.1k , C = 0.01 F , RL = 1.0k
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TS555
Application information
4.2
Astable operation
When the circuit is connected as shown in Figure 6 (pins 2 and 6 connected) it triggers itself and runs as a multi-vibrator. The external capacitor charges through RA and RB and discharges through RB only. Therefore, the duty cycle may be precisely set by the ratio of these two resistors. In the astable mode of operation, C charges and discharges between 1/3 VCC and 2/3 VCC. As in the triggered mode, the charge and discharge times, and therefore frequency, are independent of the supply voltage. Figure 6. Application schematic
VC C Reset RA 4 Out 3 8 7
TS555
Control Voltage 0.01 F 5 1 2 6
RB
C
Figure 7 shows actual waveforms generated in this mode of operation. The charge time (output HIGH) is given by: t1 = 0.693 (RA + RB) C The discharge time (output LOW) by: t2 = 0.693 x RB x C Thus the total period T is given by: T = t1 + t2 = 0.693 (RA + 2RB) C The frequency of oscillation is then:
1 1.44 f = -- = ------------------------------------T (RA + 2RB )C
The duty cycle is given by:
RB D = --------------------------RA + 2RB
Figure 7.
Timing diagram
t = 0.5 ms / div OUTPUT VOLTAGE = 5.0V/div
CAPACITOR VOLTAGE = 1.0V/div R = R = 4.8 k , C = 0.1 F , R L = 1.0k A B
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Package information
TS555
5
Package information
In order to meet environmental requirements, STMicroelectronics offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com.
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TS555
Package information
5.1
DIP8 package information
Figure 8. DIP8 package mechanical drawing
Table 11.
DIP8 package mechanical data
Dimensions
Ref. Min. A A1 A2 b b2 c D E E1 e eA eB L 2.92 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10
Millimeters Typ. Max. 5.33 0.015 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 10.92 3.30 3.81 0.115 4.95 0.56 1.78 0.36 10.16 8.26 7.11 0.115 0.014 0.045 0.008 0.355 0.300 0.240 Min.
Inches Typ. Max. 0.210
0.130 0.018 0.060 0.010 0.365 0.310 0.250 0.100 0.300
0.195 0.022 0.070 0.014 0.400 0.325 0.280
0.430 0.130 0.150
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Package information
TS555
5.2
SO-8 package information
Figure 9. SO-8 package mechanical drawing
Table 12.
SO-8 package mechanical data
Dimensions
Ref. Min. A A1 A2 b c D E E1 e h L L1 k ccc 1 0.25 0.40 0.10 1.25 0.28 0.17 4.80 5.80 3.80
Millimeters Typ. Max. 1.75 0.25 0.004 0.049 0.48 0.23 4.90 6.00 3.90 1.27 0.50 1.27 1.04 8 0.10 1 0.010 0.016 5.00 6.20 4.00 0.011 0.007 0.189 0.228 0.150 Min.
Inches Typ. Max. 0.069 0.010
0.019 0.010 0.193 0.236 0.154 0.050 0.020 0.050 0.040 8 0.004 0.197 0.244 0.157
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TS555
Package information
5.3
TSSOP8 package information
Figure 10. TSSOP8 package mechanical drawing
Table 13.
TSSOP8 package mechanical data
Dimensions
Ref. Min. A A1 A2 b c D E E1 e k L L1 aaa 0 0.45 0.05 0.80 0.19 0.09 2.90 6.20 4.30
Millimeters Typ. Max. 1.2 0.15 1.00 1.05 0.30 0.20 3.00 6.40 4.40 0.65 8 0.60 1 0.1 0.75 0 0.018 3.10 6.60 4.50 0.002 0.031 0.007 0.004 0.114 0.244 0.169 Min.
Inches Typ. Max. 0.047 0.006 0.039 0.041 0.012 0.008 0.118 0.252 0.173 0.0256 8 0.024 0.039 0.004 0.030 0.122 0.260 0.177
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Ordering information
TS555
6
Ordering information
Table 14. Order codes
Temperature range Package DIP8 0C, +70C SO-8 TSSOP8 DIP8 -40C, +125C SO-8 TSSOP8 DIP8 -55C, +125C SO-8 TSSOP8 Packaging Tube Tube or Tape & reel Tape & reel Tube Tube or Tape & reel Tape & reel Tube Tube or Tape & reel Tape & reel Marking TS555CN 555C 555C TS555IN 555I 555I TS555CM 555M 555M
Order code TS555CN TS555CD TS555CDT TS555CPT TS555IN TS555ID TS555IDT TS555IPT TS555MN TS555MD TS555MDT TS555MPT
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TS555
Revision history
7
Revision history
Table 15.
Date 01-Feb-2003
Document revision history
Revision 1 Initial release. Document reformatted. Added output current, ESD and thermal resistance values in Table 1: Absolute maximum ratings. Added output current values in Table 2: Operating conditions. Changes
03-Nov-2008
2
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TS555
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