APPLICATION NOTE
BENCHMARK ST72 vs. PIC16
by Microcontroller Division Application Team
ABSTRACT
This document presents the results of a competitive analysis between the STMicroelectonics ST72 254 and the Microchip PIC16F876. These two microcontrollers (MCUs) have been chosen for comparison because they are in a similar performance category and were introduced on the market at the same time. The comparison of the two MCUs is divided into two major parts. First the cores, with a comparison of their architecture including performance benchmarks. These benchmarks are based on assembler and C routines that are representative of typical microcontroller applications. The second part examines the peripherals in terms of their functionality and to what extent they off-load the core and the driver software. Finally, you will find a table summarizing the weak and the strong points of each MCU.
Two files are appended to this document, you can find them in our Web server (mcu.st.com) in the application note section. The first one entitled "Performance comparison between ST72 254 and PIC16F876" includes the results given in this document plus the description of the source and the compilation options used. This file was created in order to allow you to easily reproduce the benchmark. The second file regroups all the source files used.
The information on the PIC16F876 is based on the Microchip datasheet: DS30292A.PDF
AN1150/0799
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Table of Contents
1 DEVICE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 R AM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 R OM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5 VOLTAGE RANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.6 S T A C K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 R EGIST E R S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.8 ADDRESSING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.10 INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.11 POW ER SAVING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.12 POW ER CONSUMPTION DATA (TAKEN FROM THE DATASHEET) . 12 3 CORE PERFORMANCE COMPARISON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 ASSEMBLER TEST ROUTINES OVERVIEW . . . . . . . . . . . . . . . . . . . . 3.2 ASSEMBLER TEST RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 RESULTS ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 C TEST ROUTINES OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 C TEST RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 C LOC K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 WDT: WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 LVD: LOW VOLTAGE DETECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 ADC: ANALOG TO DIGITAL CONVERTER . . . . . . . . . . . . . . . . . . . . . . 4.7 SPI SERIAL COMMUNICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 I²C SERIAL COMMUNICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 USART/SCI SERIAL COMMUNICATION (PIC16F87X ONLY) . . . . . . . 4.10 ISP: IN SITU PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 IN CIRCUIT DEBUGGING (PIC16F87X ONLY) . . . . . . . . . . . . . . . . . . . 4.12 RESET PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 PAC KA GE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15 16 17 18 19 20 20 21 21 26 27 28 29 31 33 34 35 35 35
5 DEVICE SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 WEAK / STRONG POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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2
BENCHMARK ST72 vs. PIC16
1 DEVICE DESCRIPTION
Table 1. Microchip
P I C16C62B Program memory RAM S t ack CPU Frequency Oscillator Power saving Operating Range P ackag e I/O port 2K *14 128* 8 PIC16C72A 2 K *1 4 128 *8 PIC16F873 4K*14 (Flash) 192 *8 128*8 EEPROM PIC16F876 8K*14 (Flash) 368* 8 128*8 EEPROM
8*13-bit, can store up to 8 addresses Up to 5MHz (with 20MHz oscillator) RC / Ceramic / Crystal One mode (Sleep Mode) 0C to +70C or -40C to +85C (optional -40C to +125C on 16C62B or 16C72A but not on 16F87x) SO28/PDIP28 (windowed version available for 16C62B or 16C72A) 22 pins with individual direction control. Output are push-pull (except 1 true opendrain pin). 8 pins may have internal pull-up (globally selected). Current up to 25mA. On-chip RC and a 8-bit prescaler (the prescaler is shared with TIMER0). The timeout period may vary between 7ms and 4.2s. But due to the internal RC variations, the time-out period is between 896ms and 4.2s for the same settings. 8-bit timer/counter with 8-bit prescaler (shared with WDT) 16-bit timer/counter with prescaler, internal/external clock and possible dedicated oscillator. 8-bit timer with 8-bit period register, prescaler and postscaler (this timer does not support external clock despite what is described in the Microchip datasheet)
Watchdog
Timer
S e ri a l communication ADC LVD RESET ISP
SPI, I²C No
SPI, I²C 8-bit with 5 inputs
SPI/I²C,SCI 10-bit with 5 inputs
Selectable, one level (known as BOR in the Microchip documentation) WDT, POR, LVD, External. During internal reset (WDT, LVD or POR) the reset state is not externally visible) MCLR,Clk,Data (need 12V on MCLR) Two modes: The old one, and a new +5V only mode (it needs one more pin)
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BENCHMARK ST72 vs. PIC16
Table 2. STMicroelectronics
ST72104G1 ST72104G2 ST72216G1 ST72215G2 ST72254G1 ST72254G2 Program memory 4K*8 (flash) 8K*8 (flash) 4K*8 (flash) 8K*8 (flash) RAM S t ack Oscillator Power saving CPU Frequency Operating Range P ackag e I/O port Watchdog 25 6*8 12 8*8 2 56*8 1 28*8 2 56*8 1 28*8 256*8 128*8 4K*8 (flash) 256*8 128*8 8K*8 (flash) 256*8 128*8
RC / Ceramic / Crystal / internal / Clock security system (clk filter, safe oscillator, limitation detection) Four power saving modes Up to 8MHz (with 16MHz oscillator) -40C to +85C (optional -40C to +125C) SO28/SDIP32 22 pins with individual direction control and individual mode control (push-pull, open-drain, input with or without pull up). Open drain mode is limited to logic level except for PA4 and PA6, which are true open drain pins. 64 values selectable for time-out from 1.5ms to 98ms @ Fcpu=8MHz One 16-bit timer/counter One 16-bit timer/counter with 2 IC, 2 OC, 1 PWM with 2 IC, 2 OC, 1 PWM One 16-bit timer with 2 IC, 2 OC, 1 PWM
Timer
S e ri a l communication ADC LVD RESET ISP No
SPI No
SPI
SPI, I²C 8-bit with 6 inputs
SPI, I²C
3 selectable levels W DT, POR, LVD, External. During internal reset (WDT, LVD or POR), the reset state is externally visible (reset pin in low state). Internal pull-up. Reset, ISPSEL, IPSCLK, IPSDATA
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BENCHMARK ST72 vs. PIC16
2 CORE
2.1 ARCHITECTURE · PIC16 The PIC16 family is based on a Harvard architecture (i.e.: data and program memory spaces are separated). These processors have a RISC core (Reduced Instruction Set Computer) with only 35 instructions. All these instructions have the same size: 14 bits (for the PIC16 family). They are executed in one CPU cycle except branches which need two cycles. The processor uses an accumulator called W (Working register). De spite its Harvard architecture, the PIC16F87x program memory is readable and writable by the MCU during program execution. But the access method is not simple. This means, it is not efficient to store data tables directly in program memory. · ST72 The ST72 family is based on a Von Neuman architecture (i.e.: data and program share the sa me memory space). These processors have a CISC core (Complex Instruction Set Computer) with 63 instructions. These instructions are from 2 to 4 bytes long. The processor uses an accumulator called A. Read access throughout the entire memory space is very easy. In consequence, the program memory can be efficiently used to store constant tables. 2.2 RAM Table 3. RAM
S T 7xxG1 - 2 PIC16C62/72A P I C16F 873 P I C16F 876 256*8 with no bank switching 128*8 accessible through 2 banks of 128 bytes (the banks contain 96 bytes of user data and the hardware registers) 192*8 accessible through 2 banks of 128 bytes (the banks contain 96 bytes of user data and the hardware registers) 368*8 accessible through 4 banks of 128 bytes (the banks contain 96 bytes of user data and the hardware registers)
On the ST72, the first 128 bytes of the RAM array is call the zero page (addresses from $80 to $FF). The data in this zone can be accessed in short addressing mode (8-bit addresses) reducin g the opcode size and speeding-up the access. This is not a bank system, because it is possible (but slower) to access the entire RAM array using the long addressing mode (16-bit addresses).
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BENCHMARK ST72 vs. PIC16
2.3 ROM Table 4. ROM
ST72254G1 ST72254G2 PIC 16C62/72A 4 K*8 (-> up to 2048 instructions) FLASH which can store either programs or data 8 K*8 (-> up to 4096 instructions) FLASH which can store either programs or data 2K*14 (->really 2048 instructions) OTP or EPROM (UV erasable) 8K*14 (->really 8092 instructions) FLASH for program storage 256*8 EEPROM for data storage. This EEPROM is accessible only through an indexed mode (9 instructions are needed to read one EEPROM Byte)
PIC 16F87x
· Program memory access Th e PIC16F87x allows the program to read or write program memory during normal execution. 14 opcodes are needed to read one word (14-bit) and 23 opcodes to write one word. The MCU is halted during a write (10ms) and after it restarts with the next instruction. In the ST72, read access to the program memory is very easy, but there is no write access allowed during execution.
· Conclusion The two program memory organisations are quite different. A PIC16 with 8K*14 of memory cou ld be compared to a ST72 with 16K*8 (which does not exist in 28 pins). But due to the RISC instruction set of the PIC16, more assembly instructions are needed to code the same program in the ST72.
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BENCHMARK ST72 vs. PIC16
2.4 FREQUENCY Table 5. Frequency
PIC16C62 / PIC16F87x Foscilator max FCPU max FINSTRUCTION max 20M hz 5MH z (Fosc/4) 5MH z (Instructions are 1 or 2 cycles long) 16M hz 8MHz (Fosc/2) 4MHz (quickest instructions are two cycles long) S T 72254
2.5 VOLTAGE RANGE PIC 16C 62/72A PIC 16LC 62/72A PIC16F87x PIC16LF87x ST72 254 4.5 V - 5.5 V
20 Fosc (MHz)
2.5 V - 5.5 V 4.5 V - 5.5 V 2.0 V - 5.5 V 3.0 V - 5.5 V
16 12 8 4 0 1,5 2
ST7
2,5
3
3,5
4
4,5
5
5,5
Voltage (V)
20 Fosc (MHz) 16 12 8 4 0 1,5 2
Fosc (MHz)
PIC16LCx-04 PIC16xCx-04 PIC16 Cx-20 PIC16xC -XX
20 16 12 8 4 0
PIC16LFx-04 PIC16xFx-04 PIC16 Fx-20 PIC16xF -XX
2,5
3
3,5
4
4,5
5
5,5
1,5
2
2,5
3
3,5
4
4,5
5
5,5
Voltage (V)
Voltage (V)
· Conclusion The PIC16F87x has a wider voltage range. It can work at 2.0 V Bu t to take advantage of this voltage range, the operating frequency must be lowered to 4MHz. Moreover, two different MCUs are needed to cover the entire voltage range. For example: at 3.5V, the ST72254 can work at full speed (16MHz) and the PIC can run only at 4MHz.
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BENCHMARK ST72 vs. PIC16
2.6 STACK · PIC16 The stack is only 8 levels deep (it is like a 16 bytes deep stack) and is separated from the user RA M. The stack cannot be accessed by software (no PUSH or POP!). · ST72 The stack is up to 128 bytes deep, it can store 64 addresses. It shares the user RAM. The stack can be easily accessed by software (PUSH/POP instructions, Stack Pointer is R/W) 2.7 REGISTERS Table 6. Registers
PIC16 Accumulator Program counter Stack Pointer Index Register W (8-bit) 13-bit (memory is organised in words of 14bit) not accessible FSR (8-bit) needs bank switching A (8-bit) 16-bit (memory is organised in bytes) 7-bit Two Index Register X,Y: 8-bit ST72
2.7.1 CODE CONDITION REGISTER vs. STATUS REGISTER The two registers are nearly the same but the ST72 has a negative bit to indicate if the result of the last operation is negative or not. 2.8 ADDRESSING MODE The PIC16 offers only 3 addressing modes (Immediate, Relative, Indexed). The RAM is organised in banks of 96 bytes. This means that bank switching is needed to access the entire RAM. The architecture of the PIC does not allow programs to directly address FLASH or EEPR O M . The ST72 is really more powerful. It has 11 different addressing modes. And it never needs b a n k switching. And, last but not least, it allows programs to access RAM or FLASH (for reading) in exactly the same way.
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BENCHMARK ST72 vs. PIC16
2.8.1 Indexed mode Th e PIC16 has one index register (FSR), but it works like a data memory location. This means that it is not possible to work directly with this register. The only operations which can be done without using the accumulator are: incrementation, decrementation and comparison with zero. Consequently, table manipulations are quite hard to handle. The ST72 has two index registers. The following operations on this register can be done dire ctly (without using the accumulator): incrementation, decrementation, comparison with a value and loading a value (literal or stored in a register). 2.9 INSTRUCTION SET Due to its RISC architecture the PIC16's instruction set is very small, only 35 instructions. Bu t these instructions are executed quickly (all need only one CPU cycle except branches which need two cycles). The internal clock is divided by 4. In consequence, compared to the ST72 (where the clock is divided by 2) the instructions are like 2 or 4 cycle instructions of the ST72.
Th e ST72 has a CISC architecture with 63 instructions (nearly twice as many as the PIC). These instructions are one to four bytes long and need between 2 to 12 CPU cycles.
Th e ST72 has a multiplication instruction 8-bit*8-bit, result on 16-bits. This multiplication needs only 11 CPU cycles. To do the same with PIC architecture, you need at least 37 CPU cycles and 35*14 bits of program memory (or 71 CPU cycles and 16*14 bits of memory).
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BENCHMARK ST72 vs. PIC16
2.10 INTERRUPT Table 7. Interrupt sources/vectors
PIC16C62B IT Sources IT Vectors Register saved 7 1 No 8 1 No PIC16C72A 1 No PIC16F87x 13 19 7 PC, X, A and CC ST72254
Table 8. Interrupt reaction time
PIC16 Min TINSTRUCTION * TJUMP TCONTEXT SAVING TOTAL (TCPU) Interrupt reaction time 1 2 4 7 1.4 s M ax 2 2 10 14 2.8 s M in 2 10 10 1.25 s ST72 Max 12 10 22 2.75 s
Included in the jump
*TINSTRUCTION is the number of fCPU cycles needed to complete the current instruction
· PIC16 During an interrupt, only the return address is automatically saved onto the stack. Saving the con te xt needs to be done manually (10 instructions needed) and the interrupt sub-routine must also restore the context (6 instructions needed). · ST72 The ST72 has 7 different interrupt vectors, it allows you to easily create independent interrupt subroutines. Context saving is done automatically. The only weak point of the interrupt mechanism of the ST72 is that the interrupt priority is fixed by hardware. But some ST72s have a Nested Interrupt feature (ex: ST72311R6) · Conclusion The interrupt response times are very much the same. But for marketing reasons, Microchip does not take the time needed to save the context into account. This is why Microchip announces better response times. Moreover, the PIC architecture provides only one interrupt vector. So, the interrupt sub-routine has to read all the interrupt flags in order to find which interrupt needs to be serviced.This means a significant software overhead when many interrupt sources are used.
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BENCHMARK ST72 vs. PIC16
2.11 POWER SAVING MODE · PIC16 The PIC16 has only one power saving mode: the sleep mode. In this mode the oscillator is shut off. Any of the following events can cause a wake-up from sleep mode:
s External
reset Timer (in sleep mode a Watchdog time-out does not reset the MCU) (if the individual interrupt enable bit is set) mode interrupt
s Watchdog s Interrupt s TMR1
interrupt (if the TIMER1 clock is an external clock or if it is it's own oscillator) event trigger (cf. A/D and TIMER1) in slave mode (if available) write complete
s Capture s Special s SPI
or I²C in slave mode conversion if A/D clk is RC
s USART s A/D
s EEPROM
The MCU needs 1024 T osc (256 CPU cycles) to wake-up (except in RC mode where the wakeup is immediate) · ST72 The ST72 has three different power saving modes:
s Slow
mode, which allows the internal clock of the device to be reduced (4 different speeds available) mode, which turns off the CPU but keeps the clock active for the peripherals. It can be exited by any peripheral interrupt (ex: timer, SPI...). Wake-up from this mode is immediate. mode, which turns off the CPU and the clock system. It can be exited by external interrupt. The CPU needs 4096 CPU cycles (8092 Tosc) to wake-up in order to stabilise the oscillator.
s Wait
s Halt
· Conclusion W ith its three power saving modes, the ST72 is quite flexible. It is possible to adjust the powe r consumption to the exact needs of the application. However, in situations when the PIC16 sleep mode can be used, it might be more efficient. This is because serial communication is still possible in slave mode. In terms of current consumptio n, the PIC16's sleep mode is not unlike the ST72's halt mode. Mo re o ve r, the PIC16's wake-up is faster: 1024 oscillator cycles compared to 8092 for the ST72 , and with an RC oscillator the PIC16 is woken-up immediately but the ST72 is not.
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BENCHMARK ST72 vs. PIC16
2.12 POWER CONSUMPTION DATA (TAKEN FROM THE DATASHEET) Table 9. PIC16 power consumption data (Low power device)
PIC16LF87x, PIC16LC62B/72A low consumption devices PIC16LF87x T yp Max PIC16LC62B/72A T yp M ax
Run mode OCS1=external square wave from rail to rail. All I/O tristated, pulled to VDD. /MCLR pulled to VDD. VDD=3.0V XT mode, RC oscillator 4MHz (Fcpu=1MHz)* LP mode, Fosc=32KHz (Fcpu=9KHz) WDT disabled W DT enabled, -40C to +85C W DT disabled, -40C to +85C W DT disabled, 0C to +70C TIMER1 oscillator add approx 20uA (Vdd=5V) *In RC mode the current through R is not included. 2mA 20uA 7. 5uA 0. 9uA 0. 9uA 3. 8m A 48uA 30uA 5uA 5uA 2m A 22. 5uA 7.5uA 0.9uA 0.9uA 3. 8m A 48uA 30uA 5u A 5u A
Power down current (sleep mode), all I/O in high impedance and tied to VDD or VSS. VDD=3.0V
LVD add typ 85uA max 200uA of consumption (characterized but not tested) (Vdd=5V)
Table 10. PIC16 power consumption data (standard device)
PIC16F87, PIC16C62B/72A PIC16F87x T yp Max PIC16C 62B/72A T yp M ax
Run mode OCS1=external square wave from rail to rail. All I/O tristated, pulled to VDD. /MCLR pulled to VDD. VDD=5.5V XT mode, RC oscillator 4MHz (Fcpu=1MHz)* HS mode, Fosc=20MHz (Fcpu=5Mhz) W DT enabled, -40C to +85C W DT disabled, -40C to +85C W DT disabled, 0C to +70C W DT disabled, -40C to +125C TIMER1 oscillator add approx 20uA *In RC mode the current through R is not included. 2mA 10m A 10.5uA 1. 5uA 1. 5uA 2. 5uA 5mA 20m A 42uA 19uA 16uA 19uA 2. 7m A 10m A 10. 5uA 1.5uA 1.5uA 2.5uA 5mA 20m A 42uA 19uA 16uA 19uA
Power down current (sleep mode), all I/O in high impedance and tied to VDD or VSS. VDD=4.0V
LVD add typ 85uA max 200uA of consumption (characterized but not tested)
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BENCHMARK ST72 vs. PIC16
Table 11. ST72254 power consumption data
ST72254 T yp M ax
Run mode OCS1=external square wave. All I/Os in input mode with a static value VDD or VSS. CPU running with memory access. Fosc=16MHz (Fcpu=8Mhz) VDD=5V Fosc= 8MHz (Fcpu=4Mhz) VDD=5V Slow mode. All I/Os in input mode with a static VDD or V SS value Fosc=16MHz (Fcpu=500Khz) VDD=5V Fosc= 8MHz (Fcpu=250Khz) VDD=5V Wait mode. All I/Os in input mode with a static VDD or VSS value (values are characterized but not tested) Fosc=16MHz (Fcpu=8Mhz) VDD=5V Fosc= 8MHz (Fcpu=4Mhz) VDD=5V Slow Wait mode. All I/Os in input mode with a static VDD or VSS value Fosc=16MHz (Fcpu=500Khz) VDD=5V Fosc= 8MHz (Fcpu=250Khz) VDD=5 V 0. 4m A 0. 2m A 0. 5uA 0.8mA 0.4mA 5 uA 2mA 1mA 4mA 2mA 0. 7m A 0. 5m A 1.4mA 1mA 5.5mA 3mA 10mA 6mA
Halt mode. All I/Os in input mode with a static VDD or VSS value. LVD disabled
· Conclusion In run mode, the ST72254 draws less power than the PIC16F876. 5.5mA versus 10mA and with the maximum values the difference is even bigger 10mA vs. 20mA. For the power saving modes, the conclusion is hard to establish because the modes available are quite different.
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BENCHMARK ST72 vs. PIC16
3 CORE PERFORMANCE COMPARISON
STMicroelectronics has developed two sets of test routines related to 8-bit and low-end 16-bit microcon troller applications to evaluate the computing performance of microcontroller core s. These routines have been implemented on ST72254 and PIC16F876 Microcontroller Units. - The first set of routines has been written in assembler language to optimize their implementation and focus on core performance, without being dependent upon compiler code transformation. - The second set tries to evaluate the performance of the two MCUs and their respective C compilers. This benchmark uses a C language program, representative of an automotive application. The C compilers used were from Hiware on the ST72 and from Hi-Tech on the PIC16.
The speed of the two MCUs has been compared in two ways: - Firstly, at the maximum frequency commercially available on each MCU. this means at an external frequency of 16MHz on the ST72 and of 20MHz on the PIC16. - Secondly, at the same current consumption level (10mA).
Table 12. Current Consumption data (taken from datasheets) ST 72254 PIC16C72A PIC16C72A F ext 16MHz 20MHz 1 0 M H z* F CPU 8M H z 5M H z 2 .5 M H z Consumption (Max) 10 mA 20 mA 10 mA Ru n mode Ru n mode Ru n mode
* this value is determined by interpolation
As you can see, to reach the same power consumption level on the two MCUs, the PIC's runnin g frequency must be lowered to 10Mhz (ext.) and the ST72 can keep its maximum frequency of 16MHz (ext.).
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BENCHMARK ST72 vs. PIC16
3.1 ASSEMBLER TEST ROUTINES OVERVIEW The set of test routines is made of 8 assembly programs which cover all the typical needs of an MCU application. This routine tests only the core performance and does not include any peripheral management. Table 13. Assembler test routine overview
Abbreviated name Full name String search Character search Bubble sort Block move Block translation 16-bit value right shift Bit manipulation 32-bit by 16-bit division 16-bit integer multiplication Description Features stressed
string char bubble blkmov convert shright bitsrt 32div 16m u l
search a 16-byte string in a 128- 8-bit data block manipulation character array in ROM string manipulation search a byte in a 40-byte array 8-bit data manipulation in ROM char manipulation sort of a one-dimension array of 16-bit data manipulation 10 16-bit integers integer manipulation move a 64-byte block from a 8-bit data block manipulation place in RAM to another block move translate a 80-byte block in a 8-bit data manipulation different format use of a lookup table shift a 16-bit value five places to 16-bit data manipulation the right bit manipulation set, reset, and test of 3 bits in a bit computation 128-bit array bit and 8-bit data manipulation Unsigned division of a 32-bit bit manipulation dividend by a 16-bit divisor 16-bit substraction multiplication of two unsigned 16-bit data computation words giving a 32-bit result integer manipulation
· Notes on memory accesses used in the test routines: The size of the arrays manipulated by the test routines has been chosen in order to minimize RAM bank switching on the PIC16 processor. This means that the results do not include any overhead for memory bank switching on the PIC16 MCU. But with the complexityle vels of real-world applications, the paginated memory can be a major source of time and code overhead. Fo r the same reason on the ST72 the data are placed in the zero page, allowing to use the short addressing mode.
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BENCHMARK ST72 vs. PIC16
3.2 ASSEMBLER TEST RESULTS Table 14. Execution Speed
At Maximum Frequency PIC16
@20MHz
At a Current of 10mA P I C 16
@10MHz
ST72
@16MHz
Speed Ratio
ST 72/PIC16*
ST72
@16MHz
Speed Ratio
ST72/PIC16*
Description
search a 16-byte string in a 128-character array in ROM search a byte in a 40-byte array in ROM sort of a one-dimensional array of 10 16-bit integers move a 64-byte block from one place in RAM to another translate a 80-byte block into a different format shift a 16-bit value five places to the right set, reset, and test of 3 bits in a 128-bit array Unsigned division of a 32-bit dividend by a 16-bit divisor multiplication of two unsigned words giving a 32-bit result Average results
string ch ar bubble blkmov convert shright bitsrt 32div 16m u l A V G.
371 s 282 s 84 s 57 s
1.32 1.49 0.88 1.28 1.06 0.65 0.58 0.56 2.29 0.98
741 s 282 s 169 s 57 s
2.63 2.98 1.76 2.55 2.13 1.29 1.17 1.12 4.58 1.95
752 s 857 s 154 s 121 s 256 s 241 s 6 s 36 s 10 s 62 s
1504 s 857 s 308 s 121 s 513 s 241 s 13 s 72 s 10 s 62 s
124 s 222 s 41 s 18 s
248 s 222 s 72 s 18 s
203 s 208 s
406 s 208 s
*The speed ratio is calculated as follows: (Time PIC16)/(Time ST72). So, a number higher than 1 means that the ST72 is faster.
- At their maximum frequency, we can see that the execution speed of the two MCUs is truly comparable. Even though, in this configuration the external frequency of the PIC16 is higher (20Mhz) than that of the ST72 (16MHz). - At the same power consumption level, the ST72254 is significantly better. In other words, for the same power consumption budget, the ST72254 is nearly 2 times more powerful than the PIC16F87x.
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BENCHMARK ST72 vs. PIC16
3.3 RESULTS ANALYSIS · Bit manipulation: The Microchip architecture is very fast for bit manipulation. Modifying one bit in a data byte can be performed in only 1 CPU cycle which means in 0.2s@20MHz. To do the same operation the ST72 needs 5 CPU cycles (0.625s@16MHz).
· Memory access: The PIC16 is faster in direct addressing mode (1 cycle 0.2s@20MHz compared to 3 cycles 0.375s@16MHz). This is very useful for many parts of the application where variables are directly used, for example in loop control. The indirect mode of the PIC16 (needed for table or string manipulation) is very slow, because its index register cannot be loaded without losing the content of the accumulator. Th e ST72 with its two index registers and its wider choice of addressing modes allows very easy (and fast) data manipulation. To summarize, when there is no need for indirect addressing, the PIC16 runs faster. But for more complex algorithms the ST72 is better (faster and easier to program). Moreover, the test routines use only a small amount memory so, there is no problem of bank switch in g. But in a real (and large-sized) application, this could be a major limitation of the PIC16 architecture.
· Use of Constant tables The PIC16 cannot read the content of its ROM directly, this means that, constant tables must be handled in a strange way. It needs a sub-routine call and a computed jump. This takes at least 6 CPU cycles (1.2s@20MHz). On the ST72, the same operation needs 6 CPU cycles (0.625s@16MHz). Moreover, due to the need for a 8-bit computed jump, reading a constant table bigger than 256 bytes needs more time and code on the Microchip architecture.
· Multiplication: Here, the comparison is easy: The ST72 has a 8-bit multiply instruction. The PIC16 does not have any. Doing multiplication entirely by software implies considerable time and code overhead.
17/40
BENCHMARK ST72 vs. PIC16
3.4 C TEST ROUTINES OVERVIEW The source program has been provided by a customer. It has 9 modules controlled by the main routine in `FILE7.C'. It uses all instructions usually found in C language programs. The source makes heavy use of unsigned char, bit and table manipulations. The modules a re described in the following table. We have tried to highlight the main features of each module. Table 15. Module description
Module file1 file2 file3 file4 file5 file6 file7 file8 file9 #lines 204 538 93 251 164 68 133 88 34 Description after evaluation of a data by a switch, manipulation of "global" data and function calls (~100) definition of functions with data manipulation, for loop, while statement, if and switch uses definitions of 6 functions manipulating arrays, one function doing intensive calculation mainly load of constant tables, and manipulation of structures at the end exactly the same file than file8.c but using switch/case statement if processing and bitwise computation the file contains the "main", initialises data and calls functions in the other files exactly the same file then file5.c signed char data computation Features stressed switch/case processing function calls loop statements arithmetic computation array manipulation bit calculation constant table manipulation structure use switch/case statement bit manipulation and if use function calls data initialisation if/else statements signed data manipulation
Note : Number of lines: 1918. 3.4.1 Modification of the source files The PIC16 data memory is organised in banks which contains up to 96 bytes of RAM. But, the Hi-Tech C compiler (PIC16) does not distribute the variables automatically into these different banks. So, to make the compilation phase work, the sources files need to be modified. Two files have been modified: `FILE2.C' and `FILE2.H'. The modifications consist of using the keywords bank1 and bank2 to place some of the variables in the different memory banks. Fo r the ST72 we have made two sets of sources. The first one called standard does not have any modifications. The second one called improved is modified to take more advantage of the use of the zero page. The only modified file is `FILE2.H' where two lines are added:
#pragma DATA_SEG SHORT ZEROPAGE #pragma DATA_SEG DEFAULT
In order to make heavily-used global variables directly accessible (in short addressing mode)
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BENCHMARK ST72 vs. PIC16
3.5 C TEST RESULTS Table 16. Results
ST72 (Standard) ROM usage RAM usage 7242 bytes 200 bytes ST72 (improved)* 6849 bytes 200 bytes Execution time CPU cycle Time at the maximum frequency Time at a 10mA current 96374 12. 04m s @ 16M hz 9 4312 11.78ms@16Mhz 6260 9 12.52ms@20Mhz P I C16* 5529 words of 14 bits 180 bytes
12. 04m s @ 16M hz
11.78ms@16Mhz
25.04ms@10Mhz
* These source files have been modified
- In terms of execution speed, the results are the same as in the assembly routine test: the execution speed of the two MCUs is truly comparable at their maximum frequenc y. And for the same power consumption budget, the ST72 is nearly 2 times more powerful than the PIC16. - In terms of program size: the reported size is between 20% and 30% higher on the ST72 than on the PIC16. But this is normal, because the memory of the PIC16 is organ ised in words of 14 bits and not in bytes (8-bit) like on the ST72.
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BENCHMARK ST72 vs. PIC16
4 PERIPHERALS
4.1 I/O PORTS Bo th PIC16 and ST72 propose I/O ports with individual direction control. Both have 22 I/O pins. · PIC16F87x
s Port
A (6 pins): analog input. TTL buffers except RA4 which has Schmitt trigger input or open drain output (true open drain but limited to 8.4 V) B (8 pins): TTL buffer, input with pull-up (globally selectable) RB0 external interrupt pin. RB4->RB7: Interrupt when a value on a pin changes (selectable globally on input pins). C: 8 pins with Schmitt trigger input buffer, TTL output
s Port
s Port
Note: The interrupt-on-change is dedicated to interfacing a 4*4 keypad. It can be used to wake-u p the CPU when a key is pressed. But if the interrupt occurs while a read is in progress on PORTB (even a bit set on a pin) the interrupt may not be taken into account. Consequently, if the interrupt-on-change feature is used, reading PORTB must be avoided.
· ST72254 For all I/O pins it is possible to individually choose between :
s floating s pull-up s push s open
input input with interrupt
pull output
drain output. The open drain outputs are limited to logic level. But there are 2 true opendrain pins.
Table 17. Output Voltage level
PIC16
Vol Voh 0.6 V / 8.5mA VDD-0.7 V / 3 mA
ST72 standard output
0.5 V / 2 mA,1.3 V / 5mA VDD-0.8 V / 2mA ,VDD-2 V / 5mA
ST72 High sink output
0.5 V / 8mA, 1.3V / 20mA VDD-0.8 V / 2mA ,VDD-2 V / 5mA
PIC16F87x: All the TTL buffers can Source/Sink high current ST72 54: has 8 outputs able to sink high current. · Conclusion The ST72 offers more flexibility in the I/O port configuration but the PIC16 outputs can sink or source bigger currents.
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BENCHMARK ST72 vs. PIC16
4.2 CLOCK Table 18. Clock characteristics
PIC16C62B/72A Min External clock Quartz/ ceramic oscillator RC oscillator E x t e rn a l R E x t e rn a l C Internal RC Safe clock oscillator Clock spikes filter 0 MHz 0.1 MHz 0 MHz 3K 20 pF No No No Max 20 MHz 20 MHz 4 MHz 100 K 3K 20 pF No No No 100 K PIC16F87x M in 0 MHz M ax 20 MHz 20 MHz 0 1 MHz 1 MHz 22 K 0 250 kHz ST72254 M in M ax 16 MHz 16 Mhz 14 Mhz 47 K 470 pF 430 kHz
Typ: 4 Mhz Yes with detection
Th e ST72 has a useful clock module. It ensures that the MCU will always run, even if the crystal has a problem. This security system can be a welcome feature for a lot of applications.The ST72 proposes also an internal RC oscillator which allows to reduce the need for external components to the minimum. 4.3 TIMER Table 19. Timer summary
P I C16F 87 S T 72254
2 timers 8-bit 1 timer 16-bit 2 PWM (same frequency) or 2 IC (same time base) or 2 OC (same time base) or 1 PWM and 1 IC 2 timers 16-bit 2 PWM and 2 IC or 1 PWM and 2 OC and 3 IC or 2 One Pulse Mode and 2 IC and 2 OC or 4 IC and 4 OC
N o simple way to access the 16-bit s e c u rit y system (latches the LSB after reading timer the MSB) (12 instructions to read the timer)
21/40
BENCHMARK ST72 vs. PIC16
Table 20. PWM
PIC (Fosc=20MHz) Maximum Resolution Possible frequencies at full resolution Maximum frequency at full resolution Maximum frequency at 10-bit resolution Resolution available at 1 kHz Resolution available at 20kHz 10-bit 3 19. 53K Hz 19. 53K Hz 102 4 100 0 ST7 (Fosc=16MHz) 16-bit 3 61 Hz 3.9KHz 8000 200
· PIC It has 3 different timers but with some restrictions.
s TIMER0
(8-bit) share its prescaler with the Watchdog. The prescaler allows to choose between 8 different timer frequencies. Internal or External clock (if the prescaler is used to increase the Watchdog time-out there is no possibility to choose the TIMER0 frequency.) (16-bit) has four prescaler values. Internal or External clock (in asynchronous mode or in synchronous mode). Dedicated oscillator (up to 200KHz). (8-bit) has three prescaler values. Period register, in fact it is a compare register and when a match is detected, the timer is cleared.
s TIMER1
s TIMER2
CCP module: It is a register which can be configured as an input capture register or as an output compare register or as a PWM duty cycle register (it is an exclusive or!). It is possible to automatically clear the timer when there is an output compare match (this possibility is referenced in the Microchip documentation as Special-event Trigger).
s The
PIC16C62B has one CCP module so it is possible to do either one IC or one OC or one P WM .
s The
PIC16C72A also seems to have only one CCP module but there are some mistakes in the Microchip documentation. PIC16F87x has two CCP modules so it is possible to do two PWMs or two ICs or OCs or to do a mix. The Special event Trigger of the second CCP module can clear TIMER1 and start an A/D conversion.
s The
22/40
BENCHMARK ST72 vs. PIC16
The two CCP modules share the same timer resources, and there are also some major restrictions due to the interaction between the two modules. Table 21. CCP module interaction (PIC16F87x)
CC Px mode CCPy mode Restriction
C aptur e Capture C om par e PW M PWM PWM
C aptur e Compare C om par e P WM C aptur e C om par e
Same time base Same time base (The special event Trigger clears the timer) Same time base (The special event Trigger clears the timer) Same frequency! and same update rate no problem no problem
The PIC16 does not provide any security system for ensuring the integrity of reading or writing the 16-bit timer, which needs two 8-bit accesses. To secure the access to the CCP register (IC, OC or PWM), Microchip proposes to first shut off the function of the CCP register then to do the access and finally to re-enable the CCP module.
To directly read or write the 16-bit timer, Microchip proposes the following sequence of code Table 22. Example of code for accessing the 16-bit timer
Example 12-3: Writing a 16-bit Free Running Timer ; All interrupts are disabled CLRF TMR1L ; Clear Low byte, Ensures no ; rollover into TMR1H MOVLW HI_BYTE ; Value to load into TMR1H MOVWF TMR1H, F ; Write High byte MOVLW LO_BYTE ; Value to load into TMR1L MOVWF TMR1H, F ; Write Low byte ; Re-enable the Interrupt (if required) CONTINUE ; Continue with your code
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BENCHMARK ST72 vs. PIC16
Table 23. Example of code for accessing the 16-bit timer
Example 12-4: Reading a 16-bit Free Running Timer ; All interrupts are disabled MOVF TMR1H, W ; Read high byte MOVWF TMPH ; MOVF TMR1L, W ; Read low byte MOVWF TMPL ; MOVF TMR1H, W ; Read high byte SUBWF TMPH, W ; Sub 1st read with 2 nd read BTFSC STATUS,Z ; Is result = 0 GOTO CONTINUE ; Good 16-bit read ; ; TMR1L may have rolled over between the read of the high and low bytes. ; Reading the high and low bytes now will read a good value. ; MOVF TMR1H, W ; Read high byte MOVWF TMPH ; MOVF TMR1L, W ; Read low byte MOVWF TMPL ; ; Re-enable the Interrupt (if required) CONTINUE ; Continue with your code
This program is taken from a Microchip application note. Finally, reading the timer requires between 9 and 12 CPU cycles and 12 14-bit words of program memory
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BENCHMARK ST72 vs. PIC16
· ST72 The ST72 has one or two 16-bit timers. The first timer (non-optional) can work with an external clock but the second one (optional) ca n n o t . The two timers are really independent. The timer value cannot be set directly (just a clear is possible). Each timer has
sA s2 s2 s1 s1 s4
prescaler which provides 3 different time bases input capture functions output compare functions PWM (use the 2 OCs) One pulse mode (use 1 IC and 1 OC)
alternate functions on the I/O ports (IC1,IC2,OC1,OC2). The first timer may also use an external clock pin
On the ST72 with 2 16-bit timers, there are 4 ICs, 4 OCs, 2 PWMs (really independent) and 2 One-pulse modes. The ST72 offers a simple security system for accessing the 16-bit register (Timer, IC or OC): The access to the MSB part disables the function or latches the LSB value until the access to the LSB part is performed. · Conclusion The PIC16 offers a better PWM for frequencies over 3.9KHz. At frequencies below this limit, the precision of the ST72 PWM is better. Moreover, the ST72 offers two really independent PWMs while the PIC16 PWMs are linked and must run at the same frequency.
Microchip has three timers, this would appear to be better than on the ST72. But there are a lot of restrictions in the use of these timers. This means that with its two timers the ST72 is more powerful. In fact, it depends on the exact needs of the application. If the application can deal with the interactions between the different modules, then it can take an advantage of the three timers available on the PIC16.
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BENCHMARK ST72 vs. PIC16
4.4 WDT: WATCHDOG TIMER Table 24. Watchdog timer
PIC16
Timer source Min Time out Max Time out Possible values Refresh method Power down mode Dedicated RC oscillator Between 7-30 ms (depending of the device) Between 896ms-4.2s (depending of the device) 8 values using the TIMER0 prescaler Clear the timer The WDT can wake-up the CPU from sleep mode Internal clock 1.5ms (16MHz osc.) 98.3ms (16MHz osc.) 64 Can load any value in the timer The WDT is stopped in halt mode
S T 72
· PIC16 It uses an internal dedicated RC oscillator. It shares an 8-bit prescaler with the TIMER0 module. So when using the prescaler to increase the time-out period of the Watchdog, there is no possibility to change the TIMER0 (8-bit timer) frequency. The time-out period is between 7 and 33 ms without prescaler (the variations are due to frequency variations of the RC oscillator between each device). U s i n g the prescaler, 8 time-out values can be chosen giving a time-out period up to 7*128=896 ms or 33*128=4.2s regardless of Fcpu. In sleep mode, the Watchdog is still running. A Watchdog time-out while the MCU is in sleep mode will wake-up the MCU (and not reset it). So this feature prevents erroneously putting the CPU in sleep mode. If the CPU is put back in sleep mode, the Watchdog is automatically cleared. The WDT can only be cleared. So you cannot easily modify the time-out period during execution.
· ST72 The Watchdog timer is completely independent of the other timers. The time-out period can be chosen between 64 values. It goes from 1.5ms to 98.3 ms (with a 16Mhz oscillator) In Halt mode, the oscillator is shut off, so the Watchdog is also shut off. It restarts when the MC U is woken-up. You can choose the value you want to load into the WDT. So you can easily choose the WDT time-out for the next block of instructions. · Conclusion The Watchdog of the ST72 allows the time-out period to be defined more precisely. But, the Watchdog of the PIC16 offers a protection against erroneously entering sleep mode.
26/40
BENCHMARK ST72 vs. PIC16
4.5 LVD: LOW VOLTAGE DETECTOR Table 25. Low Voltage detector
PIC 16 M in Selectable LVD Reset release threshold M ax Typ 4.3 V (high) 3.7 V 4.3 V 3.9 V (med) 3.35 V (low) 3.85 V(high) Reset generation threshold 3.7 V 4.3 V 3.50 V (med) 3.00 V (low) Hyster eri s Done by holding in reset state for a minimum time after V DD rises again Yes (one level) ST72 Max 4.5V(high) 4.05V (med) 3.45 V (low) 4.25 V (high) 3.80 V (med) 3.20 V (low) Yes (3 levels)
250 mV
· PIC16 It offers a single level low voltage detector. The CPU is put in Reset, when the voltage goes below the low-level value for more than 100 s (min time to detect the low voltage). When VDD rise s-up again, the CPU enters power-up reset mode. The power-up Reset is active for at least 28ms. If V DD goes down again during this time then the power-up timer is cleared.
· Conclusion The LVD module of the PIC16 is limited because it can only be used in 5V operating mode. But if the application runs at 5V there is no significant difference between the two modules.
27/40
BENCHMARK ST72 vs. PIC16
4.6 ADC: ANALOG TO DIGITAL CONVERTER The A/D conversion modules of the PIC16 and of the ST72 are based on the same A/D conversion method (successive approximations). The PIC16C62B does not have any ADC cell. Table 26. ADC characteristics
P I C16C72A Resolution Channel Conversion time (under a 10K source impedance) Maximum conversion frequency Voltage reference (full scale) Total absolute error Integral linearity error Differential linearity error Full scale error Offset error 8-bit 5 20 s 50K Hz +-1 lsb +-1 lsb +-1 lsb +-1 lsb +-1 lsb 5 20 s 50KHz +-1 lsb +-1 lsb +-1 lsb +-1 lsb +-1 lsb PIC16F87 10-bit 8-bit 6 3 s 333K Hz V DD +-1 lsb +-0.5 lsb +-0.5 lsb +-0.5 lsb +-0.5 lsb ST72254
VDD or VREF (I/O pin)
Test condition: Pic : At VREF=VDD=5.12V ST7: VDD=5V worst-case temperature, negative injection VDD=VDDA=5V fcpu=8MHz F A D C =8 M H z All these values are guaranteed (maximum value). 4.6.1 Features The PIC16F87x offers the possibility to assign an I/O pin to be the high analog voltage reference. This is not available on 28-pin versions of the ST72. Th e PIC16F87x ADC can work when the MCU is in sleep mode, using the timer output co mpa re function to start the A/D conversion. The timer is automatically cleared. When the conversion is ready, the MCU is woken-up. To provide the A/D clock, there is a built-in RC oscillator (using the RC oscillator, the conversion time is 48 s for the PIC16F87). This feature provides a way to do A/D conversion at a fixed rate with a minimum software overhead. On the ST72, this mechanism doesn't exist. But, in wait mode the A/D module is still able to work, so an output compare interrupt can be set to wake-up the MCU and then it can read the last converted value, and set the OC up again to finally go back in wait. The software overhead is slightly more significant.
28/40
BENCHMARK ST72 vs. PIC16
· Conclusion The A/D module of the ST72 is really better than the module of the PIC16C72A (faster and more precise). But in comparison with the PIC16F87, the conclusion is more difficult to establish. The PIC16F87 A/D module has a better resolution and the automatic sample rate feature, but the ST72 A/D module runs significantly faster. So the advantages depend on the application.
4.7 SPI SERIAL COMMUNICATION · Common Features
s Clk
edge and polarity select on transfer complete baud rate
s Interrupt
s Selectable s MSB
first transmission buffered transmission register buffered reception register
s Single
s Double s SS
allows to select the active slave
· PIC16
s Receive s Can
overflow detection (in slave mode).
work while in sleep (slave mode only), the MCU is woken-up by the IT on transfer complete. SPI and I²C cells of the PIC share the same registers, so it is not possible to use the SPI and the I²C simultaneously.
s The
· ST72
s Write s Mode
collision detection: if a write is made to the register before the transfer is complete.
Fault detection: if the SS is pulled low while in master mode, it automatically switches from master to slave mode.
s Can
work in wait mode (master or slave mode), the MCU is woken-up by the interrupt on transfer complete. But it can't work in Halt mode.
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BENCHMARK ST72 vs. PIC16
Table 27. Baud Rate
PIC16 (Fext=20MHz) 5 MHz Master mode (see note) ST72 (Fext=16MHz) 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 4M Hz (Fcpu/2)
* *
2.5 MHz
1.25 MHz
625 kHz
312,5 kHz * 156 kHz Maximum in Slave mode PIC16C62/72A: 1.78MHz (1/(2.5Tcpu+60ns) PIC16F87x: 2.27MHz (1/(2Tcpu+40ns)
*These baud rates use the TIMER2 output as baud rate generator.
· Conclusion The two SPIs, are almost the same. The PIC16 is faster in transmission but slower in reception. And TIMER2 is needed in order to obtain some baud rates. The PIC16 does not allow the SPI and the I²C to be used simultaneously. The PIC16 provides a receive-overflow detection (reception of a new byte completed before reading of the previous). This can be very useful, and certainly more useful than the write collision detection of the ST72.
The ST72 allows a lower SPI speed, which could be useful with some slow peripherals.
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BENCHMARK ST72 vs. PIC16
4.8 I²C SERIAL COMMUNICATION Table 28. I²C characteristic
PIC16C 62B/72A Address Speed Acknowledge Interrupt Master/Slave General call support Multi-master mode Bus arbitration Write collision detection Acknowledge detection Receive overflow detection Bus error detection Power down activity
Yes Yes Yes No Yes (in slave mode only) Slave only No No
PIC 16F87
7-bit/10-bit Standard and Fast mode automatic
ST72254
End-of-Byte / Stop detection / Address match Master/Slave Yes Yes SW Yes Master/slave Yes Yes Automatic Yes Yes and automatic acknowledge failure detection No Yes Yes in wait mode but not in halt
The PIC16C62B/72A doesn't support the I²C master mode (it can be emulated by software). They also don't support general calls. 4.8.1 Common features:
s 7-bit/10-bit
addressing transmission flag (with interrupt capability) address
s End-of-byte
s Programmable s General
call support (ST7 and PIC16F87x) and fast mode support (100KHz and 400KHz) acknowledge. of transmission in progress (busy flag) generation (master mode ST7 PIC16F87x)
s Standard
s Automatic s Detection s Start/Stop s Stop
detection with IT (slave mode). on reception of a good address.
s Interrupt
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BENCHMARK ST72 vs. PIC16
· PIC16
s Multi-master s Write
support but bus arbitration must be done by software (PIC16F87x).
collision detection: when a write is done while the previous byte is been shifted (master mode PIC16F87x). detection with IT (slave mode). overflow detection (slave mode).
s Start
s Receive
s Acknowledge
reception detection. In sleep mode the MCU can be woken-up when receiving of a byte or when an address match is completed (in slave mode only).
The PIC16 does not allow the I²C and the SPI to be used simultaneously.
· ST72
s Multi-master s The s The s Bus
support with bus lost arbitration detection (ARLO)
acknowledge of a general call can be disabled acknowledge sending can be disabled (globally) Error detection: if a start or stop condition is issued during a byte transfer. failure detection: reception of something else when waiting for an acknowledge.
s Acknowledge s In
wait mode, the I²C module continues to work normally (master or slave mode) and the MCU can be woken-up by any interrupt from the I²C module.
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BENCHMARK ST72 vs. PIC16
4.9 USART/SCI SERIAL COMMUNICATION (PIC16F87X ONLY) This device is present only on the PIC16F87x. It is able to perform serial communications in the following modes:
s Asynchronous s Synchronous s Synchronous
(Full duplex)
Master (half duplex) Slave (half duplex)
s 8/9
bit reception mode error detection detection error detection
s Framing s Address s Overrun
Table 29. SCI Baud rate in asynchronous mode
Standard Baud rate
300 1200 2400 9600 19200 76800 96000 30 0 0
Fosc=20Mhz Real Baud rate
NA 1221 2404 9469 19530 78130 104200 312500 +1.73 +0.16 -1.36 +1.73 +1.73 +8.51 +4.17
Fosc=16Mhz %error Real Baud rate
NA 1202 2404 9615 19230 83330 NA NA +0.16 +0.16 +0.16 +0.16 +8.51
% e rro r
Note : The ST72254 does not have an SCI, but some ST72 devices have one (ex: ST72331J2)
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BENCHMARK ST72 vs. PIC16
4.10 ISP: IN SITU PROGRAMMING Table 30. ISP Characteristics
PIC16C62B/72A Memory
ISP Pin needed for ISP Pin used Entering programming mode Supply voltage during programming
PIC 16F87 FLASH
Yes (two modes) 4 MCLR, clock, data, VSS 5 MCLR, clock, data, VSS, PGM Sequence applied to PGM while in reset
ST72 FLASH
Yes 5 Reset, clock, data, VSS, IPSEL Sequence applied to IPSEL while in reset
EPROM (OTP / UV)
Yes 5 MCLR, clock, data, VSS, VDD
Transition from 0V to +12V on MCLR Bulk erasing works only at +5V Programming can be done at any voltage in the VDD range
+5V only (even if the board works at 3V)
+5V only (even if the board works at 3V)
Supply voltage during verify
Verify needs to be Not precised in the Midone at the VDDmin and the VDD max of the crochip documentation application Program directly loaded into the EPROM (OPT/UV)
+5V
No specific needs, programming and verifying can be done at any voltage in the VDD range
Programming method
Program directly Program directly loaded into the FLASH loaded into the FLASH
First a program is loaded in RAM, then it is executed, and it takes in charge the Flash programming 15 ms per 16*8-bit Yes
Programming Timing Code protection
10 ms per 14-bit Yes
· Conclusion : Compared to the ISP of the PIC16C62B/72A (old device), the ST72's ISP is far better because, it does not need a special voltage supply. This point is very important in case of an app l i c a t i o n at +3V where the MCU must be powered at +5V for programming. For the PIC16F87x it is possible to use the ISP at any voltage in the VDD range, but bulk erasing can only work at +5V. The ST72 ISP is also about 6 times faster (for the same size of code).
Note: Microchip's ISP is presented as a "two-pin ISP" but in fact a third pin is needed to select the programming mode (and this is without counting the M CLR, VDD, and GND pins).
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1
BENCHMARK ST72 vs. PIC16
4.11 IN CIRCUIT DEBUGGING (PIC16F87X ONLY) It is available on the PIC16F87x only. It uses the in situ programming serial interface (MCLR, VDD, GND, RB7 and RB6). The debugger functionality takes a part of the MCU resources for its own use: Table 31. Resources used by the In Circuit Debugging
I/O pins S t ack Program Memory Data Memory R B6,RB7 1 level Last 100h words
Not precised in the Microchip documentation
N o further data is available in the Microchip documentation at the time this document is written.
4.12 RESET PIN Table 32. Reset
PIC16 Direction Internal Pull-up Pin filtered Other Input only no no. But Schmitt trigger input. Y es Y es ST72 Bi-directional pin
Can receive a +12V to en- (to be taken into account the Reset pin ter ISP mode must be pulled low for at least 20 s)
· Conclusion The ST72 reset pin is more useful and secure. It allows you to easily put all the board in reset when the MCU generates a Reset (internal or external). Its internal pull-up reduces the number of external components. 4.13 PACKAGE The SMD version packages are the same for both (SO28). For the DIP package, the situation is different: Microchip proposes a PDIP28 package and ST a SDIP32 package. Despite the fact that the ST72 package has more pins, it is smaller but cannot be plugged on the standard test board
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BENCHMARK ST72 vs. PIC16
5 DEVICE SUMMARY
Table 33. Device Summary
PIC16F87x
Architecture Program Memory RAM Data EEPROM Harvard RISC Up to 8K*14 (really 8092 instructions) 368*8 accessible through 4 banks of 128 bytes 128*8 EEPROM accessible only through an indexed mode. (9 instructions are needed do read one EEPROM Byte) 8*13 (cannot be accessed, no push or pop) External / Internal Instruction time: Min / Max Number of instruction Multiplication / Division Number of Addressing Mode Sources / Vectors / Priority Register saved Reaction time Min / Max 20MHz / 5Mhz (FOSC/4) 0.2s / 0.4s 35 SW / SW 3 (indexed mode need bank switching) 13 / 1 PC (The context is not automatically saved) 1.4s / 2.8s (This time take into account the code needed to save the context, The difference is mainly due to the number of registers saved) For Fosc >4MHz : 4.5V-5.5V For Fosc 4MHz : 2 V- 5.5 V RC / Ceramic / Crystal Typ / Max (Run mode) Power saving mode Direction control Mode control Output mode Input mode Power output 10mA/ 20mA @Fext=20MHz one sleep mode Individual Global Push-Pull (except 1 pin true open-drain). Floating / 8 pins may have internal pull-up All outputs are HIGH SINK: VOL=0.6V at 8.5mA Von Neuman CISC 8K*8 (-> up to 4096 instructions) 256*8 with no bank switching
ST72254
Memory
Stack Frequency
128*8 16 MHz / 8 MHz (FOSC/2) 0.250s / 1.5s 63 HW / SW 11 19 / 7 PC, CCR, A, X 1.25 s / 2.75s (the difference between these two times is mainly due to different instruction times) 3 V - 5.5 V RC / Ceramic / Crystal / internal Clock security system (clk filter, safe oscillator) 5.5mA / 10mA@Fext=16MHz three power saving modes Individual Individual Push-Pull / open-drain (logic level except 2 pins) Floating / Pull-Up with interrupt Normal outputs: VOL=0.5V at 2mA 8 High sink outputs: VOL=0.5V at 8mA
Instruction
Interrupt
Voltage range Oscillator Consumption
I/O
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BENCHMARK ST72 vs. PIC16 Table 33. Device Summary
PIC16F87x
Watchdog Time out: Min time / Max time Number of time out values Other Timers PWM/IC/OC usable in the same time Timer Access to the 16-bit register PWM Resolution: Max / at 1KHz/ at 20Khz Speed: Master / Slave SPI 7ms-30ms / 896ms-4.2s (depending of the device) 8 / (the prescaler is shared with TIMER0) Dedicated on-chip RC. The WDT can wake-up the CPU when it is in sleep mode 2 8-bit timers / 1 16-bit timer 2 PWM (same frequency) or 2 IC (same time base) or 2 OC (same time base) or 1 PWM and 1 IC No simple way to access 16-bit timer (12 instructions to read the timer) 10-bit / 1024 / 1000 5 MHz / 4.1MHz Receive overflow detection The PIC does not allow to use simultaneously the I²C and the SPI. 100 kHz or 400 kHz / 7-bit or 10-bit yes / SW Receive overflow detection The PIC does not allow to use simultaneously the I²C and the SPI. Asynchronous (Full duplex) (max 312Kbit/s) Synchronous (half duplex) (max 5000Kbit/s)
ST72254
1.5ms / 98ms (Fosc=16MHz) 64 It is possible to load any value in the timer, to easily choose the time-out period 2 16-bit timers 2 PWM and 2 IC or 1 PWM and 2 OC and 3 IC or 2 One Pulse Mode and 2 IC and 2 OC or 4 IC and 4 OC security system (latches of LSB after reading the MSB) 16-bit / 8000 / 200 2 MHz / 4MHz Writes collision detection: 100 kHz or 400 kHz / 7-bit or 10-bit yes / HW bus lost arbitration detection Bus Error detection
I²C
Speed / Addressing mode Multi-master / Bus arbitration Other
USART / SCI
Mode (max speed) Resolution / Channel / Conversion time Voltage reference Level Hysteresis
no
ADC
8-bit / 6 / 3s 10-bit / 5 / 20s internal (VDD) Internal (VDD) or external Can work in sleep mode, using a On-Chip RC and IT to wake-up One level for 5V operating Done by holding in reset state for a minimum time The reset state is not visible externally 3 levels 250mV of hysteresis The reset state is visible externally 5 sequence on IPsel 15ms to program 16*8-bit no 37/40
LVD RESET ISP ICD
Pins needed Way to enter programming mode speed In Circuit Debugging
5 or 6 (depending of the mode used) +12V on Mclr or sequence on PGM 10ms to program 14-bit (one opcode) yes
BENCHMARK ST72 vs. PIC16
6 WEAK / STRONG POINTS
Table 34. Weak / Strong points
PIC16F87x ST72254
Both MCU have the same execution speed at their maximum frequency (PIC@20MHz and ST7@16MHz external freq.) - Average assembler benchmark speed ratio: 1.03 (ST7 speed / PIC speed) Core Execution Speed - C compiler benchmark speed ratio: 1.02
À Fast bit manipulation À Fast direct memory access
=> Fast execution of small algorithms
À Fast calculation (8-bit HW multiplication) À Fast and easy indirect memory management À Fast and easy constant table manipulation
=> Fast and easy implementation of complex algorithms
Power Ä Consumption
À The SPI or I²C are still working in sleep mode (for slave operations)
Only 1 low power consumption mode ÄÄ To keep a timer active while in sleep, a dedicated oscillator is needed
ÀÀ Lower consumption about 2 times for the same speed À 4 power saving modes (slow, wait, slow-wait, halt)
Instruction Set
Stack
À Instructions are slower but they are more powerful À Instructions are single cycle (except branch which need 2 cycles) (difference between RISC/CISC) Ä Only 3 addressing modes À Many addressing modes (11) with 2 index registers Ä Manipulation of the only index register is not easy (no direct load of literal value) À Fast 8-bit HW multiplication ÀÀ Push/Pop instructions, Stack pointer is R/W ÀÀ 128 bytes deep ÄÄ No software access Ä The Stack pointer cannot be used as an index register ÄÄ Only 8 levels deep
=> Allow recursive calls and heavy imbrication level
Ram
EEPROM
À More RAM on the PIC16F876 (368 bytes) ÄÄ Need bank switching (each bank contains up to 96 bytes of user RAM) À Allow to store permanent data (256 bytes) À It is possible to read or write the program memory Ä Difficult read access to EEPROM or FLASH (9 or 12 opcodes needed) Ä Only 1 interrupt vector => Software overhead to find the interrupt source Ä No hardware context saving (need to be done by software)
ÀÀ No bank switching À Direct read access to program memory ÄÄ No way to store permanent data on the ST72254
but some ST7 have a 256-bytes EEPROM ex: ST72331J2
Interrupt
À Each peripheral has its own interrupt vector À 7 different vectors => Fast and easy interrupt management Ä static priority, but some ST7 have a nested interrupt feature
ex.:ST72311R6
Clock
Ä RC oscillator usable up to only 4MHz (Fcpu=1MHz)
À Internal RC (4MHz) À External RC oscillator usable up to 14 Mhz (=> Fcpu=7Mhz) À Safe clock, Clock filter, with clock spike detection
=> Allow secure clock management for critical applications
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BENCHMARK ST72 vs. PIC16 Table 34. Weak / Strong points
PIC16F87x À 3 timers: One 16-bit and two 8-bit À Better PWM precision (max: 10-bit) for frequencies over 3.9KHz À The 16-bit timer can use a dedicated slow oscillator ÄÄ To keep a timer active in sleep mode, a dedicated oscillator is needed. Ä No easy way to access the 16-bit timer (12 opcodes to read the timer) ÄÄ Many interactions between the 3 timers:
The 2 PWMs must run at the same frequency The prescaler of TIMER0 is shared with the watchdog The output of TIMER2 is needed to generate some baud rates of the SPI
ST72254
Timer
À À À À
2 true 16-bit timers No interaction between the 2 timers Better PWM precision (max: 16-bit) for frequencies below 3.9KHz Secure and easy access to the 16-bit timer registers
À Push pull or open drain output modes with individual control À High sink output for all pins => direct led driving À Floating or internal pull-up input modes with individual control Ä Only push-pull output mode available (except for two open-drain pins) I/O Ä When using the Interrupt-On-Change feature (pins RB4-7) reading PORTB must Ä Activation of the internal Pull-up, active also activates the interrupt. be avoided Ä Only 8 high sink I/Os À Reception overrun detection À Transmission speed up to 5MHz (@Fosc=20MHz) À Reception speed up to 4MHz (@Fosc=16MHz) Ä Reception speed only up to 2.27MHz (@Fosc=20MHz) SPI Ä Transmission speed only up to 2Mhz (@Fosc=16MHz) Ä Need TIMER2 output for some baud rate ÄÄ Can not be used at the same time as the I²C cell À Reception overrun detection À Multi-master support with hardware bus arbitration I²C ÄÄ Can not be used at the same time as the SPI cell USART / SCI À Present ÄÄ No SCI on the ST72254. But some ST7 have a SCI cell ex: ST72331J2 ÀÀ 10-bit Resolution ADC À Automatic sampling rate with low software overhead À Fast conversion (3s, up to 333KHz) Ä Slow conversion (20s, up to 50KHz) À Faster (about 6 times) In System ÄÄ Fully functional at Vdd=+5V ONLY Programming À Works at any VDDlevel
In Circuit debugging Voltage Range
ÀÀ Present (but not yet fully described in the Microchip documentation) À Larger voltage range (2V-5.5V) Ä 2 different devices in order to cover the entire voltage range ÄÄ Below 4.5V, the external frequency must be decreased to 4MHz
Ä No À between 3.5V and 5.5V the maximum frequency can be used
(16MHz)
Ä smaller voltage range (3V-5.5V)
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BENCHMARK ST72 vs. PIC16
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