AN1462 APPLICATION NOTE
Connecting the MPC555 32-bit Microcontroller to the M616Z08 SRAM
INTRODUCTION
This application note describes a method of connecting the M616Z08 SRAM to the MPC555 Microcontroller. The M616Z08 is an advanced, 128 Kbit SRAM memory from ST Microelectronics, Inc., which is configured with an 8 Kbit x 16 bus width. The MPC555 is a member of Motorola's PowerPC family of integrated microprocessors. It is a general-purpose, 32-bit microcontroller with a wide variety of application areas, but it is particularly targeted toward automotive applications.
ADVANTAGES OF SRAM
The M616Z08 is a 128 Kbit (131,072 bits) CMOS SRAM, organized by 16 bits. It has an access time of 20ns and it will operate in the temperature range of 40 to 125C. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.6V 10% or 3.3V 1-% supply, and all inputs and outputs are TTL compatible. Two WRITE enable pins allow writing to upper and lower bytes. The M616Z08 is available in a 44-lead SOIC package.
MPC555 BUS ARCHITECTURE
The MPC555's Bus architecture can be daunting on first appearance. There are many control lines to allow for 8-bit accesses, 16-bit accesses, 32-bit accesses, bus arbitration, and so forth. Many applications do not need to make use of these features. Only a simple connections is considered here. The MPC555 can be configured as Big-Endian or Little-Endian, with the normal configuration being Big-Endian. The M616Z08 part is Big-Endian insofar as the hexadecimal data used to control the command interface uses D0 to equate to the LSB. The MPC555's memory controller includes control lines that are suitable for connecting to the M616Z08 without the need for glue logic. The MPC555 is a 3.3V processor and will connect to the M616Z08 directly, without the need for any transceivers. Software must set up the MPC555 registers to make the control signals compatible with the M616Z08. How the registers are programmed is beyond the scope of this application note. However, the M616Z08 can only operate in the asynchronous mode.
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TABLE OF CONTENTS
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ADVANTAGES OF SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 MPC555 BUS ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 M616Z08 BUS ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 1. M616Z08 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. M616Z08 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 "Operational" Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. WE (0,1) States During Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 3. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DC Characteristics Comparison Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 4. Input/Output DC Characteristics Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 MPC555 to M616Z08 CONNECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. MPC555 to M616Z08 Interface (Hardware Hookup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 5. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
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M616Z08 BUS ARCHITECTURE
Figure 1 and Table 1 show the control, address, and data pins of the M616Z08. Figure 1. M616Z08 Logic Diagram
VCC
13 A0-A12
16 DQ0-DQ15
WE0 WE1 CE OE
M616Z08
VSS
AI04213
Table 1. M616Z08 Signal Names
A0-A12 DQ0-DQ15 CE OE WE0 WE 1 V CC VSS Address Inputs Data Input/Output Chip Enable Output Enable WRITE Enable DQ 0-7
WRITE Enable DQ 8-15
READ Mode
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The M616Z08 is in the READ Mode whenever WRITE Enable (WE0 or WE1) is High with Output Enable (OE) Low, and the Chip Enable (CE) is asserted. This provides access to data from sixteen of the 131,072 locations (bits) in the static memory array, specified by the 13 address inputs. Valid data will be available at the sixteen output pins within 20ns after the last stable address, providing OE is Low and CE is Low.
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WRITE Mode The M616Z08 is in the WRITE Mode whenever the WE0 (low memory addresses) or WE1 (high memory addresses) and the CE pin are low. Either the Chip Enable input (CE) or the WRITE Enable input (WE0 or WE1) must be de-asserted during address transitions for subsequent WRITE cycles. WRITE begins with the concurrence of Chip Enable being active with WE0 or WE1 low. The WRITE cycle can be terminated by the earlier rising edge of CE, or WE0/WE1. If the Output is enabled (CE = Low and OE = Low), then WE0 or WE1 will return the outputs to high impedance within 10ns of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for 10ns before the rising edge of WRITE Enable, or for 10ns before the rising edge of CE, whichever occurs first, and remain valid for 0ns. "Operational" Mode The M616Z08 has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (CE = High). An Output Enable (OE) signal provides a high speed tri-state control, allowing fast READ/WRITE cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs WE0 or WE1 and CE as summarized in "Operating Modes" (below). Table 2. WE (0,1) States During Access
WRITE Enable WE0 WE1 Used during 16-bit Port Access WRITE Enable for DQ (0-7) WRITE Enable for DQ (8-15)
Table 3. Operating Modes
Operation Deselect Word WRITE Byte 0 WRITE Byte 1 WRITE Byte 1 WRITE, Byte 1 READ Byte 1 WRITE, Byte 0 READ Word READ CE 1 0 0 0 OE X(1) 1 WE0
DC Characteristics Comparison Table Table 4 gives a summary of the Input/Output DC Characteristics on the high and low voltage levels and shows that they are compatible.
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Table 4. Input/Output DC Characteristics Comparison
Comment VIL3 VIH3 VOL3 VOH3 MPC555 0.8V max 2.0V min 0.5V max 2.4V min VOL VOH VIL VIH M616Z08 0.2V max VCC 0.2V min 0.3 * VCC max 0.7 * VCC min MPC555 Low Input from M616Z08 MPC555 High Input from M616Z08 M616Z08 Low Input from MPC555 M616Z08 High Input from MPC555
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DQ815 Hi- Z Hi- Z Hi- Z Hi- Z Data Hi- Z Data
DQ0DQ7 H i-Z H i- Z H i- Z H i- Z H i- Z Data Data
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MPC555 TO M616Z08 CONNECTION
Figure 2 shows a connection scheme for the MPC555 to M616Z08 interface. This scheme creates an 8 Kbit x 32 bit wide data bus using two M616Z08 SRAMs. Figure 2. MPC555 to M616Z08 Interface (Hardware Hookup)
MPC555/565 M616Z08 Address [12:0] Address [12:0] Data [15:0] WE#BE#[3:0] WE#BE#0 WE#BE#1 Data [15:0] WE0# WE1# OE# CS#[1] CE#
OE# CS#[3:0]
M616Z08
Address [12:0] Data [31:16] WE#BE#2 WE#BE#3
CONCLUSION
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The M616Z08 can be connected to the MPC555 in a "glueless" configuration. This SRAM will operate from 2.34 to 3.6V. It is configured as an 8 Kbit x 16 memory. The SRAM has equal cycle and access times of 20ns. It also has a tri-state common I/O and two WRITE Enable pins to allow writing to upper and lower bytes. It is the responsibility of the software to initialize the memory controller interface of the MPC555 Microcontroller to access the SRAM.
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CE#
AI05649
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REVISION HISTORY
Table 5. Document Revision History
Date August 3, 2002 Version 1.0 First Issue Revision Details
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If you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: ask.memory@st.com (for general enquiries) Please remember to include your name, company, location, telephone number and fax number.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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