AN2381 Application note
LIS3LV02DL: 3-Axis - 2g/6g digital output low voltage linear accelerometer
Introduction
This document is intended to give application notes for the low-voltage 3-axis digital output linear MEMS accelerometer provided in LGA package. The LIS3LV02DL is a three axes digital output linear accelerometer that includes a sensing element and an IC interface able to take the information from the sensing element and to provide the measured acceleration signals to the external world through an I2C/SPI serial interface. The sensing element, capable of detecting the acceleration, is manufactured using a dedicated process developed by ST to produce inertial sensors and actuators in silicon. The IC interface instead is manufactured using a CMOS process that allows high level of integration to design a dedicated circuit which is factory trimmed to better match the sensing element characteristics. The LIS3LV02DL has a user selectable full scale of 2g, 6g and it is capable of measuring acceleration over a bandwidth of 640 Hz for all axes. The device bandwidth may be selected accordingly to the application requirements. A self-test capability allows the user to check the functioning of the system. The device may be configured to generate an inertial wake-up/free-fall interrupt signal when a programmable acceleration threshold is crossed at least in one of the three axes. The LIS3LV02DL is available in plastic SMD package and it is specified over a temperature range extending from -40C to +85C. The small size and weight of this package make it an ideal choice for handheld portable applications such as cell phones and PDAs or any other application where size, weight and package performance are required.
June 2006
Rev 1
1/47
www.st.com
Contents
AN2381
Contents
1 2 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical connection and board layout hints . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 Electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power supply and board layout hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 I2C Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1 4.1.2 4.1.3 I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C Subsequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C Read and Write sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2
SPI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2.1 4.2.2 4.2.3 4.2.4 Read & Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI Read in 3-wires Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Registers Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.1 5.1.2 Reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Registers loaded at Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2
Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.1 5.2.2 5.2.3 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3
Data and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 OUTX_L (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUTX_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUTY_L (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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AN2381 5.3.6 5.3.7 5.3.8
Contents OUTY_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 OUTZ_L (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 OUTZ_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4
Free-Fall and Wake-Up Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FF_WU_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FF_WU_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FF_WU_ACK (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FF_WU_THS_L (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FF_WU_THS_H (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FF_WU_DURATION (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5
Direction-Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 DD_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DD_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DD_ACK (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DD_THSI_L (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DD_THSI_H (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DD_THSE_L (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DD_THSE_H (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1 6.2 Star t-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Reading acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2.1 6.2.2 6.2.3 Using the Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Using the Data-Ready Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Using the Block Data Update feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3
Understanding acceleration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.1 6.3.2 6.3.3 Data Alignment: 12 and 16 bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Big-Little Endian Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Example of Acceleration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.4 6.5
Interrupt generation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Iner tial wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.5.1 6.5.2 HP filter bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Using the HP filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.6 6.7
Free-Fall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Direction detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Contents
AN2381
6.8 6.9 6.10
Output data rate selection and reading timing . . . . . . . . . . . . . . . . . . . . . 44 Data Ready vs. Interrupt Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Using the external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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AN2381
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C/SPI signals mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output Data Registers Content vs. Acceleration (FS= 2g) . . . . . . . . . . . . . . . . . . . . . . . . . 39 Output data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Timing Value to Avoid Loosing the Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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List of figures
AN2381
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 LIS3LV02DL electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C Subsequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read & Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Multiple Bytes SPI Read Protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Multiple Bytes SPI Write Protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI Read Protocol In 3-wires Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 HP Filter Transfer Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Block diagram of data output path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FF_WU_CFG High and Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DD_CFG High and Low Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Free-Fall, Wake-Up Interrupt Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Direction Detector Interrupt Generator for X axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Reading Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Interrupt and DataReady Signal Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 45 Data Ready Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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AN2381
Theory of operation
1
Theory of operation
The LIS3LV02DL is a high performance, low-power, LGA packaged, digital output 3-axis linear accelerometer. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I2C/SPI serial interface. A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is up to 100fF. The complete measurement chain is composed by a low-noise capacitive amplifier which converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by three analog-to-digital converters, one for each axis, that translate the produced signal into a digital bit stream. The converters are tightly coupled with dedicated reconstruction filters which remove the high frequency components of the quantization noise and provide low rate and high resolution digital words. The charge amplifier and the converters are operated respectively at 61.5 kHz and 20.5 kHz. The data rate at the output of the reconstruction depends on the user selected Decimation Factor (DF) and spans from 40 Hz to 2560 Hz. The acceleration data may be accessed through an I2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS3LV02DL features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in digital system employing the device itself. The LIS3LV02DL may also be configured to generate an inertial Wake-Up, Direction Detection or Free-Fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off). The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation. This allows the user to employ the device without further calibration.
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Theory of operation Figure 1. Device block diagram
AN2381
X+ Y+ Z+
CHARGE AMPLIFIER
M UX DE M UX
Reconstruction Filte r I2C CS SCL/SPC SDA/SDIO SDO
a
ZYX-
Reconstruction Filte r
Regs Array
SPI
Reconstruction Filte r
TRIMMING SELF TEST REFERENCE CIRCUIT
CLOCK
CONTROL LOGIC & INTERRUPT GEN.
RDY/INT
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AN2381
Electrical connection and board layout hints
2
2.1
Electrical connection and board layout hints
Electrical connection
The typical electrical connection of the LIS3LV02DL is shown in Figure 2 Figure 2. LIS3LV02DL electrical connection
Z
Vdd_IO
SDA/SDI/SDO SCL/SPC
1
RDY/INT CS
Y
SDO
6 7 8 9 LIS3LV02DL
1 16 15 14
X
(TOP VIEW)
DIRECTION OF THE DETECTABLE ACCELERATIONS
Vdd
100nF GND
10uF
Digital signal from/to signal controller.Signal's levels are defined by proper selection of Vdd_IO
The device core is supplied through Vdd line (Vdd typ=2.5V) while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 F Al) should be placed as near as possible to the pin 13 of the device. Both the voltage supplies must be present at the same time to have proper behavior of the IC. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication bus. The central die pad and pin #1 indicator are physically connected to GND. The functionality of the device and the measured acceleration data are selectable/accessible through the I2C/SPI interface. When using the I2C, CS must be tied high while SDO must be left floating.
2.2
Power supply and board layout hints
The LIS3LV02DL is designed for a voltage supply spanning from 2.16V up to 3.6V. The typical current consumption in normal mode at 2.5V is 600A. Adequate power supply decoupling is required to ensure IC performances. The optimum decoupling is achieved by using two capacitors of different types that target different kinds of noise on the power supply leads. To attenuate high frequency transients, spikes, or digital
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Electrical connection and board layout hints
AN2381
hash on the line it is recommended the use of one 100nF ceramic or polyester capacitor which must be placed as close as possible to device Vdd lead. For filtering lower-frequency noise signals, a larger aluminum capacitor of 10F or greater should be placed near the device in parallel to the former capacitor. It is recommended that the afore capacitors are placed as close as possible to pin 13.
2.3
Soldering information
The LGA-16 package is lead free and green package qualified for soldering heat resistance according to JEDEC J-STD-020C. Land pattern and soldering recommendations are available upon request.
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AN2381
Absolute maximum ratings
3
Absolute maximum ratings
Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 1.
Symbol Vdd Vdd_IO Vin Supply voltage(1)
Absolute maximum ratings
Ratings Maximum Value -0.3 to 6 -0.3 to Vdd +0.1 -0.3 to Vdd_IO +0.3 3000g for 0.5 ms Acceleration (Any axis, Powered, Vdd=2.5V) 10000g for 0.1 ms 3000g for 0.5 ms Acceleration (Any axis, Unpowered) 10000g for 0.1 ms Operating Temperature Range Storage Temperature Range -40 to +85 -40 to +125 4.0 (HBM) C C kV V kV Unit V V V
I/O pins Supply voltage(1) Input voltage on any control pin (CS, SCL/SPC, SDA/SDI/SDO, CK)
APOW
AUNP TOP TSTG
ESD
Electrostatic discharge protection
200 (MM) 1.5 (CDM)
1. Supply voltage on any pin should never exceed 6.0V.
Warning:
This is a ESD sensitive device, improper handling can cause permanent damages to the part.
Warning:
This is a mechanical shock sensitive device, improper handling can cause permanent damages to the part.
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Digital interfaces
AN2381
4
Digital interfaces
The registers embedded inside the LIS3LV02DL may be accessed through I2C and SPI serial interfaces. They are mapped onto the same pads. To select/exploit the I2C interface, CS line must be tied high. Table 2. I2C/SPI signals mapping
Description SPI chip select (CS) I2C/SPI selector (1: I2C mode; 0: SPI enabled) SPI CK line (SPC) I2C clock line (SCL) SPI data in (SDI) I2C serial data (SDA) SPI data out (SDO) -when in 3-wire modeSDO SPI data out (SDO) -when not in 3-wire mode-
Pin Name CS SCL/SPC SDI/SDA/SDO
4.1
I2C Bus interface
The LIS3LV02DL I2C is a bus slave. The I2C is employed to write/read the data into/from the registers. The relevant I2C terminology is shown in Table 3: Table 3. Terminology
Term Transmitter Receiver Master Slave Description The device which sends data to the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by the master
There are two signals associated with the I2C bus: SCL and SDA. These pins are described in the subsequent table: Table 4. I2C Pin Description
Term SCL SDA Serial CLock Line Serial DAta Line Description
SDA is a bidirectional line. Both SCL and SDA are connected to a positive supply voltage via a pull-up resistor. When the bus is free both lines are HIGH.
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AN2381
Digital interfaces
4.1.1
I2C Operation
The transaction on the bus is started through a START signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH (refer to ST condition in the following paragraph). After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave (SA subsequence). When an address is sent, each device in the system compares the first seven bits after a start condition with its own address. If they match, the device considers itself addressed by the Master. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse (SAK subsequence). A receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. The I2C embedded inside the LIS3LV02DL behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a salve address is sent (SA), once a slave acknowledge has been returned (SAK), a 8-bit sub-address will be transmitted (SUB): the 7 LSB represent the actual register address while the MSB enables address autoincrement. If the MSB of the SUB field is `1', the SUB (register address) will be automatically increased by one to allow multiple data read/write at increasing addresses. Otherwise if the MSB of the SUB field is `0', the SUB will remain unchanged and multiple read/write on the same address can be performed. If the LSB of the slave address was `1' (read), a repeated START (SR) condition will have to be issued after the sub-address byte; if the LSB is `0' (write) the Master will transmit to the slave with direction unchanged.
4.1.2
I2C Subsequences
In order to better define subsequences and to clarify line SCL and SDA behavior, a description containing discrete value of SCL and SDA will follow. In column there is the value present on line SCL and SDA in discrete timing. These simple subsequences are used to realize complex commands described in the following paragraph.
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Digital interfaces Figure 3. I2C Subsequences
AN2381
ST: START condition SCL SDA 1111 1100
SR: Repeated START condition SCL SDA 1111 1100
SAD: Slave address (binary address: abcdefgh. In LIS3LV02DL "abcdefg" = "0011101") SCL SDA 00110 0aaaa 0110 bbbb 0110 cccc 0110 dddd 0110 eeee 0110 ffff 0110 gggg 0110 hhhh
Bit h=0 => write, h=1 => read SAK: Slave acknowledge (Z means high impedance) SCL SDA (force) SDA (read) 0011 ZZZZ XX00 Check that SDA is 0 after SCL=1
SUB: Sub address (binary address: abcdefgh) SCL SDA 00110 0aaaa 0110 bbbb 0110 cccc 0110 dddd 0110 eeee 0110 ffff 0110 gggg 0110 hhhh
Bit a=0 => do not increment address in multiple mode a=1 => increment address in multiple mode DATA (Master): send DATA byte (binary number: abcdefgh) SCL SDA 00110 0aaaa 0110 bbbb 0110 cccc 0110 dddd 0110 eeee 0110 ffff 0110 gggg 0110 hhhh
DATA (Slave): read DATA byte (binary number: abcdefgh) SCL SDA (force) SDA (read) 00110 ZZZZ a 0110 ZZZZ b 0110 ZZZZ c 0110 ZZZZ d 0110 ZZZZ e 0110 ZZZZ f 0110 ZZZZ g 0110 ZZZZ h
SP: STOP condition SCL SDA MAK: Master Acknowledge SCL SDA 0011 0000 1111 0011
NMAK: No Master Acknowledge SCL SDA 0011 or 00011 ZZZZ or 1111
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Digital interfaces
4.1.3
I2C Read and Write sequences
The previous subsequences are used to realize actual write and read sequences described in the tables below. Transfer when Master is writing one byte to slave:
Master Slave ST SA + W SAK SUB SAK DATA SAK SP
Transfer when Master is writing multiple bytes to slave:
Master Slave ST SA + W SAK SUB SAK DATA SAK DATA SAK SP
Transfer when Master is receiving (reading) one byte of data from slave:
Master Slave ST SA + W SAK SUB SAK SR SA + R SAK DATA NMAK SP
Transfer when Master is receiving (reading) multiple bytes of data from slave:
Master Slave Master Slave DATA ST SA + W SAK MAK DATA SUB SAK SR SA + R SAK NMAK DATA SP MAK
Data are transmitted in byte format. Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant Bit (MSB) first. If a receiver can't receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn't acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition (SP). Each data transfer must be terminated by the generation of a STOP condition.
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Digital interfaces
AN2381
4.2
SPI Bus Interface
The LIS3LV02DL SPI is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SPDI and SPDO.
4.2.1
Read & Write Protocol
Figure 4.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
Read & Write Protocol
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the Chip Select and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the Read Register and Write Register commands are completed in 16 clocks pulses or in multiple of 8 in case of multiple byte read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address will be auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is 0 the address used to read/write data remains the same for every block. When MS bit is 1 the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged.
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Digital interfaces
4.2.2
SPI Read
Figure 5. SPI Read Protocol
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clocks pulses. Multiple byte read command is performed adding blocks of 8 clocks pulses at the previous one.
bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reading. Figure 6.
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0
Multiple Bytes SPI Read Protocol (2 bytes example)
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8
4.2.3
SPI Write
Figure 7. SPI Write Protocol
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
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Digital interfaces
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The SPI Write command is performed with 16 clocks pulses. Multiple byte write command is performed adding blocks of 8 clocks pulses at the previous one.
bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writing. Figure 8.
CS SPC SDI
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
Multiple Bytes SPI Write Protocol (2 bytes example)
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
4.2.4
SPI Read in 3-wires Mode
3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in CTRL_REG2. Figure 9. SPI Read Protocol In 3-wires Mode
CS SPC SDI
RW MS AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clocks pulses:
bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
Multiple read command is also available in 3-wires mode.
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Registers Description
5
5.1
Registers Description
Registers Address Map
The table given below provides a listing of the registers embedded in the device and the related address Table 5.
.
Registers address map
Register Address Type Binary 0 0 00 - 001110 Hex 00 - 0E 0F 10 - 15 16 17 18 19 1A 1B 1C-1F 20 21 22 23 111 0 100 dummy Dummy register Not Used 0 output output output output output output Reserved 0 0 dummy Dummy register Not Used 0 Calibration Calibration Calibration Calibration Calibration Calibration 00111010 Reserved Loaded at boot Loaded at boot Loaded at boot Loaded at boot Loaded at boot Loaded at boot Reserved Reserved Default Comment
Reg. Name
WHO_AM_I
r
001111 010000 - 010101
OFFSET_X OFFSET_Y OFFSET_Z GAIN_X GAIN_Y GAIN_Z
rw rw rw rw rw rw
010110 010111 011000 011001 011010 011011 011100 -011111
CTRL_REG1 CTRL_REG2 CTRL_REG3 HP_FILTER RESET
rw rw rw r
10 0 0 100001 100010 100011
0100100 - 0100110 24 - 26 STATUS_REG OUTX_L OUTX_H OUTY_L OUTY_H OUTZ_L OUTZ_H rw r r r r r r 100111 101000 101001 101010 101011 101100 101101 101110 - 101111 FF_WU_CFG FF_WU_SRC FF_WU_ACK rw rw r 110000 110001 110010 110011 FF_WU_THS_L rw 110100 27 28 29 2A 2B 2C 2D 2E - 2F 30 31 32 33 34
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Registers Description Table 5. Registers address map (continued)
Register Address Reg. Name FF_WU_THS_H FF_WU_DURATION Type Binary rw rw 110101 110110 110111 DD_CFG DD_SRC DD_ACK rw rw r 111000 111001 111010 111011 DD_THSI_L DD_THSI_H DD_THSE_L DD_THSE_H rw rw rw rw 111100 111101 111110 111111 35 36 37 38 39 3A 3B 3C 3D 3E 3F 0 0 0 0 0 0 dummy Hex 0 0 Default
AN2381
Comment
Not Used
Dummy register Not Used
5.1.1
Reserved registers
Registers marked as reserved must not be changed. Random changes of the content of those registers might cause permanent damages to the device.
5.1.2
Registers loaded at Boot
The LIS3LV02DL is factory trimmed. The content of the registers that are loaded at boot must not be changed. Their content is automatically restored when the device is poweredup.
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Registers Description
5.2
5.2.1
Control registers
CTRL_REG1 (20h)
Control register #1.
PD1 PD0 DF1 DF0 ST Zen Yen Xen
PD1, PD0
Power Down Control. Default value: 00 (00: power down mode; x1, 1x: normal mode) Decimation Factor Control. Default value: 00 (00: decimate by 512 01: decimate by 128 10: decimate by 32 11: decimate by 8) Self Test Enable. Default value: 0 (0: normal mode; 1: self test enabled) Z-axis enable. Default value: 1 (0: channel disabled; 1: channel enabled) Y-axis enable. Default value: 1 (0: channel disabled; 1: channel enabled) X-axis enable. Default value: 1 (0: channel disabled; 1: channel enabled)
DF1, DF0
ST
Zen
Yen
Xen
PD1, PD0 bits allow to turn on the device. The device is in power-down mode when PD1, PD0= "00" (default value after boot). The device is in normal mode when either PD1 or PD0 is set to 1. DF1, DF0 bits allow to modify the decimation factor of the internal digital filter thus selecting the data rate at which acceleration samples are produced. The default value is 00 which corresponds to a data-rate of 40Hz (decimation factor of 512). By changing the content of DF1, DF0 to "01", "10" and "11" the selected data-rate will be set respectively equal to 160Hz, to 640Hz and to 2560Hz which correspond to a decimation of 128, 32, 8 respectively. ST bit is used to activate the self test function. When the bit is set to 1, an output change will occur to the device outputs thus allowing to check the functionality of the whole measurement chain. Zen bit enables the Z-axis measurement channel when set to 1. The default value is 1. Yen bit enables the Y-axis measurement channel when set to 1. The default value is 1. Xen bit enables the X-axis measurement channel when set to 1. The default value is 1.
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Registers Description
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5.2.2
CTRL_REG2 (21h)
Control register #2
.
FS
BDU
BLE
BOOT
IEN
DRDY
SIM
DAS
FS
Full Scale selection. Default value: 0 (0: +/- 2g; 1: +/- 6g) Block Data Update. Default value: 0 (0: continuous update; 1: output registers not updated until MSB and LSB reading) Big/Little Endian selection. Default value: 0 (0: little endian; 1: big endian) Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) Interrupt Enable. Default value: 0 (0: data-ready on RDY pad; 1: interrupt signal on RDY pad) Enable Data-Ready generation. Default value: 0 (0: data-ready gen. disabled; 1: enable data-ready generation) SPI Serial Interface Mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface) Data Alignment Selection. Default value: 0 (0: 12 bit right justified; 1: 16 bit left justified)
BDU
BLE
BOOT
IEN
DRDY
SIM
DAS
FS bit is used to select Full Scale value. After the device power-up the default full scale value is +/-2g. In order to obtain a +/-6g full scale it is necessary to set FS bit to `1'. BDU bit is used to inhibit output registers update until both upper and lower register parts are read. In default mode (BDU= `0') the output register values are updated continuously. If for any reason it is not sure to read faster than output data rate it is recommended to set BDU bit to `1'. In this way the content of output registers is not updated until both MSB and LSB are read avoiding to read values related to different sample time. BLE bit is used to select Big Endian or Little Endian representation for output registers. In Big Endian's one, MSB acceleration value is located at addresses 28h (X-axis), 2Ah (Y-axis) and 2Ch (Z-axis) while LSB acceleration value is located at addresses 29h (X-axis), 2Bh (Yaxis) and 2Dh (Z-axis). In Little Endian representation (default choice) the order is inverted (refer to data register description for more details). BOOT bit is used to refresh the content of internal registers stored in the flash memory block. At the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. If for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. When BOOT bit is set to `1' the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every accelerometer. They permit a good behavior of the device and normally they have not to be changed. At the end of the boot process the BOOT bit is set again to `0'.
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Registers Description IEN bit is used to switch the value present on data-ready pad between Data-ready signal and Interrupt signal. At power up the Data-ready signal is chosen. It is however necessary to modify DRDY bit to enable Data-ready signal generation. DRDY bit is used to enable DataReady pad activation. If DRDY bit is `0' (default value) on DataReady pad a `0' value is present. If a DataReady signal is desired it is necessary to set to `1' DRDY bit. DataReady signal goes to `1' whenever a new data is available for all the enabled axes. For example if Z-axis is disabled, DataReady signal goes to `1' when new values are available for both X and Y axes. DataReady signal comes back to `0' when all the registers containing values of the enabled axes are read. To be sure not to loose any data coming from the accelerometer data registers must be read before a new DataReady rising edge is generated. In this case DataReady signal will have the same frequency of the data rate chosen. SIM bit selects the SPI Serial Interface Mode. When SIM is `0' (default value) the 4-wire interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire interface mode output data are sent to SDA_SDI pad. DAS bit selects between 12 bit right justified and 16 bit left justified data representation. The first case is the default case and the most significant bits are replaced by the bit representing the sign.
5.2.3
CTRL_REG3 (22h)
Control register #3
.
ECK
HPDD
HPFF
FDS
res
res
CFS1
CFS0
ECK HPDD HPFF FDS
External Clock. Default value: 0 (0: clock from internal oscillator; 1: clock from external pad) High Pass filter enabled for Direction Detection. Default value: 0 (0: filter bypassed; 1: filter enabled) High Pass filter enabled for Free-Fall. Default value: 0 (0: filter bypassed; 1: filter enabled) Filtered Data Selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter) High-pass filter Cut-off Frequency coefficient Selection (00: HPc = 512 01: HPc = 1024 10: HPc = 2048 11: HPc = 4096) Reserved. These bit are reserved for future enhancements. Best to be left to their default value (10 binary)
CFS1, CFS0
res
ECK bit selects whether the clock used in the core comes from internal oscillator or from external pad OSC_IN. In the latter case internal oscillator is switched off and the pin PullDown is disabled thus reducing power consumption. External clock must be in the range of 1.045 MHz +/- 10% and must have a duty cycle of 50%. HPDD bit permits to select either filtered or not filtered data to feed the Signal Processing (Direction Detection) block as described in Figure 11. When HPDD is set to `0' (default
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Registers Description
AN2381
mode) the data used to generate DD interrupt come directly from digital block or temperature compensation block while if HPDD is set to `1' the interrupt signals are based on High-Pass filtered data. Complete data flow is represented in Figure 11. HPFF bit allows to select between filtered or not filtered data to be processed by the Signal Processing (WakeUp or FreeFall) block as described in Figure 11. If HPFF is set `0' (default mode) data used to generate WU or FF interrupt come directly from digital block or temperature compensation block while if HPFF is set `1' the interrupt signals are based on High-Pass filtered data. Complete data flow is represented in Figure 11. FDS bit decides whether data stored in output registers are High Pass filtered or not. In default mode (FDS bit set to `0') signal are not filtered while it is possible to access data coming from HP filter setting FDS bit to `1'. Complete data flow is represented in Figure 11. CFS<1:0> bit select High-pass filter Cut-off Frequency coefficient. Increasing this number makes Cut-off Frequency (@-3dB) move to lower values.
The Cut-off Frequency behavior is described by the following equation:
0.318 O D R f C u t o f f = -------------- ------------- HPc 2
where HPc = 512, 1024, 2048, 4096 when CFS<1:0>= 00, 01, 10, 11 respectively and ODR represents the Output Data Rate selectable through the DF1, DF0 bits in CTRL_REG1. The figure below gives a representation of the possible transfer functions obtained modifying Output Data Rate and High Pass Filter coefficient (HPc). Figure 10. HP Filter Transfer Function
HP Filter frequency responce 0
-0.5
-1
|Amplitude| (dB)
-1.5 ODR = 40Hz; HP coeff.= 512 ODR = 40Hz; HP coeff.= 1024 ODR = 40Hz; HP coeff.= 2048 ODR = 40Hz; HP coeff.= 4096 ODR = 160Hz; HP coeff.= 512 ODR = 160Hz; HP coeff.= 1024 ODR = 160Hz; HP coeff.= 2048 OD -3dB R = 160Hz; HP coeff.= 4096 ODR = 640Hz; HP coeff.= 512 ODR = 640Hz; HP coeff.= 1024 ODR = 640Hz; HP coeff.= 2048 ODR = 640Hz; HP coeff.= 4096 ODR = 2560Hz; HP coeff.= 512 ODR = 2560Hz; HP coeff.= 1024 ODR = 2560Hz; HP coeff.= 2048 ODR = 2560Hz; HP coeff.= 4096 10
-2
-2
-2.5
-3
-3.5
-4 10
-1
10 Frequence (Hz)
0
10
1
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AN2381
Registers Description Figure 11 gives a representation of a output data path towards serial interfaces with its control signals. Figure 11. Block diagram of data output path
Digital Filter, Offset and Gain Adjust
0 Output reg 1 CTRL_REG3(FDS) 0 High Pass Filter HP_FILTER_RESET 1 DD CTRL_REG3(HPDD) Interrupt Generator (FF, WU, DD) FF 0 1 CTRL_REG3(HPFF) Regs Array
I2 C /S P I
FF_WU_SRC DD_SRC
Data Path
The data coming from Offset and Gain adjust block go directly to register array for reading when FDS is set to '0' (default value) Instead when the FDS bit in CTRL_REG3 is set to '1', the path that involves the use of the embedded HP filter is activated. HP filtered data can be selected for further processing by the Interrupt Generator block setting the desired values of HPDD and HPFF bit. Default value is `0' and corresponds to the use of non filtered data. The output of Interrupt Generator block is used to load FF_WU_SRC and DD_SRC registers.
5.3
5.3.1
Data and Status Registers
WHO_AM_I (0Fh)
Device identification register.
0 0 1 1 1 0 1 0
This register contains a device identifier which for LIS3LV02DL is set to 3Ah.
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Registers Description
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5.3.2
STATUS_REG (27h)
Data output status register.
ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA
ZYXOR
X, Y and Z axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: a new set of data has overwritten the previous ones) Z axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the Z-axis has overwritten the previous one) Y axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the Y-axis has overwritten the previous one) X axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the X-axis has overwritten the previous one) X, Y and Z axis new Data Available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) Z axis new Data Available. Default value: 0 (0: a new data for the Z-axis is not yet available; 1: a new data for the Z-axis is available) Y axis new Data Available. Default value: 0 (0: a new data for the Y-axis is not yet available; 1: a new data for the Y-axis is available) X axis new Data Available. Default value: 0 (0: a new data for the X-axis is not yet available; 1: a new data for the X-axis is available)
ZOR
YOR
XOR
ZYXDA
ZDA
YDA
XDA
ZYXOR is set to one whenever a new set of acceleration data is produced before completing the retrieval of the previous set. When this occurs, the content of at least one acceleration data register (i.e. OUTX_L, OUTX_H, OUTY_L, OUTY_H, OUTZ_L, OUTZ_H) has been overwritten unless BDU bit in CTRL_REG2 is `1'. ZYXOR is cleared when the upper parts (OUTX_H, OUTY_H, OUTZ_H) of the active channel registers are read. ZOR is set to 1 whenever a new acceleration sample related to the Z-axis is generated before the retrieval of the previous sample. When this occurs and the BDU bit in CTRL_REG2 is `0', the previous sample is overwritten. When BDU bit is set to `1' no update is performed until both upper and lower part of OUTZ register are read. ZOR is cleared anytime OUTZ_H register is read. YOR is set to 1 whenever a new acceleration sample related to the Y-axis is generated before the retrieval of the previous sample. When this occurs and the BDU bit in CTRL_REG2 is `0', the previous sample is overwritten. When BDU bit is set to `1' no update is performed until both upper and lower part of OUTY register are read. YOR is cleared anytime OUTY_H register is read. XOR is set to 1 whenever a new acceleration sample related to the X-axis is generated before the retrieval of the previous sample. When this occurs and the BDU bit in CTRL_REG2 is `0', the previous sample is overwritten. When BDU bit is set to `1' no update
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Registers Description is performed until both upper and lower part of OUTX register are read. XOR is cleared anytime OUTX_H register is read. The ZYXDA bit signals that a new sample for all the enabled channels is available. ZYXDA is cleared when the Most Significant part of all the enabled channels are read. ZDA is set to 1 whenever a new acceleration sample related to the Z-axis is available. ZDA is cleared anytime OUTZ_H register is read. In order to trigger, the ZDA bit requires the Z axis to be enabled (bit Zen=1 inside CTRL_REG1). YDA is set to 1 whenever a new acceleration sample related to the Y-axis is available. YDA is cleared anytime OUTY_H register is read. In order to trigger, the YDA bit requires the Y axis to be enabled (bit Yen=1 inside CTRL_REG1). XDA is set to 1 whenever a new acceleration sample related to the X-axis is available. XDA is cleared anytime OUTX_H register is read. In order to trigger, the XDA bit requires the X axis to be enabled (bit Xen=1 inside CTRL_REG1).
5.3.3
OUTX_L (28h)
X-axis output register, less significant bits.
XD7 XD7, XD0 XD6 XD5 XD4 XD3 XD2 XD1 XD0
X axis acceleration data LSb (bit BLE in CTRL_REG2 register set to `0')
In Big Endian Mode (bit BLE in CTRL_REG2 set to `1') the content of this register becomes the Most Significant part of acceleration data and depends by bit DAS in CTRL_REG2 register.
5.3.4
OUTX_H (29h)
X-axis output register, most significant bits. When reading the register in "12 bit right justified" mode (bit DAS in CTRL_REG2 register set to 0) the most significant bits (7:4) are replaced with XD11 (i.e. XD15-XD12=XD11, XD11, XD11, XD11).
XD15 XD15, XD8 XD14 XD13 XD12 XD11 XD10 XD9 XD8
X axis acceleration data MSb (bit BLE in CTRL_REG2 register set to `0')
In Big Endian Mode (bit BLE in CTRL_REG2 set to `1') the content of this register becomes the Less Significant part of acceleration data.
5.3.5
OUTY_L (2Ah)
Y-axis output register, less significant bits.
YD7 YD11, YD8 YD6 YD5 YD4 YD3 YD2 YD1 YD0
Y axis acceleration data LSb (bit BLE in CTRL_REG2 register set to `0')
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Registers Description
AN2381
In Big Endian Mode (bit BLE in CTRL_REG2 set to `1') the content of this register becomes the Most Significant part of acceleration data and depends by bit DAS in CTRL_REG2 register.
5.3.6
OUTY_H (2Bh)
Y-axis output register, most significant bits. When reading the register in "12 bit right justified" mode (bit DAS in A_IF_CTRL2 reg set to 0) the most significant bits (7:4) are replaced with YD11 (i.e. YD15-YD12=YD11, YD11, YD11, YD11).
YD15 YD15, YD8 YD14 YD13 YD12 YD11 YD10 YD9 YD8
Y axis acceleration data MSb (bit BLE in CTRL_REG2 register set to `0')
In Big Endian Mode (bit BLE in CTRL_REG2 set to `1') the content of this register becomes the Less Significant part of acceleration data.
5.3.7
OUTZ_L (2Ch)
Z-axis output register, less significant bits.
ZD7 ZD11, ZD8 ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0
Z axis acceleration data LSb (bit BLE in CTRL_REG2 register set to `0')
In Big Endian Mode (bit BLE in CTRL_REG2 set to `1') the content of this register becomes the Most Significant part of acceleration data and depends by bit DAS in CTRL_REG2 register.
5.3.8
OUTZ_H (2Dh)
Z-axis output register, most significant bits. When reading the register in "12 bit right justified" mode (bit DAS in A_IF_CTRL2 reg set to 0) the most significant bits (7:4) are replaced with ZD11 (i.e. ZD15-ZD12=ZD11, ZD11, ZD11, ZD11).
ZD15 ZD15, ZD8 ZD14 ZD13 ZD12 ZD11 ZD10 ZD9 ZD8
Z axis acceleration data MSb (bit BLE in CTRL_REG2 register set to `0')
In Big Endian Mode (bit BLE in CTRL_REG2 set to `1') the content of this register becomes the Less Significant part of acceleration data.
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Registers Description
5.4
Free-Fall and Wake-Up Registers
The following sections describes the registers that are involved in the generation of the interrupt signal associated to the inertial wake-up and free-fall events.
5.4.1
HP_FILTER_RESET (23h)
Dummy register. A read at this address set the content of the internal High-Pass filter to the actual X, Y and Z acceleration values.
X X X X X X X X
5.4.2
FF_WU_CFG (30h)
Free-fall and wake-up configuration register.
AOI LIR ZHIE ZLIE YHIE YLIE XHIE XLIE
AOI
And/Or combination of Interrupt events. Default value: 0 (0: OR combination of interrupt events; 1: AND combination of interrupt events) Latch Interrupt request into FF_WU_SRC register with the FF_WU_SRC register cleared by reading FF_WU_ACK register. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
LIR
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
AOI bit allows to select between Wake-Up (OR combination of interrupt events) and FreeFall (AND combination of interrupt events) detection LIR defines whether the configured interrupt event has to be latched by the device once it has happened. In order to clear the request and the related source reg (FF_WU_SRC) it is necessary to perform a reading at the dummy register FF_WU_ACK reg.
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Registers Description
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XHIE (YHIE, ZHIE) set an interrupt event to occur when the measured acceleration data on X (Y, Z) channel is higher than the threshold set in FF_WU_THS register. XLIE (YLIE, ZLIE) set an interrupt event to occur when the measured acceleration data on X (Y, Z) channel is lower than the threshold set in FF_WU_THS register. The threshold module which is used by the system to detect any free-fall or inertial wake-up event is defined by FF_WU_THS_H and FF_WU_THS_L registers and it is given by their concatenation FF_WU_THS_H & FF_WU_THS_L. The threshold value is expressed over 16 bit as an unsigned number and X, (Y, Z) high is true when the unsigned acceleration value of the X (Y, Z) channel is higher than FF_WU_THS_H & FF_WU_THS_L. Similarly, X, (Y, Z) low is true when the unsigned acceleration value of the X (Y, Z) channel is lower than FF_WU_THS_H & FF_WU_THS_L. Refer to Figure 12 for more details. Figure 12. FF_WU_CFG High and Low
+ Full Scale X (Y, Z) high Threshold module 0 g level Threshold module X (Y, Z) high - Full Scale Negative acceleration Positive acceleration
X (Y, Z) low
5.4.3
FF_WU_SRC (31h)
Free-fall and wake-up source register. Read only register.
x IA ZH ZL YH YL XH XL
IA
Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt event has been generated) Z High. Default value: 0 (0: no interrupt; 1: ZH event has occurred) Z Low. Default value: 0 (0: no interrupt; 1: ZL event has occurred) Y High. Default value: 0 (0: no interrupt; 1: YH event has occurred) Y Low. Default value: 0 (0: no interrupt; 1: YL event has occurred) X High. Default value: 0 (0: no interrupt; 1: XH event has occurred) X Low. Default value: 0 (0: no interrupt; 1: XL event has occurred)
ZH ZL YH YL XH XL
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Registers Description This register keeps track of the acceleration event which is being triggering (or has triggered, in case of LIR bit in FF_WU_SRC reg set to 1) the interrupt signal. In particular IA is equal to 1 when the combination of acceleration events specified in FF_WU_CFG register is true. This bit is used for the generation of the interrupt signal associated to the freefall/wake-up events (see Figure 17 for any additional detail). X, (Y, Z) high is true when the module of the acceleration value of the X (Y, Z) channel is higher than the preset threshold which is defined as the concatenation of FF_WU_THS_H & FF_WU_THS_L. Similarly, X, (Y, Z) low is true when the module of the acceleration value of the X (Y, Z) channel is lower than FF_WU_THS_H & FF_WU_THS_L. Refer to Figure 12 for more details.
5.4.4
FF_WU_ACK (32h)
Dummy register. A read at this address clears the FF_WU_SRC reg and the FF, WU interrupt if the latched option was chosen (LIR bit in FF_WU_CFG reg set to 1).
X X X X X X X X
5.4.5
FF_WU_THS_L (34h)
Free-Fall, Wake-Up threshold, less significant bits.
THS7 THS7, THS0 THS6 THS5 THS4 THS3 THS2 THS1 THS0
Free-fall / wake-up Threshold Lsb
5.4.6
FF_WU_THS_H (35h)
Free-Fall, Wake-Up threshold, most significant bits.
THS15 THS15, THS8 THS14 THS13 THS12 THS11 THS10 THS9 THS8
Free-fall / wake-up Threshold Msb
FF_WU_THS_H and FF_WU_THS_L registers define the threshold which is used by the system to detect any free-fall or inertial wake-up event. The threshold value is expressed over 16 bit as an unsigned number. In particular 7FFFh corresponds to full-scale acceleration (i.e. either 2g or 6g depending on the value of FS bit in CTRL_REG2).
5.4.7
FF_WU_DURATION (36h)
Set the minimum duration of the free-fall/wake-up event that must be recognized by the LIS3LV02DL
.
FWD7
FWD6
FWD5
FWD4
FWD3
FWD2
FWD1
FWD0
FWD7, FWD0
Free-fall / wake-up minimum duration threshold (default value 00h)
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Registers Description
AN2381
The number contained in the register represents the number of samples produced at the sampling rate set by DF1, DF0 bits in CTRL_REG1. Events having a duration shorter than the value specified in the FF_WU_DURATION register are filtered out by the device. A value of 00h in this register means that the interrupt is generated as soon as the free-fall/wake-up event configured in FF_WU_CFG reg occurs without waiting for any confirmation.
5.5
Direction-Detection Registers
The LIS3LV02DL allows the implementation of motion-controlled functions such as gaming and terminal control while requiring reduced computational power to the application controller. The following sections describes the functionality of the registers that are involved in the recognition of the direction in which the terminal has been tilted.
5.5.1
DD_CFG (38h)
Direction Detector configuration register.
IEND LIR ZHIE ZLIE YHIE YLIE XHIE XLIE
IEND
Interrupt enable on Direction change. Default value: 0 (0: disabled 1: interrupt signal enabled) Latch Interrupt request into DD_SRC register with the DD_SRC register cleared by reading DD_ACK register. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched) Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
LIR
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
IEND enables the generation of an interrupt signal when a change in DD_SRC reg occurs, i.e. when the tilt of terminal has changed with respect to the previous one.
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Registers Description LIR defines whether the current direction/tilt status has to be latched inside the DD_SRC register. In order to clear the content of the DD_SRC register and the related interrupt request (if enabled through the IEND bit) it is necessary to perform a reading at the dummy register DD_ACK. For any additional detail refer to Figure 17. XHIE (YHIE, ZHIE) configure the device to recognize whether the acceleration value along the X axis has exceeded the preset threshold module in the positive direction of the related acceleration axis. XLIE (YLIE, ZLIE) configure the device to recognize whether the acceleration value along the X axis has exceeded the preset threshold module in the negative direction of the related acceleration axis. In order to avoid false detections and/or bouncing produced for example by either spurious vibration or tremor, one inner/internal and one outer/external thresholds is defined. Both the thresholds are expressed over 16 bit as an unsigned number and are given respectively by the concatenation of DD_THSI_H & DD_THSI_L and DD_THSE_H & DD_THSE_L. Whenever the inner thresholds is greater than the outer one, the hysteresis region will be null and the threshold used to detect the tilt direction is DD_THSE_H & DD_THSE_L.
X, (Y, Z) acceleration data is considered high when the acceleration value of the X (Y, Z) channel is higher than the outer DD_THSE_H & DD_THSE_L threshold (i.e. acceleration exceeding the threshold in module with the terminal tilted in the positive acceleration direction). Similarly, X, (Y, Z) acceleration data is considered low when the acceleration value of the X (Y, Z) channel is lower than the outer DD_THSE_H & DD_THSE_L threshold (i.e. acceleration exceeding the threshold in module but terminal tilted in the negative acceleration direction). Both X (Y, Z) high and X (Y, Z) low in DD_SRC register are reset when the absolute acceleration data on X (Y, Z) channel is lower than the inner DD_THSI_H & DD_THSI_L threshold. Figure 13 gives a representation of acceleration area named "high", "low" and "reset" defined by thresholds written in DD_THSE and DD_THSI registers on a single acceleration axis. Figure 13. DD_CFG High and Low Description
+ Full Scale X (Y, Z) high Hysteresis Region Internal Threshold (DD_THSI) X (Y, Z) reset 0 g level Internal Threshold (DD_THSI) Hysteresis Region External Threshold (DD_THSE) X (Y, Z) low - Full Scale Negative acceleration External Threshold (DD_THSE) Positive acceleration
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Registers Description
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5.5.2
DD_SRC (39h)
Direction Detector source register.
x IA ZH ZL YH YL XH XL
IA
Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt event has been generated) Z High. Default value: 0 (0: no interrupt; 1: ZH event has occurred) Z Low. Default value: 0 (0: no interrupt; 1: ZL event has occurred) Y High. Default value: 0 (0: no interrupt; 1: YH event has occurred) Y Low. Default value: 0 (0: no interrupt; 1: YL event has occurred) X High. Default value: 0 (0: no interrupt; 1: XH event has occurred) X Low. Default value: 0 (0: no interrupt; 1: XL event has occurred)
ZH ZL YH YL XH XL
This register keeps track of the direction in which the device is being tilted. In particular IA is set to one when the tilt of terminal has changed with respect to the previous one. The axes directions that are enabled to set the IA bit to 1 are specified by DD_CFG register. This bit is used for the generation of the interrupt signal associated to the direction-detector (refer to Figure 13). X, (Y, Z) acceleration direction is considered high when the acceleration value of the X (Y, Z) channel is higher than the outer DD_THSE_H & DD_THSE_L threshold (i.e. acceleration exceeding the threshold in module with the terminal tilted in the positive acceleration direction). Similarly, X, (Y, Z) acceleration data is considered low when the acceleration value of the X (Y, Z) channel is lower than the outer DD_THSE_H & DD_THSE_L threshold (i.e. acceleration exceeding the threshold in module but terminal tilted in the negative acceleration direction). Both X (Y, Z) high and X (Y, Z) low bit in DD_SRC register are reset when the absolute acceleration data on X (Y, Z) channel is lower than the inner DD_THSI_H & DD_THSI_L threshold. Refer to reset zone in Figure 13. When the LIR bit of DD_CFG register is set to 1, the device stores the current direction/tilt status inside the DD_SRC register any time it has changed from the previous state. In order to refresh the content of the DD_SRC register and to any interrupt request it is necessary to perform a reading at the dummy register DD_ACK.
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AN2381
Registers Description
5.5.3
DD_ACK (3Ah)
Direction Detection Acknowledge, dummy register. A read at this address allows the refresh of the DD_SRC register and clears any DD interrupt signal.
x x x x x x x x
5.5.4
DD_THSI_L (3Ch)
Direction Detection Internal Threshold, less significant bits.
THSI7 THSI7, THSI0 THSI6 THSI5 THSI4 THSI3 THSI2 THSI1 THSI0
Direction detection Internal Threshold Lsb
5.5.5
DD_THSI_H (3Dh)
Direction Detection Internal Threshold, most significant bits.
THSI15 THSI14 THSI13 THSI12 THSI11 THSI10 THSI9 THSI8
THSI15, THSI8
Direction detection Internal Threshold Msb
The concatenation of DD_THSI_H and DD_THSI_L registers defines the inner/internal threshold which is used by the LIS3LV02DL device for direction-detection (refer to Figure 13). The threshold value is expressed over 16 bit as an unsigned number. In particular 7FFFh corresponds to full-scale acceleration (i.e. either 2g or 6g depending on the value of FS bit in CTRL_REG2). In case no hysteresis is desired, the inner and outer thresholds must be equal. The inner threshold should be lower than or equal to the outer one. Whenever the inner thresholds is greater than the outer one, the hysteresis region will be null and the threshold used to detect the tilt direction is DD_THSE_H & DD_THSE_L only.
5.5.6
DD_THSE_L (3Eh)
Direction Detection External Threshold, less significant bits.
THSE7 THSE6 THSE5 THSE4 THSE3 THSE2 THSE1 THSE0
THSE7, THSE0
Direction detection External Threshold Lsb
5.5.7
DD_THSE_H (3Fh)
Direction Detection External Threshold, most significant bits.
THSE15 THSE14 THSE13 THSE12 THSE11 THSE10 THSE9 THSE8
THSE15, THSE8
Direction detection External Threshold Msb
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Registers Description
AN2381
The concatenation of DD_THSE_H and DD_THSE_L registers defines the outer/external threshold which is used by the LIS3LV02DL device for direction-detection (see Figure 13). The threshold value is expressed over 16 bit as an unsigned number. In particular 7FFFh corresponds to full-scale acceleration (i.e. either 2g or 6g depending on the value of FS bit in CTRL_REG2). In case no hysteresis is desired, the inner and outer threshold must be equal. The inner threshold should be lower than or equal to the outer one. Whenever the inner thresholds is greater than the outer one, the hysteresis region will be null and the threshold used to detect the tilt direction is DD_THSE_H & DD_THSE_L only.
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AN2381
Application information
6
6.1
Application information
Start-up sequence
Once the device is powered-up it automatically downloads the calibration coefficients from the embedded flash to the internal registers. When the boot procedure is completed, i.e. approximately after 5 milli-seconds, the device automatically enters power-down mode. To turn-on the device and gather acceleration data it is necessary to write C7h inside CTRL_REG1. With this command the three acceleration channels (i.e. X, Y and Z axis) are enabled.
6.2
6.2.1
Reading acceleration data
Using the Status Register
The device is provided with a STATUS_REG which should be polled to check when a new set of data is available. The reading procedure should be the following:
1 2 3 4 5 6 7 8 9 10 11 read STATUS_REG if STATUS_REG(3)=0 then goto 1 if STATUS_REG(7)=1 then some data have been overwritten read OUTX_L read OUTX_H read OUTY_L read OUTY_H read OUTZ_L read OUTZ_H data processing goto 1
The check performed at step 3 allows to understand whether the reading rate is adequate compared to the data production rate. In case one or more acceleration samples have been overwritten by new data because of a reading rate too slow, the bit STATUS_REG(7) will be set to 1. The overrun bit are automatically cleared when all the data present inside the device have been read and new data have not been produced in the meanwhile.
6.2.2
Using the Data-Ready Signal
The device may be configured to have one HW signal (RDY, pin #6) to determinate when a new set of measurement data is available for reading. This signal is represented by STATUS_REG(3) content. The signal is active high (data available) and it returns to logic zero when the higher part of the data of all the enabled channels have been read. To use the RDY signal, it is necessary to set the CTRL_REG2 to xxxx 01xx.
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Application information
AN2381
6.2.3
Using the Block Data Update feature
In case the reading of the acceleration data is particularly slow and it can not be (or it is not required to have it) synchronized with either the XYZDA bit present inside the STATUS_REG or with the RDY signal, it is strongly recommended to set the BDU (Block Data Update) bit in CTRL_REG2 to 1. This feature avoids the reading of values (most significant and least significant parts of the acceleration data) related to different samples. In particular, when the BDU is activated, the data registers related to each channel always contain the most recent acceleration data produced by the device but, in case the reading of a given pair (i.e. OUTX_H and OUTX_L, OUTY_H and OUTY_L, OUTZ_H and OUTZ_L) is initiated, the refresh for that pair is blocked until both MSB and LSB parts of the data are read.
6.3
Understanding acceleration data
The measured acceleration data are sent into OUTX_H, OUTX_L, OUTY_H, OUTY_L, OUTZ_H and OUTZ_L registers. Those registers contain respectively the most significant part and the least significant part of the acceleration signals acting on the X, Y and Z axes. The complete acceleration data for the X (Y, Z) channel is given by the concatenation OUTX_H & OUTX_L (OUTY_H & OUTY_L, OUTZ_H & OUTZ_L) and it is expressed as a 2's complement number.
6.3.1
Data Alignment: 12 and 16 bit Modes
In 12 bit mode (bit DAS in CTRL_REG2 set to 0 -default configuration-) the acceleration data are right justified and the most significant bits represent a replica of the sign bit while in 16 bit mode (bit DAS in CTRL_REG2 set to 1) the data produced by the device are left justified. In the latter mode, a few of the least significant bit stored inside OUTX_L, OUTY_L and OUTZ_L registers might assume random values accordingly to the SNR performances of the device.
6.3.2
Big-Little Endian Selection
The LIS3LV02DL allows to swap the content of the lower and the upper part of the acceleration registers (i.e. OUTX_H with OUTX_L) so to be compliant with both little-endian and big-endian data representations. "Little Endian" means that the low-order byte of the number is stored in memory at the lowest address, and the high-order byte at the highest address. (The little end comes first). This mode corresponds to bit BLE in CTRL_REG2 reset to 0 -default configuration-. On the contrary "Big Endian" means that the high-order byte of the number is stored in memory at the lowest address, and the low-order byte at the highest address. In order to activate big-endian mode it is necessary to set bit DAS in CTRL_REG2 to 1.
6.3.3
Example of Acceleration Data
The table below provides few basic examples of the data that will be read in the dataregisters when the device is subject to a given acceleration. The values listed in the table are given under the hypothesis of perfect device calibration (i.e no offset, no gain error, ....) and show practically the effect of DAS and BLE bit.
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AN2381 Table 6.
Application information Output Data Registers Content vs. Acceleration (FS= 2g)
DAS=0; BLE=0 Acceleration Values 28h 0g 350 mg 1g -350 mg -1g 00h 66h 00h 9Ah 00h 29h 00h 01h 04h FEh FCh 28h 00h 01h 04h FEh FCh DAS=0; BLE=1 DAS=1; BLE=0 DAS=1; BLE=1
Register Address 29h 00h 66h 00h 9Ah 00h 28h 0xh 6xh 0xh Axh 0xh 29h 00h 16h 40h E9h C0h 28h 00h 16h 40h E9h C0h 29h 0xh 6xh 0xh Axh 0xh
6.4
Interrupt generation description
The LIS3LV02DL can provide an interrupt signal and offers several possibilities to personalize this signal. The registers involved in the interrupt generation behavior are CTRL_REG2, FF_WU_CFG, FF_WU_THS, FF_WU_DURATION, DD_CFG, DD_THSI, DD_THSE. In this section a brief description of the capability of the interrupt generation is provided. The LIS3LV02DL interrupt signal can behave as Free-Fall, Wake-Up and/or Direction Detector. Whenever an interrupt condition is verified the interrupt signal goes high and reading FF_WU_SRC and DD_SRC registers it is possible to understand which condition happened. Free-Fall signal (FF) and Wake-Up signal (WU) interrupt generation block is represented by the diagram below: Figure 14. Free-Fall, Wake-Up Interrupt Generator
THS reg |b|>a? Accel_X |b|>a? Accel_Y |b|>a? Accel_Z Z_en Y_en FF FF_WU_CFG(AOI)
1
WU X_en
0
FF or WU interrupt generation is selected through AOI bit in FF_WU_CFG register (address 30 hexadecimal). If AOI bit is `0' signals coming from comparators are put in logical or. Depending on values written in FF_WU_CFG register every time the value of almost one of the enabled axes exceeds the threshold written in module in FF_WU_THS registers a FF, WU interrupt is generated. Otherwise if AOI bit is `1' signals coming from comparators are going into a "NAND" port. In this case an interrupt signal is generated only if all the enabled axes are passing the threshold written in FF_WU_THS registers.
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Application information
AN2381
FF_WU_CFG(LIR) bit permits to decide if the interrupt request has to be latched or not. If LIR bit is `0' (default value) interrupt signal goes high when the interrupt condition is satisfied and comes back low immediately if the interrupt condition is no more verified. Otherwise if LIR bit is `1' whenever a interrupt condition is applied the interrupt signal remains high even if the condition comes back to non-interrupt status until a reading to FF_WU_ACK register is performed. The remaining bits of FF_WU_CFG register permits to decide on which axis the interrupt decision has to be performed and on which direction the threshold has to be passed to generate the interrupt request. Figure 15 is a representation of Direction Detector Interrupt Generator for one of the axes. The data coming from comparators are compared with the one of the previous acquisition. If a difference is found it means that the threshold written in the DD_THS registers was exceeded and an interrupt signal is generated. If different values are used for DD_THSE and DD_THSI registers it is possible to introduce an hysteresis in the interrupt generation. The difference between WU and DD signals is that the first one gives information if the device reads statically an acceleration in a chosen range while the second one provides an information on the device movement from a position. Reading Direction Detector Source Register is then possible to understand in which direction and in which versus the movement has happened. Figure 15. Direction Detector Interrupt Generator for X axis
DD_THSEreg b>a? Accel_X DD_THSI reg |b|
Memory cell XH_en
b<-a?
Memory cell XL_en
These Interrupt generator blocks can be combined with the embedded High Pass filter in order to obtain further feature. Fur thermore, as described in Figure 17, FF_WU and DD can be used together to generate an interrupt signal that is the logic "OR" of the two interrupts.
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AN2381
Application information
6.5
6.5.1
Inertial wake-up
HP filter bypassed
This paragraph provides a basic algorithm which shows the practical use of the inertial wake-up feature. In particular, with the code below, the device is configured to recognize when the absolute acceleration along either X or Y axis exceeds a preset threshold (100mg used in the example). The event which triggers the interrupt is latched inside the device and its occurrence is signalled through the usage of the RDY/INT pin.
1 2 3 4 5 6 7 8 9 10 11 12 write C7h into CTRL_REG1 write 08h into CTRL_REG2 write 08h into CTRL_REG3 write 60h into FF_WU_THS_L register write 06h into FF_WU_THS_H register write 00h into FF_WU_DURATION register write 4Ah into FF_WU_CFG poll RDY/INT pad; if RDY/INT=0 then goto 8 read FF_WU_SRC register (Wake-up event has occurred; insert your code here) read FF_WU_ACK register goto 8 // Turn on the sensor and set DF=512 // Enables interrupt generation // Set CTRL_REG3 to its default state // Set the lower part of wake-up threshold // Set the higher part of wake-up threshold // No filtering/confirmation on the event // Configure desired wake-up event // Poll RDY/INT pin waiting for the // wake-up event // Return the event that has triggered the // interrupt // Event handling // Clear interrupt request
6.5.2
Using the HP filter
The code provided below gives a basic routine which shows the practical use of the inertial wake-up feature performed onto high-pass filtered data. In particular the device is configured to recognize when the high-frequency component of the acceleration applied along either X, Y or Z axis exceeds a preset threshold (100mg used in the example). The event which triggers the interrupt is latched inside the device and its occurrence is signalled through the usage of the RDY/INT pin.
1 2 3 4 5 6 write C7h into CTRL_REG1 write 08h into CTRL_REG2 write 28h into CTRL_REG3 write 60h into FF_WU_THS_L register write 06h into FF_WU_THS_H register write 00h into FF_WU_DURATION register // Turn on the sensor and set DF=512 // Enables interrupt generation // Enable the HP filter and force HPc=512 // Set the lower part of wake-up threshold // Set the higher part of wake-up threshold // No filtering/confirmation on the event
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Application information
AN2381
7 8 9 10 11 12 13 14
read HP_FILTER_RESET register write 6Ah into FF_WU_CFG poll RDY/INT pad; if RDY/INT=0 then goto 9 (Wake-up event has occurred; insert your code here) read FF_WU_SRC register (Inser t your code here) read FF_WU_ACK register goto 9
// Dummy read to force the HP filter to // actual acceleration value // (i.e. set reference acceleration/tilt value) // Configure desired wake-up event // Poll RDY/INT pin waiting for the // wake-up event // Event handling // Return the event that has triggered the // interrupt // Event handling // Clear interrupt request
At step 7, a dummy read at HP_FILTER_RESET register is performed to set the current/reference acceleration/tilt state against which the device performed the threshold comparison. This read may be performed any time it is required to set the orientation/tilt of the device as a reference state without waiting for the filter to settle.
6.6
Free-Fall detection
This paragraph provides the basics for the use of the free-fall detection feature. In particular the SW routine that configures the device to detect free-fall events and to signal them is the following:
1 2 3 4 5 6 7 8 9 10 11 write D7h into CTRL_REG1 write 08h into CTRL_REG2 write 08h into CTRL_REG3 write 60h into FF_WU_THS_L register write 16h into FF_WU_THS_H register write 05h into FF_WU_DURATION register write D5h into FF_WU_CFG poll RDY/INT pad; if RDY/INT=0 then goto 8 // Turn on the sensor and set DF=128 // Enables interrupt generation // Set CTRL_REG3 to its default state // Set the lower part of free-fall threshold // Set the higher part of free-fall threshold // Set minimum event duration // Configure free-fall recognition and latch // interrupt request // Poll RDY/INT pin waiting for the free-fall // event
(Free-fall event has occurred; insert your // Event handling code here) read FF_WU_ACK register goto 8 // Clear interrupt request
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AN2381
Application information The code sample exploits a threshold set at 350mg for free-fall recognition and the event is notified by the hardware signal RDY/INT. At step 6, the FF_WU_DURATION register is configured so to ignore events that are shorter than 5/DR=5/160~30msec (DR=data rate; see Table 7.) in order to avoid false detections. Once the free-fall event has occurred, a dummy read at FF_WU_ACK reg clears the request and the device is ready to recognize other events.
6.7
Direction detection
The code disclosed below illustrates the ability of the LIS3LV02DL device to recognize in which direction it has been tilted and to flag a change in its orientation/tilt with respect to the previous state through the hardware RDY/INT signal. In the example below the device is configured to detect tilt which exceed 260mg (set as external/outer threshold), while the internal/inner threshold is set, as an example, to 150mg.
1 2 3 4 5 6 7 8 write C7h into CTRL_REG1 write 08h into CTRL_REG2 write 4Bh into CTRL_REG3 write A3h into DD_THSE_L register write 10h into DD_THSE_H register write 99h into DD_THSI_L register write 09h into DD_THSI_H register read HP_FILTER_RESET register // Turn on the sensor and set DF=512 // Enables interrupt generation // Enable the HP filter and force HPc=4096 // Set the lower part of outer threshold // Set the higher part of outer threshold // Set the lower part of inner threshold // Set the higher part of inner threshold // Dummy read to force the HP filter to // actual acceleration value // (i.e. set reference acceleration/tilt value) // Configure direction detection along // X and Y axes // Poll RDY/INT pin waiting for a direction // change event // Event handling // Return the direction in which the tilt // has occurred // Event handling // Clear interrupt request (on direction // change)
9 10 11 12 13 14 15
write CFh into DD_CFG register poll RDY/INT pad; if RDY/INT=0 then goto 10 (Direction/tilt has changed; insert your code here) read DD_SRC register (Inser t your code here) read DD_ACK register goto 10
At step 8, a dummy read at HP_FILTER_RESET register is performed to set the current acceleration/tilt as a reference state value for threshold comparison. This read may be performed any time it is required to set the orientation/tilt of the device as a reference state without waiting for the filter to settle.
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Application information
AN2381
6.8
Output data rate selection and reading timing
The output data rate is user selectable through Decimation Factor Control bit (DF1, DF0) stored in CTRL_REG1 (20h) register. At power-on-reset DF1, DF0 are reset to 0 thus providing a default decimation factor set to 512. The selectable decimation factor are given in table below together with the output data rate. Table 7.
DF1, DF0 00 01 10 11
Output data rate
Decimation Factor 512 128 32 8 Output data rate 40 Hz 160 Hz 640 Hz 2560 Hz Digital Filter cut-off freq. (-3dB) 10 Hz 42 Hz 168 Hz 675 Hz
The output data rate precision is related to internal oscillator or to external clock precision and an error of +/- 10% should be taken in account. A minimum reading period 150 s shorter than the output data rate period is defined not to loose any data produced. During this time period the reading of the data must be performed and DataReady signal can be used as a trigger to begin the reading sequence. At the end of the complete sequence DataReady signal goes down and the following rise edge advise that new data are available. If this minimum reading frequency is not observed it is possible to loose some data and the DataReady signal have no more the meaning of a trigger signal. The status register can be used to infer if an overrun happened. Figure 16. Reading Timing T0 T1
DataReady
T2
New data available
Table 8.
Time T0 T1 T2
Timing Value to Avoid Loosing the Data
Description Data rate Reading period New data generation 150s Min 350s Typ Max 25 ms T0-T2
6.9
Data Ready vs. Interrupt Signal
The device is provided with a pin which can be activated to generate either the data-ready or the interrupt signal. The functionality of the pin is selected acting on bit IEN and DRDY of CTRL_REG2 accordingly to the block diagram given in Figure 17.
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AN2381
Application information In particular the DataReady signal, stored in STATUS_REG(3), which indicates when a new set of acceleration data is ready, is made available by setting DRDY bit to 1 and IEN bit to 0, while the interrupt signal is carried out when IEN bit is set to 1. Being the pad shared for the both DataReady and Interrupt, one signal at a time may be generated by the device. In case both DRDY and IEN are set to 1, the pad will generate the Interrupt signal which is given an higher priority. Figure 17. Interrupt and DataReady Signal Generation Block Diagram
Interrupt Generator (FF, WU, DD)
ODR Clock
0
0 1
DataReady DataReady signal
Signal
Generator
CTRL_REG2(DRDY) 0
Free-Fall, Wake-Up Interrupt Generator
Counter ff_wu_duration
IA (FF_WU_SRC)
Latch
FF_WU_CFG(LIR)
1 Interrupt signal
0 1
to RDY/INT Pad
Direction Detector IA (DD_SRC) Interrupt Generator Latch
DD_CFG(LIR)
0 0
0 1
CTRL_REG2(IEN)
1
DD_CFG(IEND)
In particular data-ready (RDY) signal rise to 1 when a new set of acceleration data has been generated and it is available for reading. The signal is reset after all the enabled channels are read through the serial interface. Figure 18. Data Ready Signal
ACCEL DATA Accel. Sample #(N) Accel. Sample #(N+1)
RDY
DATA READ X Y Z X Y Z
6.10
Using the external clock
The device provides the capability to drive the internal circuitry through an external clock. In order to switch to the external clock it is necessary to set to 1 the ECK bit stored inside CTRL_REG3. The external clock must have a frequency of 1.045 MHZ (+/-10%) and a duty cycle of 50%.
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Revision history
AN2381
7
Revision history
Table 9.
Date 15-Jun-2006
Document revision history
Revision 1 Initial release. Changes
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AN2381
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