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ST7538Q FSK powerline transceiver demonstration kit description

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AN1714 Application note
ST7538Q FSK powerline transceiver demonstration kit description
Introduction
The advantages in the implementation of a communication network using the same electrical network that supplies all the elements of the network are evident. In the presence of new wideband LANs using an RF system, for example Bluetooth, a narrowband communication system using the mains has considerable advantages also. It is widely accepted that in residential or industrial areas, in parallel to a wideband network for audio/video streaming and Internet, having a narrowband LAN is useful to carry simple information such as measurements, commands to actuators, system controls and so on. Many applications can be covered by a narrowband communication system in a residential structure, outside the house or in industrial applications (see Figure 1 below). Figure 1. Typical powerline modem applications scenario

For example in houses or commercial buildings possible applications are power management, lighting control, heating or cooling system management, remote control of appliances (by internet or telephone), and control of alarm systems. Considering external applications, the main areas concern communication with meters, in particular automatic measuring and remote control, prepaid supply systems, meter or inhome remote displays. Another relevant industrial segment could be street lighting management.

February 2008

Rev 4

1/46
www.st.com

Contents

AN1714

Contents
1 Powerline communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 The electrical network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1 1.1.2 1.1.3 1.1.4 Impedance of powerlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical connection losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Standing waves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2

ST7538Q FSK powerline transceiver description . . . . . . . . . . . . . . . . . . . . 9

2

Demonstration board for ST7538Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Signal coupling interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1 2.2.2 2.2.3 Transmitting section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Receiving section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Voltage regulation-current protection loops . . . . . . . . . . . . . . . . . . . . . . 21

2.3

Board power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.1 2.3.2 L6590 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ST7538Q power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.4 2.5 2.6 2.7

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Burst and surge protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ST7 microcontroller and RS232 interface . . . . . . . . . . . . . . . . . . . . . . . . 30
2.6.1 Modem / microcontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3

Demonstration board characterization . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1 3.2 3.3 Conducted disturbance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Narrowband conducted interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4

Design ideas for auxiliary blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1 Zero-crossing detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Appendix A Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2 ST7538Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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Contents

4.3 4.4 4.5

L6590 integrated power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 ST7 microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Surge and burst protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5 6

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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List of figures

AN1714

List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Typical powerline modem applications scenario. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Mains signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Aggregate European powerline impedance (by Malack and Engstrom). . . . . . . . . . . . . . . . 7 Voltage spectra of a 100 W light dimmer, a notebook PC, a desktop PC, a CFL lamp, a TLE lamp, all working with a 50 Hz/~220 V supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FSK modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ST7538Q transceiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ST7538Q demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Demonstration board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Demonstration board schematic: microcontroller and PC interface . . . . . . . . . . . . . . . . . . 12 Demonstration board schematic: line coupling interface and power supply . . . . . . . . . . . . 13 Demonstration board ST7538Q powerline interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Demonstration board ST7538Q transmission coupling circuit . . . . . . . . . . . . . . . . . . . . . . 15 Simplified schematic of the transmission filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Simulated characteristics of the transmission coupling filter. . . . . . . . . . . . . . . . . . . . . . . . 17 Coupling circuit with a 2nd order band pass butterworth. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Demonstration board ST7538Q receiving circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Measured filtering characteristic of the demonstration board at the RAI pin in receive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Powerline output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Voltage regulation and current protection components . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Voltage regulation/current protection loop logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Current protection loop characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Voltage regulation and current protection feedback signals . . . . . . . . . . . . . . . . . . . . . . . . 24 Power supply EMC disturbances filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Noise generation in resistive supply or ground path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 A recommended oscillator section layout for noise shielding . . . . . . . . . . . . . . . . . . . . . . . 28 Common mode and differential mode spikes example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Microcontroller/RS232 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ST7538Q / microcontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Conducted disturbance setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Output signal spectrum, channel 132.5 kHz, mains 220 V~, fixed tone . . . . . . . . . . . . . . . 38 Output signal spectrum, channel 132.5 kHz, mains 220 V~, random sequence . . . . . . . . 38 Output signal spectrum, channel 132.5 kHz, mains 110 V~, random sequence . . . . . . . . 39 Output signal spectrum, channel 110 kHz, mains 220 V~, random sequence . . . . . . . . . . 39 Narrowband conducted interferences setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Signal/noise ratio for the 132.5 kHz channel, signal level 85 dBuV . . . . . . . . . . . . . . . . . . 40 Signal/noise ratio for the 132.5 kHz channel, signal level 85 dBuV, mains 110 V~ . . . . . . 41 Signal/noise ratio for the 110 kHz channel, signal level 91 dBuV. . . . . . . . . . . . . . . . . . . . 41 Output board impedance measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Output demonstration board impedances (CN1) in receiving condition . . . . . . . . . . . . . . . 42 Output demonstration board impedances (CN1) in transmitting condition . . . . . . . . . . . . . 42 Zero-crossing coupling circuit, nonisolated solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Zero-crossing coupling circuit, isolated solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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AN1714

Powerline communication

1

Powerline communication
Although the concepts of power line communication and home automation, as well as the development of different devices dedicated for power line communication, have been present for several years, the market segment for this kind of application has only recently been growing. The three main factors that have contributed up to now to the field of the powerline communication are: a) b) c) The slow development of international norms and standards Some technical constraints related to the electrical network General consideration of costs

The first point concerns standards and norms. A general consideration in an open communication system is to have mandatory rules and guidelines to guarantee that every node, whatever the manufacturer, does not compromise the characteristics of the entire network and the performance of the communication system. For residential products this aspect is quite relevant considering the presence of many different appliances and manufacturers, and also the concern for a common language (the protocol) which is mandatory. In 2002 the CENELEC (European Committee for Electrotechnical Standardizations) published or updated a series of regulations about communication on low-voltage electrical installations. We refer in particular to the EN50065-1, concerning general requirements, frequency bands and electromagnetic disturbances; the EN50065-4-2 about the low-voltage decoupling filter and safety requirements; and the EN50065-7 about the impedance of the devices. A preliminary version (1999) of the EN50065-2-1 about immunity requirements is also available. There has been a certain alignment among the appliance manufacturers on the EHS (European Home System) protocols, even if a lot of customized protocols are present, mainly in proprietary mains. More information on EHS protocol is available in the EHS booklet. The second critical consideration concerns the technical problems regarding the specific topology of the electrical network. Figure 2 shows what happens to a signal transmitted on an electrical network. For several reasons that are listed in the next paragraph (low impedance, different kind of disturbances, etc.) the received FSK signal has a very low level and it is mixed with a great level of noise.

5/46

Powerline communication Figure 2. Mains signals

AN1714

MAINS Rx
ST ST 7538

Tx
ST 7538

Received Signal

Transmitted Signal

f fc

f fc

f

The aspects of noise and low impedance are more critical in a residential house where many different appliances are present. Every entity of the network has to be able to manage reliable communication also under these critical conditions. To achieve this goal all aspects of the application design have to be to carefully considered, from the coupling interface to the power management, from the type of microprocessor to the powerline transceiver, as well as considering their mutual influences. Last but not least, we must consider the economic point of view. It isn't a simple calculation of the node cost with respect to an equivalent wireline or wireless solution, but a consideration of other aspects such as the installation and configuration cost of the entire network. Another economic issue that has to be considered is the power consumption of a single communication node. The power consumption of each communication unit has to be lower as possible because every unit must always stay on ready to receive commands from a remote transmitter. This constraint is even more relevant in applications with a huge number of nodes. Consider for example the control of a street lighting system with thousands of lamps or a metering system with several thousands of electricity meters. The ST7538Q has been designed considering all issues previously listed. With this device it is possible to obtain highly efficient and reliable applications for powerline communication, characterized by low power consumption, low cost, and compliance with the main norms and protocol currently in place.

1.1

The electrical network
The communication medium consists of everything connected to power outlets. This includes house wiring in the walls of the building, appliance wiring, and the appliances themselves, the service panel, the triplex wire connecting the service panel to the distribution transformer and the distribution transformer itself. Since distribution transformers usually serve more than one residence, the loads and wiring of all residences connected to the same transformer must be included.

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AN1714

Powerline communication

1.1.1

Impedance of powerlines
A powerline has very variable impedance depending on several factors such as its configuration (star connection, ring connection) or the number of entities linked. Extensive data on this subject has been published by Malack and Engstrom of IBM (Electromagnetic Compatibility Laboratory), who measured the RF impedance of 86 commercial AC power distribution systems in six European countries (see Figure 3). These measurements show that the impedance of the residential power circuits increases with frequency and is in the range from about 1.5 to 8 at 100 kHz. It appears that this impedance is determined by two parameters - the loads connected to the network and the impedance of the distribution transformer. Recently a third element influences the impedance of the powerline, in particular in residential networks. It is represented by the EMI filters mounted in the last generation of home appliances (refrigerators, washing machines, television sets, stereos). Wiring seems to have a relatively small effect. The impedance is usually inductive. For typical resistive loads, signal attenuation is expected to be from 2 to 50 dB at 150 kHz depending on the distribution transformer used and the size of the loads. Moreover, it may be possible for capacitive loads to resonate with the inductance of the distribution transformer and cause the signal attenuation to vary wildly with frequency. For the compliance tests the normative EN50065 use two artificial mains networks conforming to sub clause 11.2 of CISPR 16-1:1993. Measurements on real networks have shown that this artificial network does not truly represent practical network impedance. To better evaluate the performance of a real signaling system, an adaptive network must be used in conjunction with the CISPR 16-1 artificial network. The design of the adaptive circuit is included in the informative annex F of EN50065-1 (revision 2001). Figure 3. Aggregate European powerline impedance (by Malack and Engstrom)
IMPEDANCE MAGNITUDE (OHM)
1000.0

100.0

10.0 MAXIMUM MEAN MINIMUM 0.1 0.04

1.0

0.08

0.1 0

0 .3 0

0 .7 5

2 .1 0

5.00

15.00

30.00

FREQUENCY (MHz)

1.1.2

Noise
Appliances connected to the same transformer secondary to which the powerline carrier system is connected cause the principal source of noise. The primary sources of noise are Triacs used in light dimmers, universal motors, switching power supplies used in small and portable appliances and fluorescent lamps.

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Powerline communication

AN1714

Triacs generate noise synchronous with the 50 Hz power signal and this noise appears as harmonics of 50 Hz. Universal motors found in mixers or drills also create noise, but it is not as strong as light dimmer noise, and not generally synchronous with 50 Hz. Fur thermore, light dimmers are often left on for long periods of time whereas universal motors are used intermittently. In the last years two other sources of strong noise have been introduced in the electrical network. They are Compact Fluorescent Lamps (CFL) and the switching power supplies of rechargeable battery (for example notebook PCs) or small appliances. In many cases they have a working frequency or some harmonics in the range of the powerline communication band (from 10 kHz to 150 kHz). Of course the presence of continuous tones exactly at communication channel frequency can affect the reliability of communication. The Figure 4 shows some of the noise sources we refer to. The measurement setup consists of an insulation transformer with a VARIAC, a spectrum analyzer HP4395A coupled by a high voltage capacitor (1F) and a 2 mH transformer (1:1). Figure 4. Voltage spectra of a 100 W light dimmer, a notebook PC, a desktop PC, a CFL lamp, a TLE lamp, all working with a 50 Hz/~220 V supply
dBuV 110.0

90.0

70.0

50.0

30.0

10.0

Background CFL 11W Desktop PC Dimmer 100W TLE 22W Notebook PC 1.00E+04

1.00E+03

Hz

1.00E+05

1.00E+06

1.1.3

Typical connection losses
The transmitting range of a home automation system depends on the physical topology of the electric power distribution network inside the building where the system is installed. Different connection losses can be measured. For communication nodes connected to the same branch circuit from transmitter to receiver a typical connection loss is about 10-15 dB. If transmitter and receiver are in different branches of the circuit, separated for example by a service panel, there is an additional attenuation of 10-20 dB. In some worst-case conditions (socket with very low impedance) the attenuation of the transmitted signal can reach a value of 50-60 db.

1.1.4

Standing waves
Standing wave effects begin to occur when the physical dimensions of the communication medium are similar to about one-eighth of a wavelength, which are about 375 and 250

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AN1714

Powerline communication meters at 100 and 150 kHz respectively. Primarily the length of the triplex wire connecting the residences to the distribution transformer determines the length of the communication path on the secondary side of the power distribution system. Usually, several residences use the same distribution transformer. It would be rare that a linear run of this wiring would exceed 250 meters in length although the total length of branches might occasionally exceed 250 meters. Thus standing wave effects would be rare at frequencies below 150 kHz for residential wiring.

1.2

ST7538Q FSK powerline transceiver description
The ST7538Q transceiver performs a half-duplex communication over the powerline network using Frequency Shift Keying (FSK) modulation. The FSK modulation technique translates a digital signal into a sinusoidal signal that can have two different frequency values, one for the high logic level of the digital signal (fH), the second one for the low level (fL), as depicted in Figure 5. Figure 5. FSK modulation

The average value of the two tones is the carrier frequency (fC). The difference or distance between the two frequencies is a function of the baud-rate (BAUD) of the digital signal (the number of symbols transmitted in one second) and of the deviation (dev). The relationship is: Equation 1
fH fL = B A U D d e v

The ST7538Q can be programmed to communicate using eight different frequency channels (60, 66, 72, 76, 82.05, 86, 110 and 132.5 kHz), four baud rates (600, 1200, 2400 and 4800 symbols per second) and two frequency deviations (1 and 0.5). The device operates from a 7.5 to 12.5 V single supply voltage (PAVcc) and integrates a differential-output PowerLine Interface (PLI) stage and two linear regulators providing 5 V (VDC) and 3.3 V (DVdd). Many auxiliary functions are integrated. The transmission section includes automatic control on PLI output voltage and current, programmable timeout function and thermal shutdown. The reception section includes automatic input level control, carrier/preamble detection and band-in-use signaling. Additional features are included, such as a watchdog timer, zero-crossing detector, internal oscillator and a general purpose op-amp. The serial interface (configurable as UART or SPI) allows interfacing to a host microcontroller, intended to manage the communication protocol. A reset output (RSTO) and a programmable 4-8-16 MHz clock (MCLK) can be provided to the microcontroller to simplify the application.

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Powerline communication

AN1714

Communication on the powerline can be either synchronous or asynchronous with the data clock (CLR/T) provided by the transceiver at the programmed baud rate. When in Transmission mode (i.e. RxTx line at low level), the ST7538Q transceiver samples the data on the TxD line, generating an FSK modulated signal on the ATO pin. The same signal is fed into the differential power amplifier to get four times the voltage swing and a current capability up to 370 mA rms. When in Reception mode (i.e. RxTx line at high level), an incoming signal at the RAI line is demodulated and converted in a digital bit stream on the RxD pin. The internal Control Register, which contains the operating parameters of the ST7538Q transceiver, can be programmed only using the SPI interface. The Control Register settings include the Header Recognition and Frame Length Count functions, which can be used to apply byte and frame synchronization to the received messages. Figure 6. ST7538Q transceiver block diagram

For a more detailed and complete description of the ST7538Q device please refer to the product datasheet.

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AN1714

Demonstration board for ST7538Q

2
2.1

Demonstration board for ST7538Q
Main features
The ST7538Q demonstration board implements in a two layer PCB a complete powerline communication node, including the powerline coupling circuits, a power supply section, a microcontroller and a RS232 serial interface to connect the board to a personal computer (Figure 8). This board with the related firmware load in the ST microprocessor and the PC software is a complete reference for the mains aspects of powerline communications. Figure 7. ST7538Q demonstration board

Figure 8.

Demonstration board layout
LV HV LV

PC Interface

Power Supply

ST7

Q ST7538P

Signal Signal Coupling Interface
LV HV

LV

The aim of this board is to give a useful tool to develop and to evaluate a powerline application with the device ST7538Q. So even if aspects of the board concerning size and cost aren't optimized, its schematic gives a good design reference and a valid starting point

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Demonstration board for ST7538Q

AN1714

to develop powerline modem applications. Moreover the board structure (a lot of jumpers, test points, few SMD components) allows easily connecting test probes to take measures and signal verifications, as well as customizing the application according to specific requirements. Figure 9. Demonstration board schematic: microcontroller and PC interface

TXD

5V_ P 1 3 R16 4.7K

CN7 2 4 6 8 10 R17 10K ISPDATA ISPCLOCK RESET ISPSEL

D13 1N4148

JP1

C27 100nF

C28 100nF

C29 100nF

C30 10 F

C31 100nF

5 5V 7 9

ISP INTERFACE MICRO_TXD R2OUT H_S RS232_OUT RS232_IN R1IN_A T1OUT_A 5V_232 T2IN T1IN R1OUT R1IN T1OUT VCC GND

U3
9 10 11 12 13 14 16 15 V+ 2 8 7 5

R2IN T2OUT T2OUT_A C26 100nF

CN5 FEMALE 5 9

RN1 1 5 4 R1IN_A 3 2 T1OUT_A TOUT T2OUT_A COMMON R4 R3 R2 R1 D11 RED CD/PD D10 YELLOW RX PA6 J10 5V J9 J8 D12 GREEN TX PA7 D9 RED 5V_led

ST232
4 3

C2C2+

4 8 3

C1C1+ V-

1 6

C25 100nF

7 2 6

C32 100nF

1 PC INTERFACE

PA4

PA5

C24 100nF

C23 100nF

5V_232 5V_led 5V_ P

U4
OSCOUT 5V_ P RESET RS232_OUT MCLK ISPSEL PA7 PA6 PA5 PA4 RS232_IN SS CLRT TOUT REG_OK H_S WD REG/DATA RXTX 5V_ P ZCOUT PG VDD_2 RESET PE0/TD0 OSCIN ISPSEL (HS)PA7 (HS)PA6 (HS)PA5 (HS)PA4 PE1/RDI PB0 PB1 PB2 PB3 ANI0/PD0 ANI3/PD3 ANI4/PD4 ANI5/PD5 VDDA PF2 MCO/PF0 VSSA 41 43 39 44 42 38 37 36 35 34 1 2 3 4 5 7 10 11 12 13 17 15 14 29 28 26 27 25 24 PC6/SCK/ISPCLK PC5/MOSI PC3/ICAP1_B(HS) PC4/MSO/ISPDATA PC2/ICAP2_B(HS) PC1/OCMP1/B PC0/OCMP2/B EXTCLK_A(HS) ICAP1_A/PF6(HS) OCMP1_A/PF4 PF1/BEEP AN2/PD2 AN1/PD1 PB4 VDD_0 VSS_0 VSS_1 VSS_2
D03IN1450

32 31 30

VDD_1 PA3 PC7/SS

5V_ P CD/PD SS ISPCLOCK J11 CLRT RXD ISPDATA MICRO_TXD CN6 12 11 10 7 6 4 BU 8 3 5 9 2 5V_ P 5V_ P 1

ST2334N2

23 20 19 18 16 9 8 6 21 22 33 40

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2.2
F1 TR5-F 0.5A 1 P N L3 10 H J1 1 CN2 ZCI N ZCOUT ATOP1 2 ATOP2 RXFO ATO 1 2 3 4 5 6 7 3 C8 1F 5V L8 10 H C7 2.2nF/Y1 JP35 TEST1 CMINUS 37 1 3 31 29 30 6 25 AVSS C21 100nF PAVCC PAVSS 20 27 XIN 1x 16MHz 26 32 15 14 23 39 MCLK N.C. 34 N.C. 44 N.C. 13 TEST3 JP13 5V 16 24 ZCIN JP16 XOUT RAI ZCOUT WD CL ATO ZCOUT WD C18 47pF SOLD CRYSTAL CASE TO GND C19 18pF J7 C33 10nF C38 10 F P10V GND TEST2 JPTIN VSENSE 38 40 4 5 36 42 RXFO 19 ATOP1 C13 220nF 35 17 28 33 21 J2 RXD CPLUS J3 C_OUT Rx/Tx 5V TXD REG_OK PG REG/DATA RESET C22 22nF SW1 41 10 18 2 7 8 9 11 DVDD DVSS DVSS TIMEOUT CLRT BU MCLK BU CLRT TIMEOUT GND 5V C20 300nF R15 4.7K RSTO 12 REG_DATA 43 PG REG_OK TXD RxTx C_OUT RXD CD/PD CD/PD N.C. AVDD VDC ATOP2 C16 100nF JP36 C14 10 F C15 100nF LC12 10 H D15 P6KE6V8A C_R9 100nF R10 5.1 D17 1T SM6T6V8A D16 P6KE6V8A VAC T604034096-X046 R12 50K TRIM R14 1K C17 5.6nF/63V R11 750 J4 J5 P N 1T R7 910 C10 1F L1 42V15 2 x 10mA 0.3A RADIOHM DRAIN VCC R3 10 8 R5 3.3K RL6 10 D7 1N4148 D5 GREEN D6 1N4148 1 R2 2.2K C2 C3 4.7 F 4.7 F 400V 400V P10V CN4 C1 47nF 400V L2 220 H D1 1.5A W04 L5 1mH R1 16.2 2W 2

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CN1

ACLINE 85VAC to 256VAC

L6590
GND GND GND 8 4 VCOMP 5 VFB 7 6 3 C6 22 F 50V

1

TR1 RADIOHM 69E16H1B 4 D3 D2 BZW06STPS160ASMA 171 7 D4 STTA106 2 C34 100nF C4 C5 470 F 470 F 16V 16V

U1

T2

L4 22 H CN3 C11 33nF 220V X2 R8 4.7M 1

Signal coupling interface
2 L7 330 H C36 4.7nF VSENSE CL 22 J6

ST7538Q P
U2

ATO R13 5K TRIM

C37 100pF

Figure 10. Demonstration board schematic: line coupling interface and power supply

The line signal interface links the application board to the mains, obtaining a highly efficient coupling circuit for the received and transmitted FSK signals and a reliable filtering system for the mains voltage (220 V~/50 Hz or 110 V~/60 Hz), for noise and for bursts or surges.
D03IN1451

Demonstration board for ST7538Q

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Demonstration board for ST7538Q

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It is possible to implement different topologies of coupling circuits. A first classification is between an isolated solution with a line transformer or a double capacitor and a nonisolated solution with a single high-voltage decoupling capacitor. The last one is simpler and cheaper, while the first one achieves better performances using efficiently the differential power output of the devices. The differential solution has been also preferred for the advantage in reducing the even harmonics of the transmitted signals. Figure 11. Demonstration board ST7538Q powerline interface
ST7538Q
C33

Rx Band Pass Filter
32

R11

R AI

L7 C36

Tx Band Pass Filter
L4 C11

ATOP1

19

C13

1:1
R10 D16 D17 R8 CR9

MAINS

ATOP2

21

D15 T1

LC12

Protections

Tx Band Pass Filter

In the design of the coupling interface many technical and standard constraints have to be considered that are different in a receiving condition with respect to a transmitting status. Following is a list of design specifications for signal coupling for the European market:

High selectivity in receiving mode (EN50065-2-1) Output impedances as great as possible (EN50065-7) Low noise in receiving mode Wide voltage and current signal compatibility in every condition (EN50065-1) Very low distortion in transmission mode (EN50065-1) High coupling efficiency in transmission mode (also with high loads) High reliability to burst and surge spikes (EN50065-2-1)

A series of constraints listed in EN50065-4-2, "Low voltage decoupling filters - Safety requirements", have to be guaranteed by the decoupling elements (transformer or capacitors) in order to be compliant with a 4 kV or 6 kV class. The solution implemented in the demonstration board is an isolated circuit with a 1:1 transformer and a X2 class capacitor. In the chosen topology the transmission sections components do not have any relevant influences on the receiving circuits, so the two structures can be analyzed separately. The component values that consitute the passive filters have been dimensioned for the 132.5 kHz channel, but also with the 110 kHz communication frequency, the performances of the board meet the requirement for reliable communication.

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Demonstration board for ST7538Q

2.2.1

Transmitting section
The function of the transmitting coupling circuits is to inject the transmitted signal coming from the power amplifiers (ATOP1/ATOP2) to the mains with the maximum efficiencies and filter noise and spurious signals over the Cenelec mask (EN50065-1, section 7: disturbances limits). The critical frequencies of the conducted disturbances emitted are the 2nd and 3rd harmonics of the transmitted signal (265 kHz and 497.5 kHz for the channel at 132.5 kHz) the harmonics of the working frequency of the power supply regulator and two spurious tones centered at 1.3 MHz (+/- the channel frequency) produced by the direct synthesis technique used for the transmitted signal generation. The configuration used for the transmitted circuit uses a 4th order band pass filter (four poles and two zeros). In order to have good immunity to the components spread (accuracy and temperature) and to the load variation, the filter has a band of about 60 kHz (see Figure 14). To obtain this characteristic two poles can be put at a frequency of about 100 kHz and the other at a frequency of about 160 kHz. Figure 12. Demonstration board ST7538Q transmission coupling circuit
ST7538Q
RAI
100K 32

C33

R11

C36
2.5V

L7

ATOP1
19

Transmission Coupling Section
L4 D16

Artificial Network CISPR 16-1
C11
50 50 H 5

C13

R10

1:1
D17 R8

ATOP2
21 21

CR9 LC12

D15 T1

50

5

50 H

For a correct dimension of the filters the mutual influence of the various components has to be considered, as well as the influences due to the other elements: the leakage inductance of the transformer (from 0.1 H to 10 H), the capacitance of the transil diode (about 2 nF), the ESR of the series components C13, LC12, T1, L4, C11 (from 100 m to 1 ). For a first approximate rate of the components' values, only the reactive components are used in the simplified circuit of Figure 13 and the transformer (1:1 ratio) is considered ideal. For the correct dimensioning of the filter it is better to consider the typical impedances expected for the mains network (usually an inductive load). If an impedance characterization of the network is not available it is possible to use a reference load like the artificial network CISPR16-1 (50 ohms parallel 5 plus 50 H). In the simplified circuit only the reactive part of the CISPR 16 artificial network (2 x Lc = 100 H) has been considered

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Demonstration board for ST7538Q Figure 13. Simplified schematic of the transmission filter
CISPR Load

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C13

LC12

L4

C11

Lc = 50H

1st Loop

CR9

2nd Loop
Lc = 50H

The formulas for the two couples of poles are: Equation 2
1 p 1 = p 2 ------------------------------------------------------- 160 k H z , 2 L C 12 C A 1 p 2 = p 3 ----------------------------------------------- 100 k H z 2 LB CB

Equation 3
1 1 1 ------- = ----------- + ---------- ; CA C R 9 C 13 1 -----1---- = ----------- + ----1------CB C R 9 C 11

The peak value of the signal current can reach with heavy load a current peak value greater than 1 A so all the components of the coupling interfaces in series to the signal (in particular the inductors LC12, L4 and the transformer T1) have to be guaranteed for this current without saturation or overheating problems. The maximum current of the inductive elements, as well as the series resistance, are proportional to the value of the inductance. In any case the ESR of these inductive elements has to be as low as possible to obtain a good coupling interface. In fact with a global impedance series greater than 2 the coupling losses of the transmitted signal with heavy loads could be excessive. For these reasons an LBC (Large Bobbin Core) inductor with values small as possible (LC12 = 10 H and L4 = 22 H) has been chosen in this circuit. Another constraint concerns the value of the capacitor C11. This is an X2 class capacitor that has the primary function to uncouple the transformer from the mains. It is better to use a value as low as possible for economic reasons, as well as to obtain a 50 Hz mains current in the secondary coil of the transformer as low as possible in order to reduce saturation effects. The value chosen is 33 nF. Considering that all the mains voltage drops across the C11 capacitor, the current value in the transformer coil is about: Equation 4
I r m s 220 V r m s 2 50 H z C 11 = 2.3 m A r m s

Using Equation 2 and Equation 3 the values of CR9 (100 nF) and C13 (220 nF) can be rated. The requirements for this type of capacitor are accuracy, the temperature compensation and a low ESR value. Polyester capacitors or polypropylene capacitors (better temperature coefficient) are suggested. The accuracy should be at least 10%.

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Demonstration board for ST7538Q

Figure 14. Simulated characteristics of the transmission coupling filter

dB VDB (OUTC2) 10

0

-10

-20

-30

-40

-50

-60

-70

-80 1e+U4 1e+U5 Hz 1e+U6 2e+U6

Using components with standard values the real values of the poles are: Equation 5
p 1 = p 2 = 192 k H z , p 2 = p 3 = 91 k H z

The values obtained are very close to the spec values and in agreement with the simulated results (see Figure 14). In any case for a better result we suggest using a simulator or an equivalent specific program to design filters. The R10 resistor has been added to fit the output impedance requirement in receiving mode (EN50065-7). An alternative solution for the transmission coupling circuit is shown in Figure 14 above. It implements a 2nd order band pass Butterworth filter centered at the channel frequency. The advantage of this solution is the symmetrical structure that compensates the nonlinearity of the components (lower level for the even harmonics). Also in this case a correct dimension of the filter has to take in account the parasitic elements of the various components, as well as the load influence.

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Demonstration board for ST7538Q Figure 15. Coupling circuit with a 2nd order band pass butterworth

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Q ST7538

Transmission 2nd order Band Pass Butterworth
33nF X2
19 220nF 10 H 4.7

ATOP1

1:1

MAINS

100nF

47 H

ATOP2

21 220nF 10 H

One of the most critical components of the application is the signal transformer. In order to have a good power transfer and to minimize the insertion losses it is recommended a transformer with a primary inductance greater than 1 mH and a series resistance lower than 0.5 Another constraint concerns the saturation current: a DC or low frequency current (50 . Hz) should be present. Another parameter to take in consideration is the leakage inductance. If it has a relevant value (from 10 H to 50 H) the inductance L4 can be avoided. The drawback is that this parameter has great variation that influences the output filter characteristics. For this reason in the demonstration board a transformer with a very low leakage inductance (lower than 1 H) is used . The European normative (CENELEC) gives another constraint regarding the voltage insulation resistance and dielectric strength of the application that influences the transformer. Two classes are indicated, a 4 kV and a 6 kV class. The classification and measurement criteria are codified in the EN50065-4-2 CENELEC document. In case of heavy load a smart solution is to use a 2:1 transformer. The equivalent impedance of the load referred to the primary coils of the transformer has a value four times bigger than with a 1:1 ratio transformer. Also the current supplied by the power interfaces has half value. The only critical point is that in order to have the same output signal level on the mains, the ST7538Q power interfaces has to generate a double signal (more problems with odd harmonics). Seldom a low amplitude signal at high frequency (greater than 10 MHz) can be present on the output signal. It should originate by a resonance from the leakage inductances and the parasitic capacitance of the board and of the ST7538Q output stage. Usually the series inductor LC12 stops this kind of oscillation.

2.2.2

Receiving section
The receiving circuit of the coupling interface has the main function to filter noise tones from the network that can overcome the maximum absolute rates of the RAI pin, or in any case degrade the demodulation performances of the device (EN50065-2-1, section 7.2.3: narrow-band conducted interference). The solution adopted in the demonstration board consists of a resonant parallel circuit that implements a 2nd order passive filter (C36, L7 R11). The C33 capacitor is a decouple component that saves the DC value on the RAI pin (2.5 V). This DC value obtains the maximum voltage input signal (2Vrms) compatible with the absolute of the devices.

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Demonstration board for ST7538Q Figure 16. Demonstration board ST7538Q receiving circuits
ST7538Q
RAI
100K 2.5V 60K 32

C33

R11

L7 C36
22

Receiving Coupling Section
L4 C11

PAVCC

ATOP1
60K

19

C13

R10

D16

1:1
D17 R8

CR9 ATOP2
21

D15 T1

LC12

In the receive mode the ATOP1 pin has a high impedance and a DC polarization at PAVcc/2 while the ATOP2 pin is tied to ground internally into the device with a power MOS (few milliohm resistance). With this configuration the two resonant series L4, C11 and LC12, CR9, R10 can be considered as first approximation neglected (L4/C11 has the resonance at the channel frequency while the LC12/CR9 has the resonance at an higher frequency). The only effect of these components is to attenuate the amplitude of the received signal, about 6 dB with the used values of CR9 and R10. According to these considerations the dimension of the input filter frequency depends mainly on the choice of C36 L7 and R11. These components implement a 2nd order band pass filter. The center band frequency of the filter is the channel frequency: Equation 6
1 0 ------------------------------------------------- = 132.5 k H z 2 L 7 C 36

The other parameter to take in account for the receiving filter design is the Quality factor (Q). Its value is a tradeoff between the selectivity requirements (high Q values) and the component and temperature spreads. Using a polypropylene capacitor with a 5% tolerance and a BC inductor with a tolerance of 10%, a Q value betweens 2 and 3 is acceptable. Equation 7
Q R 11 C 36 ---------- = 2.85 L7

In order to not influence the transmitting section and to reduce the DC current through the primary coil of the transformer, the value of R11 should be as high as possible. The drawback of a greater value for this resistor is that it produces a higher white noise. A value of 750 satisfies these opposite requirements for all communication channels. Fixing the resistor value and using the previous equations, it is possible to rate the values of C36 and L7.

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Demonstration board for ST7538Q

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Table 1 shows some possible commercial values for these components in reference to different communication channels. Table 1. Parallel resonance Rx filter components
Rx filter C36 Ch 132.5 kHz Ch 110 kHz Ch 86 kHz Ch 82.05 kHz Ch 76 kHz Ch 72 kHz Ch 66 kHz Ch 60 kHz 6.8 nF 10 nF 10 nF 8.2 nF 10 nF 22 nF 18 nF 22 nF L7 220 H 220 H 330 H 470 H 470 H 220 H 330 H 330 H F0 130.1 kHz 107.3 kHz 87.6 kHz 81.1 kHz 73.4 kHz 72.3 kHz 65.3 kHz 59.1 kHz

The resonance frequency of the filter is strictly linked to the spread of these components and an excessive spread can produce an excessive attenuation on the received signal. The accuracy of L7 and C36 has to be great. For the same reason the Q factor has a relevant part in the design of the Rx filter. Some application can use more than one communication channel at the same time, in this case the best choice is to have a resonance frequency at a mean value of used frequencies and a Q factor not too high. Figure 17. Measured filtering characteristic of the demonstration board at the RAI pin in receive mode
RxFilter 0.00E+00 -1.00E+01 -2.00E+01 dB -3.00E+01 -4.00E+01 -5.00E+01 1.00E+04 1.00E+05 Hz 1.00E+06

For the receiving filter a passive solution is preferred to an active filter. The experience has shown evidence that an active filter introduces white noise comparable with the received signal level. Some receiving circuit interfaces, for example with a 2:1 signal transformer, can have a gain greater than 0dB (unit gain). In this case, if the band-in-use function level of the ST7538Q is used, an attenuation of the received signal (for example with a resistors divider) is necessary to have the same level of the signal present on the mains to be compliant with Cenelec specifications.

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Demonstration board for ST7538Q

2.2.3

Voltage regulation-current protection loops
A powerline network requires an appropriate driving circuit able to adapt the output signal characteristic to the different and low values of the mains impedance. Figure 18. Powerline output characteristics
V
V0
Signal Amplitude

I zone V zone

z

Z0

Line load (ohm)

Figure 18 shows the characteristic of a coupling circuit. The characteristic has a range with constant voltage amplitude of the transmitted signal. When the line impedance has reached a critical Z0 value, corresponding to the maximum power, the amplitude of the output signal is decreased in order to have a constant current. The value of Z0 depends mainly on the network impedance, while the maximum value of V0 depends on the norm (EN50065-1) and on the maximum current capability of the powerline interface. The ST7538Q integrates a control voltage / current protection circuit. It is possible to program the values of Z0 and V0 with external resistors. The R13 trimmer sets the current protection limit and the R14 and R12 trimmers the peak voltage level. The dimension of these external components influences the design of the coupling interfaces and of the power management, too. For example all the components in series to the signal (transformer, filter inductors, decoupling capacitors, fuses) have to guarantee a maximum current or a saturation current greater than the maximum current programmed with R13, as well as the dimension of the current capability of the power supply. The capacitors on the supply line have to be chosen according to the programmed current values. The control loop circuit inside the devices is obtained by a Voltage Controlled Amplifier (VCA) with a logic circuit that implements the following control (Figure 20). The current protection has the priority with respect to the voltage loop regulation, so if an output current greater than the programmed value (Iref > IH) is detected, the digital control acts on the VCA to reduce the output signal voltage. When the current reaches the programmed value, the gain of the VCA is frozen. In case of no current protection condition (Iref < IL), the voltage regulation loop assumes the control and modifies the gain of the VCA until the output signal reaches the programmed values. The VCA changes its gain at steps of about 1dB (10%). The logic samples the current and voltages values with an internal clock of 5 Hz, so the transmitted signal is updated every 200 sec at steps of 1 dB.

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Demonstration board for ST7538Q Figure 19. Voltage regulation and current protection components
ST7538Q Vout ATOP/ATO Iout C 17 VSENSE R14 CL R12
VCL HYST VCL HYST VCL TH

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VR PK

Voltage Controlled Signal

1.865 V

R13

C37

Feedback Signal

The value of the transmitted signal is programmed using the resistors divider R12/R14 (the capacitor C17 has a decoupling function for the DC value on the VSENSE pin). The regulations loop changes the VCA amplifier gain until the sinusoidal signal on the VSENSE pin reaches the values of VCLTH (see datasheet values) with a tolerance of about 10% (VCLHYST hysteresis value). The following simplified formula calculates the resistors divider ratio. Equation 8
VR R +R VCL =190mV 14 12 TH ---------------------------- ( V C L VCL ) PK TH HIST R VCL =19mV 14 HIST

For a more precise rate in the formula, the input impedance of the VSENSE pin (~36 K) and the decoupling capacitor C17 (for values of some nanofarads this capacitor can be neglected) have to be considered also. Figure 20. Voltage regulation/current protection loop logic
Current Control

Iref < IL

Test Test

Iref > IH

Constant Gain

Reduce Gain

Voltage Control

Vref < VL

Test

Vref > VH

Increase Gain

Constant Gain

Reduce Gain

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Demonstration board for ST7538Q In the demonstration board it is possible to link the feedback signal (top of R12 resistor) to the ATOP1 or to the ATOP2 pin through jumper J36. The choice of the feedback connection point depends on the network coupling circuit topology. If a big noise coming from the mains is present disturbing the voltage control loop, a possible solution is to connect the feedback to the ATO pin. In this case the output signal has half the value with respect to the ATOP pins, so the R12 resistor has a half value (or the R14 resistor has to be doubled). In the demonstration board it is possible to change the output signal voltage level acting on the R12 trimmer. Table 2 gives the values of the trimmer to assume some standard output values. Table 2. Voltage regulation loop (divider and R12 resistors values)
Vout (dBuV) 103.5 108.0 110.9 114.0 115.9 117.5 118.8 120.0 121.9 123.5 (R14+R12)/R14 1.1 1.9 2.7 3.7 4.7 5.8 6.6 7.6 9.5 10.8 R12 (K) (2) 0.1 0.9 1.7 2.6 3.6 4.7 5.4 6.4 8.3 9.5

Vout (Vrms) (1) 0.150 0.250 0.350 0.500 0.625 0.750 0.875 1.000 1.250 1.500

1. The regulated Vout voltage is the point linked to the voltage feedback divider (top of R12). 2. The rate of R14 takes in account the input resistance on the VSENSE pin (36 K). The decoupling capacitor (C17) has been neglected.

The resistor connected to the CL pin (the trimmer R13 in the demonstration board) has the function to program the current protection threshold. The capacitor C37 in parallel to the resistor has a filtering function for noise and spikes. A mirrored current (ratio 1:5000) of the p channel power Mos of the powerline interface of the device (both ATOP1 and ATOP2) is present on the CL pin. The voltage on the CL pin is proportional to the output current and to the resistor connected to the pin. The peak value of this voltage is compared with an internal reference of the device. If the signal overcomes the threshold, the loop acts on the VCA reducing the transmitted signal and therefore the output current. The resistor value determines the output signal that the interface is able to supply. In conjunction with the programmed output voltage V0 the maximum current level fixes the minimum value of driving impedances (Z0).

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Demonstration board for ST7538Q Figure 21. Current protection loop characteristic
mA (rms) 350 325 300 275 250 225 200 175 150 125 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 R13 (Kohm) Current Protection

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Figure 21 above gives the value of the CL resistor to program the maximum current value. Figure 22 shows all the main signals of the control loop feedback, i.e. output signal, load current, VSENSE voltage and CL voltage. Figure 22. Voltage regulation and current protection feedback signals

2.3

Board power management
The demonstration board has a mains supply with a flyback converter using the monolithic switching regulator L6590. The regulator can have both a 220 V or an 110 V supply voltage of the mains. It is possible to use an external power supply connected to CN2, too. In this case the jumpers J4 and J5 have to be removed and the connector CN3 has to be used instead of the standard socket CN1.

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Demonstration board for ST7538Q The correct supply of the board is indicated by the green LED D5. It is possible to turn off this LED by removing the J1 jumper. The 5 V internal regulator of the ST7538Q (VDC pin) supplies the microcontroller ST7, the ST232 interface device and the LED (D9, D10, D11, D12). Using the jumper connections J8 (ST7), J9 (LEDs) and J10 (ST232) it is possible to monitor the current of these components or remove the supply to these demonstration board parts. The 5V supply is available also on pin #1 of the CN6 connector. A typical power consumption of the powerline application (switched regulator excluded) is about 18mA in receiving mode, 120 mA in transmitting mode without load. Every LED ON increases the current consumption by 4 mA. The current consumption of the RS232 interface is about 12 mA, which means that the overall current consumption of the microcontroller plus the ST7538Q in receiving mode is about 6 mA. The current consumption depends also on the clock frequency selected. There is a variation of 5 mA from a 4 MHz clock to a 16 MHz clock.

2.3.1

L6590 regulator
The flyback converter configuration using the L6590 regulator has a specific topology that implements the feedback on an auxiliary winding of the primary side of the flyback transformer. With this configuration it is possible to save the cost of an optocoupler. The drawback of this solution is the wide load range of the regulated voltage. In a condition of low current consumption (20mA) the value of the supply voltage is about 12 V, in transmission the value is about 10.5V. The maximum power of this configuration is about 3 W. The dimension of the maximum power consumption of the regulators is related to the current limit of the powerline interface programmed with the R13 resistor on the CL pin. If an external power supply is used, the designer must carefully verify that also in a continuous transmission condition the supply is able to supply the requested current. Another aspect that has to be considered with attention in a continuous transmission condition is the overheating condition of the devices with the thermal protection activation (transmission aborted and signal TOUT high). In the demonstration board a socket for the ST7538Q is used, therefore the slug of the package cannot be soldered to a dissipating surface as recommended. For this reason, in presence of a heavy load during a continuous transmission, the thermal protection threshold is reached in a shorter time. A critical point common to all switching solutions, especially for this kind of application, is the electromagnetic noise and the conducted disturbance generated. In particular the main noise frequencies are due to the switching frequency and to the resonance of the leakage inductance with the drain capacitance.

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Demonstration board for ST7538Q Figure 23. Power supply EMC disturbances filter circuit
R1 L1 C1 L5

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D1

MAINS

In the demonstration board these critical values are at 20 kHz or 66 kHz (switching frequencies respectively with low and high load condition) and at about 800 kHz for the resonance. It is important that the resonance of the input filter is at a frequency far from the communication bands used, otherwise its low impedance attenuates the communication signals. For the demonstration board the resonance frequency is from 10 kHz to 20 kHz. The 15 resistor R1 has the double function to protect the input stage of the supply from surge or burst and at the same time to make the application board compliant with the EN50065-7 standard. Another consideration concerns the frequencies noise generated by the supply. Even if the noise generated is compliant with the normative mask limit, it is mandatory to choose a value of switching frequency (and its lower order harmonics) far from the communication channel frequency. In fact the modem is able to demodulate very low amplitude signals (500uVrms). Noise, also with a low amplitude value, can degrade the communication. This consideration is valid only in a receiving condition, during the transmission a little noise at the same frequency of the transmitted signal (2Vrms) can be neglected. The working frequencies of the L6590 are 20 kHz with a low value current (receiving condition), and 66 kHz with high current, i.e. in a transmission condition (220 AC MAINS). In the transmission case the 2nd harmonic at 133 kHz (communication channel 132.5 kHz) has an irrelevant influence. The value of the supply voltage is related to the amplitude of the output signal (see the ST7538Q datasheet), so usually a voltage of at least 10 V is mandatory to avoid distortion problems. The same voltage value does not occur in a receiving status. In case of strong constraints regarding the power consumption, it is possible to use two different power supply values. For example possible values are 10.5 V during the transmission, and 7.5 V in the receiving status. This can be done easily by changing the feedback resistor divider of the regulator using a switch controlled by the RxTx signal (pin #4) of the ST7538Q. For more detailed information about the L6590 and other possible configuration please refer to the product datasheet and related application notes.

2.3.2

ST7538Q power supply
A fundamental aspect of the board design is the configuration of the ST7538Q supply system.

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Demonstration board for ST7538Q It is recommended to connect all grounds of the device to a common ground node, connected to the copper plate of the slug. During transmission a high current (up to 0.3Arms = 0.85App) at the signal frequency is present through the supply rail and the ground plane. In case of ground or supply paths with a "high" resistance (even a few m can be critical), the high current could produce a ripple at the second harmonic of the signal frequency that should be coupled onto the mains: Equation 9
0.85A p p 0.002 = 1.7mV p p 56 d B V

As the rate above shows, the noise contribution has a relevant value with respect to the Cenelec mask. Figure 24. Noise generation in resistive supply or ground path
Noise
ST7538Q
22 PAVcc

2 m

ATOP1 19

ZL
ATOP2 21

PAVss 18

2 m

Noise

Concerning the odd harmonics, generally they are produced by high current (high load) and are generated by saturation problems of external components or of the power section of the device. Another origin of the odd harmonics with high amplitude of the voltage output signal could be a low power supply value on the PAVCC pin. A critical aspect of the device power supply is the high peak current requested at the startup phase of the transmission. The peak value requested from the supply from the low impedance present at the ATOP pins can reach 2 A. For this reason it is mandatory to use a storage capacitor (C38) with a value of at least 10 F and an ESR as low as possible. For example a tantalum capacitor or a smoothing ceramic capacitor (TDK C series) could be used. The linear low drop voltage regulator of the ST7538Q supplies all the low voltage parts of the demonstration board, including the digital and analog (pin DVDD and AVDD) parts of the device itself. On the regulator output VDC (pin #33) a low ESR 10 H capacitor (C14) is recommended. In some conditions a noise present on the analog supply AVDD (pin # 28) can be transferred to the internal modulation and demodulation blocks. To avoid this situation it could be useful

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Demonstration board for ST7538Q

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to filter this supply pin adding an inductor (L8) in series to the capacitor (C16) or using a specific EMC component (for example a TDK chip beads series MMZ1602C).

2.4

Crystal oscillator
The ST7538Q crystal oscillator circuitry is based on a MOS amplifier working in inverter configuration. This circuitry requires a crystal having a maximum load capacitance of 16 pF and a maximum ESR of 40 . It is very important to keep the crystal oscillator and the load capacitors as close as possible to the device. The resonant circuit must be far away from noise sources such as:

Power supply circuitry Burst and surge protections Mains coupling circuits Any PCB track or via carrying a signal

To properly shield and separate the oscillator section from the rest of the board, it is recommended to use a ground plane, on both sides of the PCB, filling all the area below the crystal oscillator and its load capacitors. No tracks or vias, except for the crystal connections, should cross the ground plane. It is also recommended to use a large clearance on the oscillator related tracks to minimize humidity problems, see Figure 25. Connecting the case to ground is also a good practice to reduce the effect of radiated signals on the oscillator. Figure 25. A recommended oscillator section layout for noise shielding
ST7538Q
25 26 SGND XOUT 27 XIN

TOP Layer

Clearance

BOTTOM Layer

It is possible to provide an external clock with the requested characteristics at the XOUT pin. Probably in this case the global power consumption of the application will have a relevant increase.

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Demonstration board for ST7538Q

2.5

Burst and surge protections
The environments encompassed by this application include residential, commercial and light-industrial locations, both indoor and outdoor. For this reason a series of immunity specification standards and tests have to be applied to the powerline application to simulate the environment. The requirements include EN610000-4-2, EN610000-4-3, EN610000-4-4, EN610000-4-5, EN610000-4-6, EN610000-4-8, EN610000-4-11 and ENV50204. All these tests are listed in the EN50065-2-1 document (part 7, immunity specifications). These standards include surge tests, both common and differential mode (1 kV/0.5 kV, Tr=1.2u sec) and fast transient burst tests (2kV, Tr=5n sec, Th=50n sec, repetition frequency 5 kHz). The specific structure of the coupling interface circuit of the application is a weak point with respect to the high voltage tests. In fact an efficient coupling circuit with low insertion losses consequently obtains a very low impedance path from the mains to the power circuit of the devices that can destroy the internal power circuits of the ST7538Q. For this reason is recommended to add some specific protection on the path that links the ATOP pins to the mains. Figure 26. Common mode and differential mode spikes example
ST7538Q
22

ST7538Q

22

19 D16 D17

19

1:1
D17

D16

1:1

21

D15 21

Differential Mode

Common Mode

A solution that uses three transil diodes (P6KE6V8A or SM6T6V8A) connected in a star configuration has been implemented in the demonstration board. A bidirectional transil was not used because for common mode surge it is better to have a discharge path to ground external to the devices. In receiving mode the ATOP2 pin polarizes the coupling interface to ground. In this condition without the diode D17 all the external signals greater than 1.4 V peak-to-peak are clamped by D15 and D16. In some conditions the transil diodes may not be reliable in presence of fast transient bursts. In this case it is possible to add some fast response ESD diodes as ESDA6V1L (two components) connected in parallel to the transil with the same star configuration. The solution used for the demonstration board can give some general guidelines but can't be generalized to all types of powerline communication applications. Considerations about surge and burst protections depend on several factors such as coupling interfaces, the board layout or the characteristics of the components used. Every application needs a specific analysis.

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For some general considerations or a protection components list refer to the annexed application notes and documentation.

2.6

ST7 microcontroller and RS232 interface
To complete an application for the powerline communication a microprocessor must manage the upper layer of the communication protocol and eventually process other signals related to the application (signal from sensors, current measures, driving actuators, and so on). A different type of microcontroller can be required depending on the specific application. The demonstration board has a ST72C334J2 or ST72C334J4 microprocessor. This component is connected to the ST232 driver interface and to the ST7538Q. The loaded firmware has the function to receive from the PC program interface (through the standard RS232 serial port) some commands to manage the control register writing and reading procedures as well as the transmitting and receiving functions of the modem. The results of the executed command come back to the PC program interface and are displayed on the monitor. Figure 27. Microcontroller/RS232 interface
5V_led

ST72C334
1k 1k 1k 1k

RN1 37 36 35 D10 34 D11 D9 D12

PA7 PA6 PA5 PA4

CN5 PC INTERFACE ST232
T1OUT R1IN T2OUT
14 13 7 2 3 1

PE0/TD0 PE1/RDI ANI0/PD0

44 1 7

11 12 10

T1IN R1OUT T2IN

T1OUT_A R1IN_A T2OUT_A

The ST7 microprocessor controls also the LED diodes D9, D10, D11, D12. The D9 (red) is turned on during a transmission condition; the green LED D12 is turned on when the receiving mode is activated. The D10 yellow diode is switched on when the Band-in-Use signal is active. The D11 LED (red) is on when a Timeout event occurs. To save power consumption the LEDs are turned off by removing jumper J9. The ST7 firmware can be customized. Some of the I/O digital pins or analog input pins of the microprocessor, that can be used to monitor some external signal or sensors and to drive relays or other external devices, are available at the connector CN6. The connector CN7 is used for ST7 memory in-situ programming. For a correct programming procedure the ST7538Q has to be supplied, we suggest using an external 10 V supply from the connector CN2. The jumper J11 has to be opened.

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Demonstration board for ST7538Q If an emulator is linked to the board we recommend programming a 4 MHz clock in the ST7538Q internal register. For more accurate and complete information on the features, characteristics and issues concerning ST microprocessors, please refer to the attached documentation or to the reference documents or go to the site www.stmcu.com.

2.6.1

Modem / microcontroller interface
The interface signals between modem ST7538Q and the ST2C334 microcontroller can be divided in three categories: the control signals, the communications signals and the auxiliary signals. The first group consists of the clock signal (MCLK/OSCIN) the reset signal (RSTO/RESET) and the watchdog signal (WD/PD3). The clock signal of the microcontroller is provided by the ST7538Q from the MCLK pin. The default is 4Mhz but it is possible to increase this value (8 Mhz or 16 MHz) by programming the ST7538Q control register. The reset of the microcontroller is provided by the modem. The reset line is connected to the manual reset (C22, R15 and SW1) and to the reset pin of the CN7 connector for the In-Situ Programming mode procedures. The watchdog signal has to be managed from the microcontroller (PD3 output port). If the ST7538Q doesn't detect any activity on the WD pin, it generates a reset signal on the RSTO pin. It is possible to disable this function through the modem control register. The second group of signals consists of the links necessary for the modem/Micro Controller Unit communication. These include the data signals RXD (from the modem to the MCU) and TXD (from MCU to the modem), the transmitting/receiving status selection signal (RX/TX), the internal ST7538Q register control access signal REG/DATA, and the recovery clock signal CLRT. The ISP (In Situ Programming mode) signals coming from the CN7 connector are also linked to the communication wires and to the RESET. Remember to open the jumper J11 during the programming phase. The simplest interfacing mode is the synchronous mode. In this case it is possible to use the SPI interface of the MCU. The PC5/MOSI (Slave In Data) is connected to the RXD pin, the PC4/MISO pin (Slave Out Data) is connected to the TXD pin and the PC6/SCKI (SPI serial clock) pin is connected to the CLRT pin. The SPI Slave select (PC7/SS) is controlled by the MCU itself through the PB0 I/O port. The CLRT signal is connected to the PB1 I/O pin too. It is also possible to implement an asynchronous interfacing mode, and for this reason the pin RXD is also connected to the PC3/ICAP1_B pin (timer B input capture). In this modality of communication the CLRT signal isn't considered and the recovered clock has to be rebuilt internally by the MCU. If the ST7538Q control register has to be changed from the default configuration, the first access has to be done at baud rate of 2400. The idle state of the RXD output is the low state, so an asynchronous interface could be necessary to invert externally this signal. A diode (D13) and a pull down resistor R16 were inserted on the TXD connection line. With these components it is possible to transmit a frame coming from an external device (for example a BER tester). It is sufficient to configure the modem in a transmitting status and

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the MCU has to keep the PC4 pin low. The external signal can be applied at the diode cathode. Figure 28. ST7538Q / microcontroller interface

OSCIN RESET

42 39 R15

11

MCLK
12

RSTO
3 5

26

ISP RESET

SW1

C22

PC3/ICAP1_B PC4/MISO/ISPDATA PC5/MOSI PC6/SCKI/ISPCLK ANI4/PD3 ANI5/PD4 ANI6/PD5 PA3 MCO/PF0 PF1/BEEP PF2
27 28 29 D13 J 11 R16 8

RXD TXD

ISPDATA

CLRT WD REG/DATA RXTX CD/PD PG BU ZCOUT

10 11 12 31 15 16 17 3 4 5 2 30 38 R17

ISPCLOCK

14 43 4

1 42 9 15

ST72C334 ST72C334

PB1 PB2 PB3 PB0

ST7538Q
7 36

TOUT REG_OK

PC7/SS ISPSEL

ISPSEL

The third group of signals consists of a series of auxiliary signals coming from the ST7538Q linked to some standard input of the microcontroller. The CD/PD and BU signals give information about a carrier (or preamble detection) condition and about the BU condition (according the EN50065-1). If the zero-crossing comparator is used, the ZCOUT signal gives a digital signal synchronized with the mains phase. The PG, TOUT and REG_OK signals are monitor signals. The PG signal indicates the correct supply level of the internal 5 V regulator of the ST7538Q (VDC). If the modem regulator supplies the microcontroller or its reset is connected to the RSTO pin, it is recommended to monitor this signal. In fact when the PG signal goes down during a shutdown procedure, the microcontroller can try to correctly stop the running activities (for example a memory writing) before the UVLO threshold is reached and the entire application is reset, or before the regulator isn't able to correctly supply the micro. When a PG down is detected, the transmission is disabled to avoid uncontrolled access to the mains. In any case a correct shutdown procedure has to be completed to perform a correct reset of the application. The TOUT signal is active when a transmission procedure is aborted, either for a time out event or for an overheat condition. The REG_OK signal shows corruption of the internal modem register. Pay attention that the REG_OK function doesn't check uncontrolled control register write procedure, due for example, to a voltage spike on the REGDATA and RX/TX pins.

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Demonstration board for ST7538Q

2.7

Bill of material
Table 3.
Item 1 2 3 4

Power supply sections
N 1 1 1 2 Name CN1 CN2 C1 C2 C3 Descriptions Header 2 Header 2 47 nF/250 V~ Y2, EVOX RIFA, PME271Y447M 4.7 F/400 V Rubycon YK, 400-YK-4R7-M-T8-10x16 4.7 F/400V Rubycon YK 470 F/16V Rubycon ZL, 16-ZL-470-M-T8-10x12.5 470 F/16 V Rubycon ZL 22 F/50 V 2.2 nF/250 V~ Y1 Ceramite, 440LD22 1 F

5

2

C4 C5

6 7 8

1 1 1

C6 C7 C8 C9

9 10

1 1

C10 C34 C35

1 F 100 nF/100 V

11 12 13 14 15 16

1 1 1 1 1 2

D1 D2 D3 D4 D5 D6 D7

Rectifier 380 V/1.5 A, B380C1500M STPS160A SMA BZW06-171 STTA106 LED green 1N4148 1N4148 TR5-F 250 V 500 mA, Wickmann, 370.0500.041 Jumper closed Jumper closed Jumper closed 2x10 mH 0.3 A, Radi 42 V15 2x10 mH 0.25 A, TDK UF1717V-103YR25-02 220 H series BC, Siemens Matsushita B781.8-S1224-J 10 H series BC, Siemens Matsushita B781.8-S1103-K 1mH series LBC, Siemens Matsushita B82144-A2105-J 15 3 W metal film , 2.2 k SMD 22

17 18

1 3

F1 J1 J4 J5

19

1

L1 L1

20 21 22 23 24 25

1 1 1 1 1 1

L2 L3 L5 R1 R2 R3

33/46

Demonstration board for ST7538Q Table 3.
Item

AN1714

Power supply sections (continued)
N Name R4 Descriptions

26 27 28 29

1 1 1 1

R_L6 R5 R7 TR1 TR1

10 3320 910 0.7mH, Radiohm 69E16H.1B 0.7mH, TDK SRW16ES-ExxH004 L6590

30

1

U1

Table 4.
Item 1 2 3 4 5

Powerline modem section
N 1 1 1 1 2 Name CN3 CN4 C11 C13 C14 C30 33 nF 220 V/X2
(1),

Descriptions Header 2 Header 7 EVOX RIFA, PHE840EB5330MR17
(1),

220 nF MKT

EPCOS B32529-C1224-K

10 F TANT SMD, AVX, TPSW106*016#0600 10 F TANT SMD 10 F TANT SMD, VISHAY, 293D106X_035D2_ 100 nF SMD 100 nF SMD 100 nF SMD 100 nF SMD 6.8 nF, ARCOTRONIX, R82EC1680AA5J 47 pF SMD 18 pF SMD 10 nF CERAMIC 4.7 nF MKP 5% (1), EVOX RIFA, PFR5-472J63L4 100 pF SMD 100 nF MKT
(1)

6 7

1 4

C38 C15 C16 C20 C21

8 9 10 11 12 13 14

1 1 1 1 1 1 1

C17 C18 C19 C33 C36 C37 C_R9 D8 D14

, EPCOS, B32520-C3104-K

15

2

D15 D16

P6KE6V8A P6KE6V8A SM6T6V8A Jumper closed Jumper closed

16 17

1 3

D17 J2 J3

34/46

AN1714 Table 4.
Item

Demonstration board for ST7538Q Powerline modem section (continued)
N Name J7 18 19 20 21 22 23 24 25 26 27 28 29 1 1 1 1 1 1 1 1 1 1 1 1 J6 L_C12 L4 L7 L8 R8 R10 R11 R12 R13 R14 T1 T1 T1 T1 T1 30 31 1 1 U2 X1 10 H LBC Inductor
(1)

Descriptions Jumper closed CON3 , Siemens Matsushita B82144-A2103-K , Siemens Matsushita B82144-A2223-K

22 H 10% series LBC 330 H 5% series BC

(1) (1)

, Siemens Matsushita B781.8-S1334-J 10 H SMD 4.7 M 5 1/4 Watt , 750 50 k TRIM 5 k TRIM 1 k

VACuumschmelze T60403-F4096-X046, 1.7 mH, 1:1 transformer TDK TRTT10U-E015A012, 2 mH, 1:1 transformer SECRE T15253, 1.3 mH, 1:1 transformer ETAL P2824, 1.2 mH, 1:1 transformer RADIOHM 63V192100, 2 mH, 2:1 transformer ST7538Q (TQFP44 CTI7010 044) 16 M, quartz crystal, Q 16.0-SS3-30-30/30-FU-T1

1. Values for 132.5KHz communication channel

Table 5.
Item 1 2 3 4

ST7/RS232 section
N 1 1 1 9 Name CN5 CN6 CN7 C23 C24 C25 C26 C27 C28 C29 C31 C32 Descriptions RS232 female 9 Pin CON12 ISP interface 100 nF SMD 100 nF SMD 100 nF SMD 100 nF SMD 100 nF SMD 100 nF SMD 100 nF SMD 100 nF SMD 100 nF SMD

35/46

Demonstration board for ST7538Q Table 5.
Item 5 6 7

AN1714

ST7/RS232 section (continued)
N 1 1 2 Name C22 D12 D9 D11 Descriptions 22 nF SMD LED green LED red LED red LED yellow 1N4148 SMD Jumper open Jumper closed Jumper closed Jumper closed Jumper closed R_STRIP 1 k 4resis 4.7 k SMD 47 k SMD 10 k SW pushbutton ST232B ST72C334J4 TQFP44 SMT

8 9 10

1 1 5

D10 D13 JL1 J8 J9 J10 J11

11 12 13 14 15 16 17

1 1 1 1 1 1 1

RN1 R15 R16 R17 SW1 U3 U4

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Demonstration board characterization

3

Demonstration board characterization
This chapter includes a series of tests and measurements to characterize the demonstration board. The characterization concerns the most critical aspects required by European standards which are: 1. 2. 3. Electro-conducted disturbances Immunity to narrowband conducted noise Output impedance measurement

The results of these measures show a good match and a very close value to the measures done according to the EN50065-1, EN50065-2-1 and EN50065-7 setup and procedures.

3.1

Conducted disturbance
The EN50065-1 standard describes the test setup and procedures for these kinds of tests. The measures have been done with 220 V~ and 110 V~ mains voltages. The test pattern consists of a continuous transmission of a fixed tone (symbol "0") or a repetition of random bytes. The output signal has a peak value of 118dBuV (output CISPR-16 measure of the not modulated signal) that means a 1.6Vrms of signal on the mains. The spectrum analyzer performs a peak measure instead of a quasi-peak measure. For continuous sinusoidal signals the two types of measures give the same result. Figure 29. Conducted disturbance setup

As shown by the spectrum plots the point that is usually the closest to the mask is the 2nd harmonic. The borderline condition is obtained with the 110 V~ mains supply and with the 110 kHz channel. In the 110 kHz channel case the output board filter centered at the 132.5 kHz channel produces lower attenuation of the harmonic. The other critical condition is with the 110 V~ supply. In this case the switching regulator gives a lower supply voltage. The effect is to compress the top of the output sinusoidal

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Demonstration board characterization

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signal producing higher odd harmonics. The difference is some hundreds of microvolts but considering the strong constraints of the norm they are relevant. Figure 30. Output signal spectrum, channel 132.5 kHz, mains 220 V~, fixed tone
Ch 132.5 kHz, baud 2400, dev 0,5 Continuos Transmission - Fix Tone "0"
EN50065-1 10kHz -> 150kHz (Bw = 100Hz) 150kHz -> 30MHz (Bw=10kHz)

dBuV 120.0 110.0 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10000

2nd Harmonic 54.3dBV

3rd Harmonic 47.9dBV
10 0 0 10 0 0 0 1000 0000 10 0 0000

Figure 31. Output signal spectrum, channel 132.5 kHz, mains 220 V~, random sequence
Ch 132.5 kHz, baud 2400, dev 0,5 Continuos Transmission - Random Sequences
EN50065-1 10kHz -> 150kHz (Bw = 100Hz) 150kHz -> 30MHz (Bw =10kHz)

dBuV 120.0 110.0 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10000

2nd Harmonic 54.3dBV

3rd Harmonic 47.8dBV
10 0 0 1000 000 1000 0000 10 0000 000

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Demonstration board characterization Figure 32. Output signal spectrum, channel 132.5 kHz, mains 110 V~, random sequence
Ch 132.5 kHz, baud 2400, dev 0,5 - mains 110V~ Continuos Transmission - Random Sequences
EN50065-1 10kHz -> 150kHz (Bw = 100Hz) 150kHz -> 30MHz (Bw =10kHz)

dBuV 120.0 110.0 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0

2nd Harmonic 54.0dBV

3rd Harmonic 47.2dBV
10000 10 0 0 10 0 00 10 0 000 10 0 0000

Figure 33. Output signal spectrum, channel 110 kHz, mains 220 V~, random sequence
dBuV 120.0 110.0 100.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10000
10 0 0

Ch 110 kHz, baud 2400, dev 0,5 Continuos Transmission - Random Sequences
EN50065-1 10kHz -> 150kHz (Bw = 100Hz) 150kHz -> 30MHz (Bw=10kHz)

2nd Harmonic 54.0dBV

3rd Harmonic 47.2dBV
1000 00 0 10 00 00 00 10 00 0 0 0

3.2

Narrowband conducted interference
The setup of the narrowband conducted interferences test consists of a first transmitting demonstration board controlled by a BER (Bit Error Rate) tester that generates a random bit stream. The second board demodulates the received signal that is evaluated by the linked BER tester. The noise is produced by a waveform generator and injected into the artificial network by a coupling circuit connected to a low distortion power amplifier (EN50065-2-1, 7.2.3). Two types of signal noises have been used for the test: a pure sinusoidal signal and an amplitude-modulated signal, (modulating signal 1 kHz, modulation deep 80%). The amplitude of the noise signal is decreased until the BER measured is lower than 10-3 (one error every 1000 transmitted bits). The noise measure is done disconnecting the signal source and the coupling circuits from the artificial network.

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Demonstration board characterization Figure 34. Narrowband conducted interferences setup

AN1714

The following are different measurements with a transmitted signal of 79dBuV measured at the CISPR-16 output (minus 6dB versus mains). A measure of the 110 kHz channel (signal level 85dBuV) is also present even if the receiving filter of the board is tuned on the 132.5 kHz channel. The power amplifier used represents a limit for the measure with respect to the maximum noise voltage level. In fact for the noise tones far from the channel frequency, the BER obtained is zero and the power amplifier isn't able to produce a higher sinusoidal noise. Figure 35. Signal/noise ratio for the 132.5 kHz channel, signal level 85 dBuV
Ch 132.5KHz, BAUD 2400, DEV 0.5 S = 85 dBuV, BER < 10e-3 - mains 220V~
S/N

15 10 Fix Tone 5 AM 1kHz - 80% 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 80 90 100 110 120 130 140 150 160 170 180 190 200
FREQ[KHz]

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Demonstration board characterization Figure 36. Signal/noise ratio for the 132.5 kHz channel, signal level 85 dBuV, mains 110 V~
S/N

15 10 Fix Tone 5 AM 1kHz - 80% 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 80 90 100 110 120 130 140 150 160 170 180 190 200
FREQ[KHz]

Ch 132.5KHz, BAUD 2400, DEV 0.5 S = 85 dBuV, BER < 10e-3 - mains 110V~

Figure 37. Signal/noise ratio for the 110 kHz channel, signal level 91 dBuV
S/N

20 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 80

Ch 110KHz, BAUD 2400, DEV 0.5 S = 91 dBuV, BER < 10e-3 - mains 220V~
Fix Tone AM 1kHz - 80%

90 100 110 120 130 140 150 160 170 180
FREQ[KHz]

3.3

Output impedance
The last characterization report concerns the output impedances of the application. In order to not degrade the communication network it is mandatory to guarantee a minimum value of the output impedance of each component of the system, both in the receiving and transmitting condition. In this last case impedance constraints concern only the frequency ranges of the other communication bands.

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Demonstration board characterization Figure 38. Output board impedance measurement setup

AN1714

The reference standard is the EN50065-7. To simplify the measurement, the supply of the board is obtained by a low 10 V external power supply and the impedance meter has been connected directly to the mains connector. Figure 39 and 40 show the normative mask for the home appliance band (95 kHz - 148.5 kHz). Figure 39. Output demonstration board impedances (CN1) in receiving condition
ohm 1000 Receiving Condition
EN50065-7 Z_RX

100

10

1 10 30 50 70 KHz 90 110 130 150

Figure 40. Output demonstration board impedances (CN1) in transmitting condition
ohm 1000 Transmitting Condition
EN50065-7 Z_TX

100

10

1 10 30 50 70 KHz 90 110 130 150

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Design ideas for auxiliary blocks

4
4.1

Design ideas for auxiliary blocks
Zero-crossing detector
It is possible to synchronize the beginning of the transmission with the mains voltage (phase 0). To implement this function the zero-crossing comparator has to be used and a reduced reproduction of the mains frequency (with the same phase) has to be present on the ZCin pin (#16). The maximum voltage of this pin is 5 V. In case of a nonisolated application the circuit consists of a simple resistor divider. For an isolated system a possible solution could be a mains transformer. This solution is more expensive and is suggested only if such a mains transformer is also used in the application for another purpose. It is possible to implement another isolated solution using for example an optocoupler component also. In both cases a bidirectional transil has to protect the pin from the burst and surge and a capacitor have to be added to filter high frequency noise. Figure 41. Zero-crossing coupling circuit, nonisolated solutions

ST7538Q P
ZCout 15 ZCin
16 Tx Sync 25 100 K 10 M

MAINS

N

Figure 42. Zero-crossing coupling circuit, isolated solutions

ST7538Q

ZCout 15
100 K

ZCin
16 Tx Sync 25 100 K

50 1

MAINS

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Documentation

AN1714

Appendix A
4.2

Documentation

ST7538Q

ST7538Q datasheet Demonstration board user manual EHS Booklet

4.3

L6590 integrated power supply

L6590 datasheet Application note AN1261 Application note AN1262 Application note AN1523

4.4

ST7 microprocessor
ST72 series datasheet

4.5

Surge and burst protections

Protection guide Application note AN317 Application note AN576

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References

5

References
1. 2. SGS-THOMSON - Power Line Modem & Applications data book - September 1994 CENELEC, European Committee for Electrotechnical Standardization - EN 50065-1, Signaling on low-voltage electrical installations in the frequency range 3 kHz to 148,5 kHz. Part 1: General requirements, frequency bands and electromagnetic disturbances - July 2001 CENELEC, European Committee for Electrotechnical Standardization - EN 50065-4-2, Signaling on low-voltage electrical installations in the frequency range 3 kHz to 148,5 Khz. Part 4-2: Low voltage decoupling filters- Safety requirements - August 2001 CENELEC, European Committee for Electrotechnical Standardization - EN 50065-7, Signaling on low-voltage electrical installations in the frequency range 3 kHz to 148,5 Khz. Part 7: Equipment impedance - November 2001 CENELEC, European Committee for Electrotechnical Standardization - prEN 50065-21, Signaling on low-voltage electrical installations in the frequency range 3 kHz to 148,5 kHz. Part 2-1: Immunity requirements for mains Communications Equipment and systems operating in the range of frequencies 95 kHz to 148,5 kHz and intended for use in Residential, Commercial and Light Industrial Environments - 1999 IEC, International Electrotechnical Commission, International Special Committee On Radio Interferences - CISPR 16-1, Specification for radio disturbance and immunity measuring apparatus and methods. Part 1: Radio disturbance and immunity measuring apparatus - first edition, August 1993 EHSA, European Home System Association - EHS specifications, version 1.3a May 2001.

3.

4.

5.

6.

7.

6

Revision history
Table 6.
Date 21-Jun-2006

Document revision history
Revision 3 Minor text changes
Section 1.2 added Section 2.4 modified ST7538 replaced by ST7538Q Content reworked to improve readability, no content changes

Changes

27-Feb-2008

4

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