ST7LITE3xF2
8-bit MCU with single voltage Flash, data EEPROM, ADC, timers, SPI, LINSCITM
Features
Memories 8 Kbytes program memory: single voltage extended Flash (XFlash) Program memory with read-out protection, In-Circuit Programming and In-Application programming (ICP and IAP), data retention: 20 years at 55C. 384 bytes RAM 256 bytes data EEPROM with read-out protection. 300K write/erase cycles guaranteed, data retention: 20 years at 55C. Clock, Reset and Supply Management Enhanced reset system Enhanced low voltage supervisor (LVD) for main supply and an auxiliary voltage detector (AVD) with interrupt capability for implementing safe power-down procedures Clock sources: Internal RC 1% oscillator, crystal/ceramic resonator or external clock Optional x4 or x8 PLL for 4 or 8 MHz internal clock Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt I/O Ports Up to 15 multifunctional bidirectional I/O lines 7 high sink outputs 5 Timers Configurable Watchdog Timer Two 8-bit Lite Timers with prescaler, 1 realtime base and 1 input capture Two 12-bit Auto-reload Timers with 4 PWM outputs, input capture and output compare functions
QFN20 SO20 DIP20 2 Communication Interfaces Master/slave LINSCITM asynchronous serial interface SPI synchronous serial interface Interrupt Management 10 interrupt vectors plus TRAP and RESET 12 external interrupt lines (on 4 vectors) A/D Converter 7 input channels 10-bit resolution Instruction Set 8-bit data manipulation 63 basic instructions with illegal opcode detection 17 main addressing modes 8 x 8 unsigned multiply instructions Development Tools Full hardware/software development package DM (Debug module)
Table 1. Device summary
Features Program memory - bytes RAM (stack) - bytes Data EEPROM - bytes Peripherals Operating Supply CPU Frequency Operating Temperature Packages ST7LITE30F2 ST7LITE35F2 ST7LITE39F2 8K 384 (128) 256 Lite Timer, Autoreload Timer, SPI, LINSCI, 10-bit ADC 2.7V to 5.5V Up to 8Mhz Up to 8Mhz (w/ ext OSC up to 16MHz (w/ ext OSC up to 16MHz) and int 1MHz RC 1% PLLx8/4MHz) -40C to +125C SO20 300", DIP20, QFN20
Rev. 9
November 2007 1/173
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Table of Contents
ST7LITE3xF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 4.3 4.4 4.5 4.6 4.7 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 5.3 5.4 5.5 5.6 5.7 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 6.3 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 7.3 7.4 7.5 7.6 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2 8.3 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2 9.3 9.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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9.5 9.6 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2 DUAL 12-BIT AUTORELOAD TIMER 3 (AT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . . 90 11.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS . . . . . . . . . . . . 146 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 155 13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.2 THERMAL CHARACTERISTICS 160 15 DEVICE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 163 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 16.1 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 169
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16.2 LINSCI LIMITATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
To obtain the most recent version of this datasheet, please check at www.st.com
Please also pay special attention to the Section "KNOWN LIMITATIONS" on page 169.
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ST7LITE3xF2
1 INTRODUCTION
The ST7LITE3 is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7LITE3 features FLASH memory with byte-by-byte In-Circuit Programming (ICP) and InApplication Programming (IAP) capability. Under software control, the ST7LITE3 device can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly Figure 1. General Block Diagram efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. For easy reference, all parametric data are located in section 13 on page 131. The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.
Int. 1% RC 1MHz
PLL x 8 or PLL X4
CLKIN /2 OSC1 OSC2
Ext. OS C 1MHz to 16MHz
12-Bit Auto-Reload TIMER 2 8-Bit LITE TIMER 2 Internal CLOCK PA7:0 (8 bits) PB6:0 (7 bits)
PORT A PORT B ADC
ADDRESS AND DATA BUS
LVD VDD VSS RESET POWER SUPPLY CONTROL 8-BIT CORE ALU
Debug Module SPI
LINSCI PROGRAM MEMORY (8K Bytes)
WDG
RAM (384 Bytes)
DATA EEPROM ( 256 Bytes)
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2 PIN DESCRIPTION
Figure 2. 20-Pin QFN Package Pinout
OSC1/CLKIN
20 19 18
17 16 15
O SC2
V DD
VSS
RESET S S /AI N 0/PB 0 SCK/AIN1/PB1 MISO/A IN2/PB2 MOSI/AIN3/PB3 CLKIN/AIN4/PB4
1 2 3 4 5 6 7 8 9 10 ei2 ei2 ei1 ei3 ei0
PA0 (HS)/LTIC PA1 (HS)/ATIC PA2 (HS)/ATPWM0 PA3 (HS)/ATPWM1 PA4 (HS)/ATPWM2 PA5 (HS)/ATPWM3/ICCDATA
14 13 12 11
TDO/PA7(HS)
MCO/ICCCLKBREAK/PA6
RDI/AIN6/PB6
AIN5/PB5
(HS) 20mA High sink capability eix associated external interrupt vector
Figure 3. 20-Pin SO and DIP Package Pinout
VSS V DD RESET S S /AIN0/PB0 SCK/AIN1/PB1 MISO/AIN2/PB2 M OS I / A I N 3 / P B 3 CLKIN/AIN4/PB4 AIN5/PB5 RDI/AIN6/PB6 OSC1/CLKIN O SC2 PA0 (HS)/LTIC PA1 (HS)/ATIC PA2 (HS)/ATPWM0 PA3 (HS)/ATPWM1 PA4 (HS)/ATPWM2 PA5 (HS)/ATPWM3/ICCDATA PA6/MCO/ICCCLK/BREAK PA7 (HS)/TDO
1 2 3 4 5 6 7 8 9 10 ei2 ei2 ei1 ei3 ei0
20 19 18 17 16 15 14 13 12 11
(HS) 20mA high sink capability eix associated external interrupt vector
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PIN DESCRIPTION (Cont'd) Legend / Abbreviations for Table 2: Type: I = input, O = output, S = supply In/Output level: CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog Output: OD = open drain, PP = push-pull The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state. Table 2. Device Pin Description
Level SO20/DIP20 Type Input Pin Name Output QFN20 Port / Control Input fl oat wpu ana int Main O utput Function (after reset) OD PP Ground Main power supply X X Top priority non maskable interrupt (active low) ADC Analog Input 0 or SPI Slave Select (active low) Caution: No negative current injection allowed on this pin. For details, refer to section 13.2.2 on page 132 ADC Analog Input 1 or SPI Serial Clock Caution: No negative current injection allowed on this pin. For details, refer to section 13.2.2 on page 132 ADC Analog Input 2 or SPI Master In/ Slave Out Data ADC Analog Input 3 or SPI Master Out / Slave In Data ADC Analog Input 4 or External clock input ADC Analog Input 5 ADC Analog Input 6 or LINSCI Input LINSCI Output Alternate Function
19 20 1
1 2 3
VSS 1) VDD
1)
S S I/O CT
RESE T
2
4
PB0/AIN0/SS
I/O
CT
X ei3
X
X
X
Port B0
3
5
PB1/AIN1/SCK I /O PB2/AIN2/ MISO PB3/AIN3/ MO SI PB4/AIN4/ CLKIN** PB5/ A IN5
CT
X
X
X
X
Port B1
4 5 6 7 8 9
6 7 8 9
I/O I/O I/O I /O I/O
CT CT CT CT CT
X X X X ei2 X X X X ei2
X X X X X
X X X X X X
X X X X X X
Port B2 Port B3 Port B4 Port B5 Port B6 Port A7
10 PB6/AIN6/RDI 11 PA7/TDO
I/O CT HS
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Level SO20/DIP20 Type O u tput QFN 20 Input Pin Name
Port / Control Input float w pu ana int Main O utput Function (after reset) OD PP Alternate Function
Main Clock Output or In Circuit Communication Clock or External BREAK PA6 /MCO/ 1 0 1 2 IC CCLK/ BREA K Caution: During normal operation this pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up. Auto-Reload Timer PWM3 or In Circuit Communication Data Auto-Reload Timer PWM2 Auto-Reload Timer PWM1 Auto-Reload Timer PWM0 Auto-Reload Timer Input Capture Lite Timer Input Capture
I/O
CT
X ei1
X
X
Port A6
11 13
PA5 /ATPWM3/ I/O CT HS IC CDATA I / O CT H S I / O CT H S I / O CT H S I /O C T H S I / O CT H S O I
X X X X X X X ei0
X X X X X X
X X X X X X
Port A5 Port A4 Port A3 Port A2 Port A1 Port A0
12 14 PA4/ATPWM 2 13 15 PA3/ATPWM 1 14 16 PA2/ATPWM 0 15 17 PA1/ATIC 16 18 PA0/LTIC 17 19 OSC 2 18 20 OSC 1/CLKIN
Resonator oscillator inverter output Resonator oscillator inverter input or External clock input
Notes: 1. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground. 2. For input with interrupt possibility "eix" defines the associated external interrupt vector which can be assigned to one of the I/O pins using the EISR register. Each interrupt can be either weak pull-up or floating defined through option register OR.
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3 REGISTER & MEMORY MAP
As shown in Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM, 256 bytes of data EEPROM and 8 Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 180h to 1FFh. The highest address bytes contain the user reset and interrupt vectors. Figure 4. Memory Map
0080h
The Flash memory contains two sectors (see Figure 4) mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh). The size of Flash Sector 0 and other device options are configurable by Option byte. IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reseved area can have unpredictable effects on the device.
Short Addressing RAM (zero page)
0000h 007Fh 0080h 01FFh 0200h
HW Registers (see Table 3) RAM (384 Bytes) Reserved
00FFh 0100h
16-bit Addressing R AM
017Fh 0180h
128 By tes S tac k
01FFh DEE0h
0FFFh 1000h 10FFh 1100h
Data EEPROM (256 Bytes)
DEE1h DEE2h
RCCRH0 RCCRL0 RCCRH 1
DEE3h
Reserved
DFFFh E000h
8K FLASH PROGRAM MEMORY
DEE4h
RCCRL1
see section 7.1 on page 23 and Note 1)
E000h
Flash Memory (8K)
FFDFh FFE0h
FBFFh FC00h FFFFh
7 Kbytes SECTOR 1 1 Kbyte SECTOR 0
Interrupt & Reset Vectors (see Table 6)
FFFFh
1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes containing also the RC calibration values which are read-accessible only in user mode. If all the EEPROM data or Flash space (including the RC calibration values locations) has been erased (after the read out protection removal), then the RC calibration values can still be obtained through these addresses.
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Table 3. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h to 002Dh 002Eh 0002Fh 00030h WD G FLASH EE PROM W DGCR FC SR E ECSR LTC SR2 LTA RR L T C NT R LTC SR1 LTICR A T CSR C NT R1H C NT R1L A T R1H A T R1L P WM C R P WM 0 C S R P WM 1 C S R P WM 2 C S R P WM 3 C S R D CR0H D CR0L D CR1H D CR1L D CR2H D CR2L D CR3H D CR3L A T ICRH A T ICRL A T CSR2 BREAKCR A T R2H A T R2L D T GR Block Register Label P ADR P ADDR P A OR P BDR P BDDR P B OR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Port B Data Register Port B Data Direction Register Port B Option Register Reserved area (2 bytes) Lite Timer Control/Status Register 2 Lite Timer Auto-reload Register Lite Timer Counter Register Lite Timer Control/Status Register 1 Lite Timer Input Capture Register Timer Control/Status Register Counter Register 1 High Counter Register 1 Low Auto-Reload Register 1 High Auto-Reload Register 1 Low PWM Output Control Register PWM 0 Control/Status Register PWM 1 Control/Status Register PWM 2 Control/Status Register PWM 3 Control/Status Register PWM 0 Duty Cycle Register High PWM 0 Duty Cycle Register Low PWM 1 Duty Cycle Register High PWM 1 Duty Cycle Register Low PWM 2 Duty Cycle Register High PWM 2 Duty Cycle Register Low PWM 3 Duty Cycle Register High PWM 3 Duty Cycle Register Low Input Capture Register High Input Capture Register Low Timer Control/Status Register 2 Break Control Register Auto-Reload Register 2 High Auto-Reload Register 2 Low Dead Time Generator Register Reserved area (8 bytes) Watchdog Control Register Flash Control/Status Register Data EEPROM Control/Status Register 7Fh 00h 00h R/W R/W R/W 0Fh 00h 00h 0x00 00x0b xxh 0x00 0000b 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 03h 00h 00h 00h 00h R/W R/W Read Only R/W Read Only R/W Read Only Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only Read Only R/W R/W R/W R/W R/W Reset Status FFh1 ) 00h 40h FFh 1) 00h 00h Remarks R/W R/W R/W R/W R/W R / W2 )
Port A
Port B
LITE TIMER 2
AU TOR E L OA D TIMER 3
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Address 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh to 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h to 007Fh
Block
Register Label SPIDR SPICR SPICSR A DCCSR A DCDRH A DCDRL E ICR M CCSR R CCR SICSR
Register Name SPI Data I/O Register SPI Control Register SPI Control Status Register A/D Control Status Register A/D Data Register High A/D control and Data Register Low External Interrupt Control Register Main Clock Control/Status Register RC oscillator Control Register System Integrity Control/Status Register Reserved area (1 byte)
Reset Status xxh 0xh 00h 00h xxh x0h 00h 00h FFh 0110 0xx0b
Remarks R/W R/W R/W R/W Read Only R/W R/W R/W R/W R/W
S PI
ADC ITC MCC Clock and Reset
ITC
EISR
External Interrupt Selection Register Reserved area (3 bytes)
00h
R/W
LINSCI (LIN Master/Slave)
SCISR SCIDR SCIBRR S C ICR1 S C ICR2 S C ICR3 SCIERPR SCIETPR
SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Control Register 3 SCI Extended Receive Prescaler Register SCI Extended Transmit Prescaler Register Reserved area (1 byte)
C0h xxh 00xx xxxxb xxh 00h 00h 00h 00h
Read Only R/W R/W R/W R/W R/W R/W R/W
AW U
A WU P R A WU C S R D MC R D MS R D MB K 1 H D MB K 1 L D MB K 2 H D MB K 2 L
AWU Prescaler Register AWU Control/Status Register DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low Reserved area (47 bytes)
FFh 00h 00h 00h 00h 00h 00h 00h
R/W R/W R/W R/W R/W R/W R/W R/W
D M3 )
Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For a description of the DM registers, see the ST7 ICC Reference Manual.
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4 FLASH PROGRAM MEMORY
4.1 Introduction The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming. The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features
ICP (In-Circuit Programming) IAP (In-Application Programming) ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Sector 0 size configurable by option byte Read-out and write protection
4.3 PROGRAMMING MODES The ST7 can be programmed in three different ways: Insertion in a programming tool. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased. In-Circuit Programming. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased without removing the device from the application board. In-Application Programming. In this mode, sector 1 and data EEPROM (if present) can be programmed or erased without removing
the device from the application board and while the application is running. 4.3.1 In-Circuit Programming (ICP) ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps: Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. Download ICP Driver code in RAM from the ICCDATA pin Execute ICP Driver code in RAM to program the FLASH memory Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In Application Programming (IAP) This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
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FLASH PROGRAM MEMORY (Cont'd) 4.4 ICC INTERFACE ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are: RESET: device reset VSS: device power supply ground Figure 5. Typical ICC Interface
PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE (See Note 3) OPTIONAL (See Note 4) 9 10 7 8 5 6 3 4 1 2 APPLICATION RESET SOURCE See Note 2 APPLICATION BOARD
ICCCLK: ICC output serial clock pin ICCDATA: ICC input serial data pin CLKIN/PB4: main clock input for external source VDD: application board power supply (optional, see Note 3)
APPLICATION POWER SUPPLY (See Note 5) CLKIN/PB4
See Note 1 and caution APPLICATION I/O See Note 1 RESET ICCCLK ICCDATA VDD
ST7
Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented if another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin
must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 must be connected to the PB4 pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability must have OSC2 grounded in this case. 5. With any programming tool, while the ICP option is disabled, the external clock must be provided on PB4. 6. In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. For ST7LITE30 devices which do not support the internal RC oscillator, the "option byte disabled" mode must be used (35pulse ICC mode entry, clock provided by the tool). Caution: During normal operation ICCCLK pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This avoids entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset puts it back in input pull-up.
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FLASH PROGRAM MEMORY (Cont'd) 4.5 Memory Protection There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually. 4.5.1 Read out Protection Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Both program and data E2 memory are protected. In flash devices, this protection is removed by reprogramming the option. In this case, both program and data E2 memory are automatically erased and the device can be reprogrammed. Read-out protection selection is enabled and removed through the FMP_R bit in the option byte. 4.5.2 Flash Write/Erase Protection Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to E2 data. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable. Write/erase protection is enabled through the FMP_W bit in the option byte. 4.6 Related Documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.7 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read / Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh)
7 0 0 0 0 0 OPT LAT 0 PGM
Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing operations. When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.
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5 DATA EEPROM
5.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 5.2 MAIN FEATURES
Up to 32 Bytes programmed in the same cycle EEPROM mono-voltage (charge pump) Chained erase and programming cycles Internal control of the global programming cycle duration WAIT mode management Readout protection
Figure 6. EEPROM Block Diagram
HIGH VOLTAGE PUMP
EECSR
0
0
0
0
0
0
E2LAT E2PGM
ADDRESS DECODER
4
ROW DECODER
EEPROM MEMORY MATRIX (1 ROW = 32 x 8 BITS)
128 DATA MULTIPLEXE R 4
128 32 x 8 BITS DATA LATCHES
4
ADDRESS BUS
DATA BUS
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DATA EEPROM (Cont'd) 5.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these different memory access modes. Read Operation (E2LAT=0) The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared. On this device, Data EEPROM can also be used to execute machine code. Take care not to write to the Data EEPROM while executing from it. This would result in an unexpected code being executed. Write Operation (E2LAT=1) To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs, Figure 7. Data EEPROM Programming Flowchart the value is latched inside the 32 data latches according to its address. When PGM bit is set by the software, all the previous bytes written in the data latches (up to 32) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five Least Significant Bits of the address can change. At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously. Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit. It is not possible to read the latched data. This note is ilustrated by the Figure 9.
READ MODE E2LAT=0 E2PGM=0
WRITE MODE E2LAT=1 E2PGM=0
READ BYTES IN EEPROM AREA
WRITE UP TO 32 BYTES IN EEPROM AREA (with the same 11 MSB of the address)
START PROGRAMMING CYCLE E2LAT=1 E2PGM=1 (set by software)
0 CLEARED BY HARDWARE
E2LAT
1
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DATA EEPROM (Cont'd) Figure 8. Data E2PROM Write Operation
Row / Byte R OW DEFINITION 0 1 ... N Read operation impossible 0 1 2 3 ... 30 31 Physical Address
00h...1Fh 20h...3Fh Nx20h...Nx20h+1Fh
Read operation possible
Byte 1
Byte 2 PH ASE 1
Byte 32
Programming cycle PHASE 2
Writing data latches E2LAT b it
Set by USER application
Waiting E2PGM and E2LAT to fall
Cleared by hardware
E2PG M b it
Note: If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed.
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DATA EEPROM (Cont'd) 5.4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-HALT mode.The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode. Active-Halt mode Refer to Wait mode. Halt mode The DATA EEPROM immediately enters HALT mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted. 5.5 ACCESS ERROR HANDLING If a read access occurs while E2LAT=1, then the data bus will not be driven. If a write access occurs while E2LAT=0, then the data on the bus will not be latched. If a programming cycle is interrupted (by RESET action), the integrity of the data in memory is not guaranteed. 5.6 Data EEPROM Read-out Protection The read-out protection is enabled through an option bit (see section 15.1 on page 161). When this option is selected, the programs and data stored in the EEPROM memory are protected against read-out (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the Option Byte, the entire Program memory and EEPROM is first automatically erased. Note: Both Program Memory and data EEPROM are protected using the same option bit.
Figure 9. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE INTERNAL PROGRAMMING VOLTAGE ERASE CYCLE WRITE OF DATA LATCHES WRITE CYCLE READ OPERATION POSSIBLE
tPROG
LAT
P GM
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DATA EEPROM (Cont'd) 5.7 REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EECS R) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 0 E2LAT E2PGM
Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared. 0: Read mode 1: Write mode Bit 0 = E2PGM Programming control and status This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware. 0: Programming finished or not yet started 1: Programming cycle is in progress Note: if the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed Table 4. DATA EEPROM Register Map and Reset Values
Address (Hex.) 0030h Register Label E ECSR Reset Value 0 0 0 0 0 0 7 6 5 4 3 2 1 E2LAT 0 0 E2PGM 0
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6 CENTRAL PROCESSING UNIT
6.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 MAIN FEATURES
63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt
6.3 CPU REGISTERS The six CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions. Figure 10. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0
Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value
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CPU REGISTERS (cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
7 1 1 1 H I N Z 0 C
logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test inst ructions. Bit 0 = C Carry/borrow This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. CPU REGISTERS (Cont'd) STACK POINTER (SP) Read/Write Reset Value: 01FFh
15 0 7 1 SP 6 SP5 SP4 SP3 SP2 S P1 0 0 0 0 0 0 8 1 0 SP0
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11). Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an
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MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instrucFigure 11. Stack Manipulation Example
CALL Subroutine @ 0180h Interrupt Event P USH Y
tions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
PO P Y
IRET
RET or RSP
SP SP CC A X PC H SP PCH @ 01FFh PCL P CL PCH PCL Y CC A X PCH PCL PCH PC L SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 01FFh Stack Lower Address = 0180h
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7 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. Main features
tion code. This area cannot be erased or programmed by any ICC operation. For compatibility reasons with the SICSR register, CR[1:0] bits are stored in the 5th and 6th position of DEE1 and DEE3 addresses. Note: In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. For ST7LITE30 devices which do not support the internal RC oscillator, the "option byte disabled" mode must be used (35-pulse ICC mode entry, clock provided by the tool). See "ELECTRICAL CHARACTERISTICS" on page 131. for more information on the frequency and accuracy of the RC oscillator. To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device These bytes are systematically programmed by ST, including on FASTROM devices. Consequently, customers intending to use FASTROM service must not use these bytes. RCCR0 and RCCR1 calibration values will not be erased if the read-out protection bit is reset after it has been set . See "Read out Protection" on page 14. Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN1324 for information on how to calibrate the RC frequency using an external reference signal. 7.2 PHASE LOCKED LOOP The PLL can be used to multiply a 1MHz frequency from the RC oscillator or the external clock by 4 or 8 to obtain fOSC of 4 or 8 MHz. The PLL is enabled and the multiplication factor of 4 or 8 is selected by 2 option bits. The x4 PLL is intended for operation with VDD in the 2.7V to 3.3V range The x8 PLL is intended for operation with VDD in the 3.3V to 5.5V range Refer to Section 15.1 for the option byte description. If the PLL is disabled and the RC oscillator is enabled, then fOSC = 1MHz.
Clock Management 1 MHz internal RC oscillator (enabled by option byte, available on ST7LITE35 and ST7LITE39 devices only) 1 to 16 MHz or 32kHz External crystal/ceramic resonator (selected by option byte) External Clock Input (enabled by option byte) PLL for multiplying the frequency by 8 or 4 (enabled by option byte) Reset Sequence Manager (RSM) System Integrity Management (SI) Main supply Low voltage detection (LVD) with reset generation (enabled by option byte) Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply (enabled by option byte)
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT The device contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage range (4.5V-5.5V). It must be calibrated to obtain the frequency required in the application. This is done by software writing a 8-bit calibration value in the RCCR (RC Control Register) and in the bits [6:5] in the SICSR (SI Control Status Register). Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in EEPROM for 3V and 5V VDD supply voltages at 25C, as shown in the following table.
RCCR RCCRH0 R CCRL0 R CCRH1 RCCRL1 Conditions V DD= 5 V T A =25C f RC=1MHz VDD=3.3V T A =25C f RC=1MHz ST7LITE3 Addresses DEE0h 1) (CR[9:2] bits) DEE1h 1) (CR[1:0] bits) DEE2h 1) (CR[9:2] bits) DEE3h 1) (CR[1:0] bits)
1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area of non-volatile memory. They are read-only bytes for the applica-
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If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock. Figure 12. PLL Output Frequency Timing Diagram LOCKED bit set 4/8 x input freq. tSTAB
7.3 REGISTER DESCRIPTION MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR ) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0
MCO
0
SMS
Bits 7:2 = Reserved, must be kept cleared. Output freq. t LOCK t STARTUP Bit 1 = MCO Main Clock Out enable This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock. 0: MCO clock disabled, I/O port free for general purpose I/O. 1: MCO clock enabled. Bit 0 = SMS Slow Mode select This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock fOSC or fOSC/32. 0: Normal mode (fCPU = fOSC 1: Slow mode (fCPU = fOSC/32) RC CONTROL REGISTER (RCCR) Read / Write Reset Value: 1111 1111 (FFh)
7 CR9 CR8 CR7 CR 6 CR5 CR4 CR3 0 CR2
t When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs the clock after a delay of tSTARTUP. When the PLL output signal reaches the operating frequency, the LOCKED bit in the SICSCR register is set. Full PLL accuracy (ACCPLL) is reached after a stabilization time of tSTAB (see Figure 12 and 13.3.4Internal RC Oscillator and PLL) Refer to section 7.6.4 on page 34 for a description of the LOCKED bit in the SICSR register.
Bits 7:0 = CR[9:2] RC Oscillator Frequency Adjustment Bits These bits must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. The application can store the correct value for each voltage range in EEPROM and write it to this register at start-up. 00h = maximum available frequency FFh = lowest available frequency These bits are used with the CR[1:0] bits in the SICSR register. Refer to section 7.6.4 on page 34 Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h.
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Figure 13. Clock Management Block Diagram
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2
RCCR
CR1
CR0
SICS R CLKIN/2 (Ext Clock) 8MHz PLL 1MHz -> 8MHz PLL 1MHz -> 4MHz 4MHz OSC Option bit RC OSC PLL Clock
Tunable 1% RC Oscillator 1MHz O S C R A N GE [ 2 : 0 ] Option bits CLKIN CLKIN fCLKIN CLKIN /2 DIVIDER
fOSC
PLLx4x8
OSC,PLLOFF, OSCRANGE[2:0] Option bits
CLKIN/ O SC1 O SC2
OSC 1-16 MHZ or 32kHz
/2 DIVIDER
Crystal OSC /2
8-BIT LITE TIMER 2 COUNTER fOSC /32 DIVIDER /32 fOSC/32 1
fLTIMER (1ms timebase @ 8 MHz fOSC)
fCPU TO CPU AND PERIPHER ALS
fOSC
0
MCO SMS MCCSR fCPU M CO
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7.4 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multioscillator block (1 to 16MHz or 32kHz): an external source 5 crystal or ceramic resonator oscillators an internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 5. Refer to the electrical characteristics section for more details. External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Note: when the Multi-Oscillator is not used, PB4 is selected by default as external clock. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to section 15.1 on page 161 for more details on the frequency ranges). In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Internal RC Oscillator In this mode, the tunable 1%RC oscillator is used as main clock source. The two oscillator pins have to be tied to ground. The calibration is done through the RCCR[7:0] and SICSR[6:5] registers. Table 5. ST7 Clock Sources
Hardware Configuration
External Clock
ST7 OS C1 OSC 2
EX TERNAL SO URCE
Crystal/Ceramic Resonators
ST7 OSC 1 OSC2
CL 1
LOA D CAPA CITO RS
CL 2
Internal R C Oscillator
ST7 OSC1 OSC2
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7.5 RESET SEQUENCE MANAGER (RSM) 7.5.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 15: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 12.2.1 on page 128 for further details . These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 14: Active Phase depending on the RESET source 256 or 4096 CPU clock cycle delay (see table below) RESET vector fetch Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior. The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte: The RESET vector fetch phase duration is 2 clock c ycles.
Clock Source Internal RC Oscillator External clock (connected to CLKIN pin) External Crystal/Ceramic Oscillator (connected to OSC1/OSC2 pins) CPU clock cycle delay 256 256 4096
If the PLL is enabled by option byte, it outputs the clock after an additional delay of tSTARTUP (see Figure 12). Figure 14. RESET Sequence Phases
RESET
Active Phase INTERNAL RESET 256 or 4096 CLOCK CYCLES FETCH VECTOR
7.5.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 16). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.
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Figure 15. Reset Block Diagram
VDD
RO N
RESET
Filter INTERNAL RESET
PULSE GENERATOR
WATCHDOG RESET ILLEGAL OPCODE RESET1) LVD RESET
Note 1: See "Illegal Opcode Reset" on page 128. for more details on illegal opcode reset conditions.
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RESET SEQUENCE MANAGER (Cont'd) The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 7.5.3 External Power-On RESET If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 7.5.4 Internal Low Voltage Detector (LVD) R ESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: Power-On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD
Figure 16. RESET Sequences VDD
VIT+(LVD) VIT-(LVD)
LVD RESET
EXTERNAL RESET
WATCHDOG RESET
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
th(RSTL)in
EXTERNAL RESET SOURCE
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH
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7.6 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register. Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to section 12.2.1 on page 128 for further details . 7.6.1 Low Voltage Detector (LVD) The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: VIT+(LVD)when VDD is rising VIT-(LVD) when VDD is falling The LVD function is illustrated in Figure 17. The voltage threshold can be configured by option byte to be low, medium or high. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD), the MCU can only be in two modes: under full software control in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD allows the device to be used without any external RESET circuitry. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 99 on page 154 and note 4. The LVD is an optional function which can be selected by option byte. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.
Figure 17. Low Voltage Detector vs Reset
VDD
Vhys V I T + (LVD) VIT-(LVD)
RESET
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Figure 18. Reset and Supply Management Block Diagram
WATCHDOG TIMER (WDG)
STATUS FLAG
SYSTEM INTEGRITY MANAGEMENT RESET SEQUENCE RESET MANAGER (RSM) SICSR
WDGRF LOCKED LVDRF AVDF AVDIE
AVD Interrupt Request
LOW VOLTAGE VSS VDD DETECTOR (LVD)
AUXILIARY VOLTAGE DETECTOR (AVD)
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.6.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply voltage (VAVD). The VIT-(AVD) reference value for falling voltage is lower than the VIT+(AVD) reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only. Caution: The AVD functions only if the LVD is enFigure 19. Using the AVD to Monitor VDD VDD Early Warning Interrupt (Power has dropped, MCU not not yet in reset)
Vh y s t
abled through the option byte. 7.6.2.1 Monitoring the VDD Main Supply The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see section 15.1 on page 161). If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(LVD) or VIT-(AVD) threshold (AVDF bit is set). In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 19.
VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD)
AVDF bit AVD INTERRUPT REQUES T IF AVDIE bit = 1
0
1
RES ET
1
0
INTERRUPT Cleared by reset
INTERRUPT Cleared by hardware
LVD RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.6.3 Low Power Modes
Mode WAIT Description No effect on SI. AVD interrupts cause the device to exit from Wait mode. The SICSR register is frozen. The AVD becomes inactive and the AVD interrupt cannot be used to exit from Halt mode. Interrupt Event AVD event Enable Event Control Flag Bit AVDF A VDIE Exit from Wait Yes Exit from Halt No
set and the interrupt mask in the CC register is reset (RIM instruction).
H AL T
7.6.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.6.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read / Write Bit 1 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. Reset Value: 0110 0xx0 (6xh) If the AVDIE bit is set, an interrupt request is generated when the AVDF bit is set. Refer to Figure 7 0 19 and to Section 7.6.2.1 for additional details. 0: VDD over AVD threshold WDG 0 CR1 CR0 LOCKED LVDRF AVDF AVDIE 1: VDD under AVD threshold RF Bit 7 = Reserved, must be kept cleared. Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. Refer to section 7.3 on page 24 Bit 4 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (by reading SICSR register) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.
RESET Sources External RESET pin Watchdog LVD LVD RF 0 0 1 WDG RF 0 1 X
Bit 0 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.
Bit 3 = LOCKED PLL Locked Flag This bit is set by hardware. It is cleared only by a power-on reset. It is set automatically when the PLL reaches its operating frequency. 0: PLL not locked 1: PLL locked Bit 2 = LVDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.
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8 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: Maskable hardware interrupts as listed in the "interrupt mapping" table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 20. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. The I bit of the CC register is set to prevent additional interrupts. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit is cleared and the main program resumes. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping table). 8.1 NON MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It is serviced according to the flowchart in Figure 20. 8.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the HALT low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described in the I/O ports section), a low level on an I/O pin, configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity. 8.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: The I bit of the CC register is cleared. The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: Writing "0" to the corresponding bit in the status register or Access to the status register while the flag is set followed by a read or write of an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (cont'd) Figure 20. Interrupt Processing Flowchart
FROM RESET I BIT SET? Y N
N
INTERRUPT PENDING? Y
FETCH NEXT INSTRUCTION
N
IRET? Y
STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT
Table 6. Interrupt Mapping
N Source Block R E S ET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 LITE TIMER S PI AT TIMER AW U e i0 ei1 ei2 ei3 Reset Software Interrupt 7 Interrupt External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 LTCSR 2 SCICR1/ S C ICR2 SICSR PW MxCSR or ATCSR ATCSR LTCSR LTCSR SP ICSR ATCS R2 Lowest Priority no no no no yes2) no yes2) yes no N/A yes Description Register Label N/A AWU CSR Priority Order Exit from HALT yes Highest Priority no yes1) Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
LITE TIMER LITE TIMER RTC2 interrupt LINSCI SI AT TIMER LINSCI Interrupt AVD interrupt AT TIMER Output Compare Interrupt or Input Capture Interrupt AT TIMER Overflow Interrupt LITE TIMER Input Capture Interrupt LITE TIMER RTC1 Interrupt SPI Peripheral Interrupts AT TIMER Overflow Interrupt 2
Note 1: This interrupt exits the MCU from "Auto Wake-up from Halt" mode only. Note 2: These interrupts exit the MCU from "ACTIVE-HALT" mode only.
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INTERRUPTS (Cont'd) EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read / Write Reset Value: 0000 0000 (00h)
7 IS31 IS30 IS21 IS20 IS11 IS10 IS01 0 IS00
EXTERNAL INTERRUPT SELECTION REGISTER (EISR) Read / Write Reset Value: 0000 0000 (00h)
7 ei31 ei30 ei21 ei20 ei11 ei10 ei01 0 ei00
Bit 7:6 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei3 (Port B0) according to Table 7. Bit 5:4 = IS2[1:0] ei2 sensitivity These bits define the interrupt sensitivity for ei2 (Port B3) according to Table 7. Bit 3:2 = IS1[1:0] ei1 sensitivity These bits define the interrupt sensitivity for ei1 (Port A7) according to Table 7. Bit 1:0 = IS0[1:0] ei0 sensitivity These bits define the interrupt sensitivity for ei0 (Port A0) according to Table 7. Note: These 8 bits can be written only when the I bit in the CC register is set. Table 7. Interrupt Sensitivity Bits
Bit 7:6 = ei3[1:0] ei3 pin selection These bits are written by software. They select the Port B I/O pin used for the ei3 external interrupt according to the table below. External Interrupt I/O pin selection
ei31 0 0 1 1 ei30 0 1 0 1 I/O Pin No interrupt * PB0 PB1 PB2
* Reset State Bit 5:4 = ei2[1:0] ei2 pin selection These bits are written by software. They select the Port B I/O pin used for the ei2 external interrupt according to the table below. External Interrupt I/O pin selection
ei21 ei20 0 1 0 1 I/O Pin No interrupt * PB3 PB5 PB6
ISx1 ISx0 0 0 1 1 0 1 0 1
External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
0 0 1 1
.
* Reset State
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INTERRUPTS (Cont'd) Bit 3:2 = ei1[1:0] ei1 pin selection These bits are written by software. They select the Port A I/O pin used for the ei1 external interrupt according to the table below. External Interrupt I/O pin selection
ei11 0 0 1 1 ei10 0 1 0 1 I/O Pin No interrupt* PA 4 P A5 PA 6
Port A I/O pin used for the ei0 external interrupt according to the table below. External Interrupt I/O pin selection
ei01 0 0 1 1 ei00 0 1 0 1 I/O Pin No Interrupt* PA1 PA2 PA3
* Reset State Bits 1:0 = Reserved.
* Reset State Bit 1:0 = ei0[1:0] ei0 pin selection These bits are written by software. They select the
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9 POWER SAVING MODES
9.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, five main power saving modes are implemented in the ST7 (see Figure 21): Slow Wait (and Slow-Wait) Active Halt Auto Wake up From Halt (AWUFH) Halt After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (fOSC2). From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 21. Power Saving Mode Transitions
High RUN SLOW WAIT SLOW W A IT ACTIV E HALT AUTO WAKE UP FROM HALT HALT Low POW E R C O N SUMP TION
SMS
9.2 SLOW MODE This mode has two targets: To reduce power consumption by decreasing the internal clock in the device, To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by the SMS bit in the MCCSR register which enables or disables Slow mode. In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked at thislower frequency. Note: SLOW-WAIT mode is activated when entering WAIT mode while the device is already in SLOW mode. Figure 22. SLOW Mode Clock Transition
fOSC/32 fCPU fOSC
fOSC
NORMAL RUN MODE REQUEST
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POWER SAVING MODES (Cont'd) 9.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 23. Figure 23. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS CP U I BI T ON ON OFF 0
WFI I N S T R U C T I O N
N RE SET N INTERRUP T Y OSCILLATOR PERIPHERALS CP U I BI T ON OFF ON 0 Y
256 OR 4096 CPU CLOCK CYCLE DELAY
OSCILLATOR PERIPHERALS CP U I BI T
ON ON ON X 1)
FETC H RES ET VEC TOR OR SERVICE INTERRUPT
Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 9.4 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when ACTIVE-HALT is disabled (see section 9.5 on page 42 for more details) and when the AWUEN bit in the AWUCSR register is cleared. The MCU can exit HALT mode on reception of either a specific interrupt (see Table 6, "Interrupt Mapping," on page 36) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 25). When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see section 15.1 on page 161 for more details). Figure 24. HALT Timing Overview
RUN HA LT 256 or 4096 CPU CYCLE DELAY RESET OR INTER RUPT FE TCH VECTOR RUN
Figure 25. HALT Mode Flow-chart
H A L T INSTR UCTIO N (Active Halt disabled) (AW UCSR.AWUE N=0) ENABLE W D GH A L T 1 ) 1 W ATCHDO G RE SET OSCILLATOR OFF PERIPHERALS 2) OFF CP U OFF I BI T 0 0 W ATCHDOG DISABLE
N RE SET N Y INTERRUPT 3) Y OSCILLATOR PERIPHERALS CP U I BI T ON OFF ON X 4)
256 OR 4096 CPU CLOCK C YCL E DE LAY OSCILLATOR PERIPHERALS CP U I BI T ON ON ON X 4)
FETC H RES ET VEC TOR OR SERVICE INTERRUPT
HA LT IN STRUCTION [Active Halt disabled]
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 6, "Interrupt Mapping," on page 36 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 9.4.0.1 Halt Mode Recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode. When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" or "floating interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in program memory with the value 0x8E. As the HALT instruction clears the interrupt mask in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 9.5 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock (RTC) available. It is entered by executing the `HALT' instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the LTCSR/ATCSR register status as shown in the following table:.
ATCS R LTCSR1 A T CSR ATCSR OVFIE1 TB1IE bit CK1 bit CK0 bit bit 0 0 1 x x 0 x 1 x x x 0 0 x x 1 Meaning ACTIVE -HALT mode disabled ACTIVE -HALT mode enabled
The MCU can exit ACTIVE-HALT mode on reception of a specific interrupt (see Table 6, "Interrupt Mapping," on page 36) or a RESET. When exiting ACTIVE-HALT mode by means of a RESET, a 256 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by fetching the reset vector which woke it up (see Figure 27). When exiting ACTIVE-HALT mode by means of an interrupt, the CPU immediately resumes operation by servicing the interrupt vector which woke it up (see Figure 27). When entering ACTIVE-HALT mode, the I bit in the CC register is cleared to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately (see Note 3). In ACTIVE-HALT mode, only the main oscillator and the selected timer counter (LT/AT) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). Note: As soon as ACTIVE-HALT is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.
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POWER SAVING MODES (Cont'd) Figure 26. ACTIVE-HALT Timing Overview
RUN ACTIVE 256 OR 4096 CPU CYCLE DELAY 1)
9.6 AUTO WAKE UP FROM HALT MODE Auto Wake Up From Halt (AWUFH) mode is similar to Halt mode with the additional of an internal RC oscillator for wake-up. Compared to ACTIVEHALT mode, AWUFH has lower power consumption (the main clock is not kept running), but there is no accurate realtime clock available. It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set. Figure 28. AWUFH Mode Block Diagram
HALT
RUN
HA LT IN STRUCTION [Active Halt Enabled]
RESET OR INTER RUPT
FE TCH VECTOR
Figure 27. ACTIVE-HALT Mode Flow-chart
H A L T INSTR UCTIO N (Active Halt enabled) (AW UCSR.AWUE N=0) OSCILLATOR ON PERIPHERALS 2) OFF CP U OFF I BI T 0
AWUCK Opt bit
AWU RC Oscillator 32-KHz Oscillator f AWU_RC
1 0
N RE SET N INTERR UPT Y Y
3)
to Auto-Reload Timer Input Capture
OSCILLATOR ON PERIPHERALS 2) OFF CP U ON I BI T X 4) 256 OR 4096 CPU CLO CK C YCLE DE LAY OSCILLATOR PERIPHERALS CP U I BI T ON ON ON X 4)
/64 divider
AWU F H prescaler/1 .. 255
AWUFH interrupt (ei0 source)
FETC H R ES ET VEC TOR O R SE RVICE I NTERRUPT
Notes: 1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET. 2. Peripherals clocked with an external clock source can still be active. 3. Only the RTC1 interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode. Refer to Table 6, "Interrupt Mapping," on page 36 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
As soon as HALT mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the AWUPR register. The output of this prescaler provides the delay time. When the delay has elapsed the AWUF flag is set by hardware and an interrupt wakes-up the MCU from Halt mode. At the same time the main oscillator is immediately turned on and a 256 cycle delay is used to stabilize it. After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU flag and its associated interrupt are cleared by software reading the AWUCSR register. To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency fAWU_RC and then calculating the right prescaler value. Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run mode. This connects fAWU_RC to the input capture of the 12-bit Auto-Relad timer, allowing the fAWU_RC to be measured using the main oscillator clock as a reference timebase.
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POWER SAVING MODES (Cont'd) Similarities with Halt mode The following AWUFH mode behaviour is the same as normal Halt mode: The MCU can exit AWUFH mode by means of any interrupt with exit from Halt capability or a reset (see Section 9.4 HALT MODE). When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In AWUFH mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator). The compatibility of Watchdog operation with AWUFH mode is configured by the WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET.
Figure 29. AWUF Halt Timing Diagram tAWU RUN MODE
f CPU fAWU_RC
HALT MODE
256 OR 4096 tCPU
RUN MODE
Clear by software
AWUFH interrupt
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POWER SAVING MODES (Cont'd) Figure 30. AWUFH Mode Flow-chart
HA LT INSTRUCTION (Active-Halt disabled) (AWUCSR.AWUEN=1) ENABLE W D GH A L T 1 ) 1 W ATCHDO G RE SET AWU RC OSC ON MAIN OSC OFF PERIPHERALS 2) OFF CP U OFF I[1:0] BITS 10 0 W ATCHDOG DISABLE
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 6, "Interrupt Mapping," on page 36 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
N RE SET N Y INTERRUPT 3) Y AWU RC OSC OFF MAIN OSC ON PERIPHERA LS OFF CP U ON I[1:0] BITS XX 4) 256 CPU C LOCK C YCL E DE LAY AWU RC OSC OFF MAIN OSC ON PERIPHERA LS O N CP U ON I[1:0] BITS XX 4) FETC H R ES ET VEC TOR O R SE RVICE I NTERRUPT
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POWER SAVING MODES (Cont'd) 9.6.0.1 Register Description AWUFH CONTROL/STATUS REGISTER (AWU CSR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 A WU F A WU M A WU E N
AWUFH PRESCALER REGISTER (AWUPR) Read / Write Reset Value: 1111 1111 (FFh)
7 0
A W U A W U A W U A W U A W U A WU A WU A W U P R7 P R6 P R5 PR4 PR3 PR2 PR1 PR0
Bits 7:3 = Reserved. Bit 1= AWUF Auto Wake Up Flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value. 0: No AWU interrupt occurred 1: AWU interrupt occurred Bit 2= AWUM Auto Wake Up Measurement This bit enables the AWU RC oscillator and connects its output to the input capture of the 12-bit auto-reload timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compensate this dispersion by providing the right value in the AWUPR register. 0: Measurement disabled 1: Measurement enabled Bit 0 = AWUEN Auto Wake Up From Halt Enabled This bit enables the Auto Wake Up From Halt feature: once HALT mode is entered, the AWUFH wakes up the microcontroller after a time delay dependent on the AWU prescaler value. It is set and cleared by software. 0: AWUFH (Auto Wake Up From Halt) mode disabled 1: AWUFH (Auto Wake Up From Halt) mode enabled Table 8. AWU Register Map and Reset Values
Address (Hex.) 0049h 004Ah Register Label 7 6 5
Bits 7:0= AWUPR[7:0] Auto Wake Up Prescaler These 8 bits define the AWUPR Dividing factor (as explained below
AWUPR[7:0] 00h 01h ... FEh FFh Dividing factor Forbidden 1 ... 254 255
In AWU mode, the period that the MCU stays in Halt Mode (tAWU in Figure 29 on page 44) is defined by
t
AWU
1 = 64 × A W U P R × ------------------------- + t RCSTRT f AWURC
This prescaler register can be programmed to modify the time that the MCU stays in Halt mode before waking up automatically. Note: If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately after a HALT instruction, or the AWUPR remains unchanged.
4
3
2
1
0
A WU P R A W U P R 7 A W U P R 6 A W U P R 5 A W U P R 4 A W U P R 3 A WU P R 2 A W U P R 1 A W U P R 0 Reset Value 1 1 1 1 1 1 1 1 A WU C S R 0 0 0 0 0 A WU F A WU M A WU E N Reset Value
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10 I/O PORTS
10.1 INTRODUCTION The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include external interrupt, alternate signal input/output for onchip peripherals or analog input. 10.2 FUNCTIONAL DESCRIPTION A Data Register (DR) and a Data Direction Register (DDR) are always associated with each port. The Option Register (OR), which allows input/output options, may or may not be implemented. The following description takes into account the OR register. Refer to the Port Configuration table for device specific information. An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit x corresponding to pin x of the port. Figure 31 shows the generic I/O block diagram. 10.2.1 Input Modes Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital value from that I/O pin. If an OR bit is available, different input modes can be configured by software: floating or pull-up. Refer to I/O Port Implementation section for configuration. Notes: 1. Writing to the DR modifies the latch value but does not change the state of the input pin. 2. Do not use read/modify/write instructions (BSET/BRES) to modify the DR register. External Interrupt Function Depending on the device, setting the ORx bit while in input mode can configure an I/O as an input with interrupt. In this configuration, a signal edge or level input on the I/O generates an interrupt request via the corresponding interrupt vector (eix). Falling or rising edge sensitivity is programmed independently for each interrupt vector. The External Interrupt Control Register (EICR) or the Miscellaneous Register controls this sensitivity, depending on the device. A device may have up to 7 external interrupts. Several pins may be tied to one external interrupt vector. Refer to Pin Description to see which ports have external interrupts. If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. For this reason if one of the interrupt pins is tied low, it may mask the others. External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Modifying the sensitivity bits will clear any pending interrupts. 10.2.2 Output Modes Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the I/O through the latch. Reading the DR bits returns the previously stored value. If an OR bit is available, different output modes can be selected by software: push-pull or opendrain. Refer to I/O Port Implementation section for configuration. DR Value and Output Pin Status
DR 0 1 Push-Pull VOL V OH Op e n - D r a i n VOL Floating
10.2.3 Alternate Functions Many ST7s I/Os have one or more alternate functions. These may include output signals from, or input signals to, on-chip peripherals. The Device Pin Description table describes which peripheral signals can be input/output to which ports. A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripheral's control register). The peripheral configures the I/O as an output and takes priority over standard I/ O programming. The I/O's state is readable by addressing the corresponding I/O data register. Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this will increase current consumption. Before using an I/O as an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur. Configure an I/O as input floating for an on-chip peripheral signal which can be input and output. Caution: I/Os which can be configured as both an analog and digital alternate function need special attention. The user must control the peripherals so that the signals do not arrive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function.
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I/O PORTS (Cont'd) Figure 31. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE O UT PUT
From on-chip peripheral
1 0
VDD
P-BUFFER (see table below) PULL-UP (see table below) VDD
ALTERNATE EN ABLE BIT DR
DDR
PULL-UP CON DITION
DATA BUS
PA D
OR OR SEL
If implemented
N-BUFFER DDR SEL CMOS SCHMITT TRIG GER
DIO D ES (see table below) ANALO G INPUT
DR SEL
1 0
ALTERNATE INPUT
Combinational Logic To on-chip peripheral
EXTERNAL INTERR UPT REQUEST (eix)
SENSITIVITY SELECTION
FRO M O T HER BITS Note: Refer to the Port Configuration
table for device specific information.
Table 9. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD t o VS S
O u tput
NI (see note 1)
Legend: NI - not implemented Off - implemented not activated On - implemented and activated Note 1: The diode to VDD is not implemented in the true open drain pads. A local protection between
the pad and VOL is implemented to protect the device against positive stress. Note 2: For further details on port configuration, please refer to Table 11 and Table 12 on page 51.
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I/O PORTS (Cont'd) Table 10. I/O Configurations
Hardware Configuration
VDD RPU PAD NOTE 3 PULL-UP CONDITION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
INPUT 1)
FROM OTHER PINS INTERRUPT COMBINATIONAL POLARITY LOGIC SELECTION CONDITION
ALTERNATE INPUT To on-chip peripheral EXTERNAL INTERRUPT SOURCE (eix)
ANALOG INPUT
OPEN-DRAIN O UTPUT 2 )
VDD RPU PAD
NOTE 3 DR REGISTER ACCESS
DR REGISTER
R/W
DATA BUS
P U S H - P U L L OU T P U T 2 )
VDD RPU PAD
NOTE 3
DR REGISTER ACCESS
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE BIT
ALTERNATE OUTPUT From on-chip peripheral
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content. 3. For true open drain, these elements are not implemented.
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I/O PORTS (Cont'd) Analog alternate function Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the ADC input. Analog Recommendations Do not change the voltage level or loading on any I/O while conversion is in progress. Do not have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 10.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific I/O port features such as ADC input or open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 32. Other transitions are potentially risky and should be avoided, since they may present unwanted side-effects such as spurious interrupt generation. Figure 32. Interrupt I/O Port State Transitions 01 00 10 11
10.4 UNUSED I/O PINS Unused I/O pins must be connected to fixed voltage levels. Refer to Section 13.8. 10.5 LOW POWER MODES
Mode WAIT H AL T Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode.
10.6 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction).
Interrupt Event External interrupt on selected external event Enable Event Control Flag Bit DDRx OR x Exit from Wait Yes Exit from Halt Yes
Related Documentation AN 970: SPI Communication between ST7 and E EPROM AN1045: S/W implementation of I2C bus master AN1048: Software LCD driver
OUTPUT OUTPUT INPU T INPUT floating/pull-up floating open-drain push-pull interrupt (reset state)
XX
= DDR, OR
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I/O PORTS (Cont'd) The I/O port register configurations are summarised as follows. Standard Ports PA7:0, PB6:0
MODE floating input pull-up input open drain output push-pull output D DR 0 0 1 1 OR 0 1 0 1
Interrupt Ports Ports where the external interrupt capability is selected using the EISR register
MODE floating input pull-up interrupt input D DR 0 0 OR 0 1
Table 11. Port Configuration (Standard ports)
Port
Port A Port B
Pin name
PA7:0 PB6:0
Input (DDR=0) OR = 0 OR = 1
floating floating pull-up pull-up
Output (DDR=1) OR = 0 OR = 1
open drain open drain push-pull push-pull
Note: On ports where the external interrupt capability is selected using the EISR register, the configuration will be as follows: Table 12. Port Configuration (external interrupts)
Port
Port A Port B
Pin name
PA6:1 PB5:0
Input with interrupt (DDR=0 ; EISR00) OR = 0 OR = 1
floating floating p u l l -u p p u l l -u p
Table 13. I/O Port Register Map and Reset Values
Address (Hex.) 0000h 0001h 0002h 0003h 0004h 0005h Register Label P ADR Reset Value P ADDR Reset Value P A OR Reset Value P BDR Reset Value P BDDR Reset Value P B OR Reset Value 7 MSB 1 MSB 0 MSB 0 MSB 1 MSB 0 MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 6 5 4 3 2 1 0 LSB 1 LSB 0 LSB 0 LSB 1 LSB 0 LSB 0
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11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 11.1.2 Main Features Programmable free-running downcounter (64 increments of 16000 CPU cycles) Programmable reset Reset (if watchdog activated) when the T6 bit reaches zero Figure 33. Watchdog Block Diagram
RESET
Optional reset on HALT instruction (configurable by option byte) Hardware Watchdog selectable by option byte
11.1.3 Functional Description The counter value stored in the CR register (bits T[6:0]), is decremented every 16000 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 30s.
WATCHDOG CONTROL REGISTER (CR) WDG A T6 T5 T4 T3 T2 T1 T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER ÷16000
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WATCHDOG TIMER (Cont'd) The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is freerunning: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 14 .Watchdog Timing): The WDGA bit is set (watchdog enabled) The T6 bit is set to prevent generating an immediate reset The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset.
Table 14.Watchdog Timing
fCPU = 8MHz WDG Counter C ode C0h FFh min [ms] 1 127 max [ms] 2 128
Notes: The timing variation shown in Table 14 is due to the unknown status of the prescaler when writing to the CR register. 11.1.4 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the Option Byte description in section 15.1 on page 161. 11.1.4.1 Using Halt Mode with the WDG (WDGHALT option) If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
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WATCHDOG TIMER (Cont'd) 11.1.5 Interrupts None. 11.1.6 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0111 1111 (7Fh)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte.
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WATCHDOG TIMER (Cont'd) Table 15. Watchdog Timer Register Map and Reset Values
Address (Hex.) 002Eh Register Label W D GC R Reset Value 7 W D GA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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11.2 DUAL 12-BIT AUTORELOAD TIMER 3 (AT3) 11.2.1 Introduction The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based on one or two free-running 12-bit upcounters with an input capture register and four PWM output channels. There are 6 external pins: Four PWM outputs ATIC/LTIC pin for the Input Capture function BREAK pin for forcing a break condition on the PWM outputs 11.2.2 Main Features Single Timer or Dual Timer mode with two 12-bit upcounters (CNTR1/CNTR2) and two 12-bit autoreload registers (ATR1/ATR2) Maskable overflow interrupts Figure 34. Single Timer Mode (ENCNTR2=0)
PWM mode Generation of four independent PWMx signals Dead time generation for Half bridge driving mode with programmable dead time Frequency 2KHz-4MHz (@ 8 MHz fCPU) Programmable duty-cycles Polarity control Programmable output modes Output Compare Mode Input Capture Mode 12-bit input capture register (ATICR) Triggered by rising and falling edges Maskable IC interrupt Long range input capture Break control Flexible Clock control
ATIC
Edge Detection Circuit
12-bit Input Capture Output Compare CMP Interrupt OE0 Dead Time Generator DTE bit PWM2 Duty Cycle Generator OE2 OE3 PWM3 BPEN bit OVF1 Interrupt Break Function OE1 PWM0 PWM1
PWM0 Duty Cycle Generator 12-Bit Autoreload Register 1 PWM1 Duty Cycle Generator Clock Control 12-Bit Upcounter 1
PWM2
1ms from Lite Timer
PWM3 Duty Cycle Generator fCPU
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont'd) Figure 35. Dual Timer Mode (ENCNTR2=1)
ATIC 12-bit Input Capture Output Compare CMP Interrupt OE0 Dead Time Generator OE1 Break Function
Edge Detection Circuit
12-Bit Autoreload Register 1
PWM0 Duty Cycle Generator PWM1 Duty Cycle Generator OVF1 interrupt OVF2 interrupt
PWM0 PWM1
12-Bit Upcounter 1 Clock Control 12-Bit Upcounter 2 fCPU 1ms
DTE bit OE2 OE3
PWM2 Duty Cycle Generator PWM3 Duty Cycle Generator
PWM2 PWM3
12-Bit Autoreload Register 2 BPEN bit
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont'd) 11.2.3 Functional Description 11.2.3.1 PWM Mode This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins. PWM Frequency The four PWM signals can have the same frequency (fPWM) or can have two different frequencies. This is selected by the ENCNTR2 bit which enables single timer or dual timer mode (see Figure 34 and Figure 35). The frequency is controlled by the counter period and the ATR register value. In dual timer mode, PWM2 and PWM3 can be generated with a different frequency controlled by CNTR2 and ATR2. fPWM = fCOUNTER / (4096 - ATR) Following the above formula, If fCOUNTER is 4 Mhz, the maximum value of fPWM is 2 MHz (ATR register value = 4094),the minimum value is 1 KHz (ATR register value = 0). Duty Cycle The duty cycle is selected by programming the DCRx registers. These are preload registers. The DCRx values are transferred in Active duty cycle registers after an overflow event if the corresponding transfer bit (TRANx bit) is set. The TRAN1 bit controls the PWMx outputs driven by counter 1 and the TRAN2 bit controls the PWMx outputs driven by counter 2. PWM generation and output compare are done by comparing these active DCRx values with the counter. The maximum available resolution for the PWMx duty cycle is: Resolution = 1 / (4096 - ATR) where ATR is equal to 0. With this maximum resolution, 0% and 100% duty cycle can be obtained by changing the polarity. At reset, the counter starts counting from 0. When a upcounter overflow occurs (OVF event), the preloaded Duty cycle values are transferred to
the active Duty Cycle registers and the PWMx signals are set to a high level. When the upcounter matches the active DCRx value the PWMx signals are set to a low level. To obtain a signal on a PWMx pin, the contents of the corresponding active DCRx register must be greater than the contents of the ATR register. The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case. Polarity Inversion The polarity bits can be used to invert any of the four output signals. The inversion is synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2 register is set (reset value). See Figure 36. Figure 36. PWM Polarity Inversion
inverter PWMx PW Mx PIN
PWMxCSR Register OPx
TRANx ATCSR2 Register counter overflow
DFF
The Data Flip Flop (DFF) applies the polarity inversion when triggered by the counter overflow input. Output Control The PWMx output signals can be enabled or disabled using the OEx bits in the PWMCR register.
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont'd) Figure 37. PWM Function
4095 DUTY CYCLE R EGIST ER (DCRx)
COUNTER
AUT O-RELO A D RE GISTER (ATR) 000
t
PWMx OUTPUT
WITH OE=1 AND OPx=0 WITH OE=1 AND OPx=1
Figure 38. PWM Signal from 0% to 100% Duty Cycle
fCOUNTER ATR= FFDh COUNTER PWMx OUTPUT WITH MOD00=1 AND OPx=0 FFDh FFEh FFFh FFDh FFEh FFFh FFDh FF Eh
DCRx=000h DCRx=FFDh DCRx=FFEh
PWMx OUTPUT WITH MOD00=1 AND OPx=1
DCRx=000h
t
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont'd) Dead Time Generation A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is required for half-bridge driving where PWM signals must not be overlapped. The non-overlapping PWM0/ PWM1 signals are generated through a programmable dead time by setting the DTE bit. Dead time value = DT[6:0] x Tcounter1 DTGR[7:0] is buffered inside so as to avoid deforming the current PWM cycle. The DTGR effect will take place only after an overflow. Figure 39. Dead Time Generation T counter1
Notes: 1. Dead time is generated only when DTE=1 and DT[6:0] 0. If DTE is set and DT[6:0]=0, PWM output signals will be at their reset state. 2. Half Bridge driving is possible only if polarities of PWM0 and PWM1 are not inverted, i.e. if OP0 and OP1 are not set. If polarity is inverted, overlapping PWM0/PWM1 signals will be generated.
CK_CNTR1
CNTR1
DCR0
D CR0+1
OVF
ATR1
counter = DCR0
if DTE = 0 PWM 0
counter = DCR1
PWM 1
T dt
if DTE = 1 PWM 0
T dt
PWM 1
Tdt = DT[6:0] x Tcounter1 In the above example, when the DTE bit is set: PWM goes low at DCR0 match and goes high at ATR1+Tdt PWM1 goes high at DCR0+Tdt and goes low at ATR match. With this programmable delay (Tdt), the PWM0 and PWM1 signals which are generated are not overlapped.
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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont'd) Break Function The break function can be used to perform an emergency shutdown of the application being driven by the PWM signals. The break function is activated by the external BREAK pin (active low). In order to use the BREAK pin it must be previously enable |
