ESDALC6V1M6, ESDALC6V1-5M6
4- and 5-line low capacitance TransilTM arrays for ESD protection
Features
High ESD protection level High integration Suitable for high density boards 4 unidirectional Transil diodes (ESDALC6V1M6) 5 unidirectional Transil diodes (ESDALC6V1-5M6) Breakdown Voltage VBR = 6.1 V min Low diode capacitance (12 pF typ at 0 V) Low leakage current < 70 nA Very small PCB area: 1.45 500 microns pitch Lead-free package
I/O2 3 4 I/O3 I/O1 1 GND 2 6 I/O5 5 GND
Micro QFN package
Figure 1. Functional diagram
ESDALC6V1M6
mm²
Complies with the following standards
ESDALC6V1-5M6
I/O1 1 GND 2 I/O2 3 6 I/O5 5 I/O4 4 I/O3
IEC 61000-4-2 15 kV (air discharge) 8 kV (contact discharge) MIL STD 883G- Method 3015-7: class3B >8 kV (human body model)
Appl ication s
Where transient overvoltage protection in ESD sensitive equipment is required, such as:
Description
The ESDALC6V1xxM6 are monolithic arrays designed to protect up to 4 or 5 lines against ESD transients. The device is ideal for applications where both reduced print circuit board space and power absorption capability are required.
Computers Printers Communication systems Cellular phone handsets and accessories Video equipment
TM: Transil is a trademark of STMicroelectronics
February 2008
Rev 5
1/11
www.st.com 11
Characteristics
ESDALC6V1M6, ESDALC6V1-5M6
1
Characteristics
Table 1.
Symbol
Absolute maximum ratings (Tamb = 25 C)
Parameter ESD IEC 61000-4-2, air discharge ESD IEC 61000-4-2, contact discharge MIL STD 883G- Method 3015-7: class3B, (human body model) Peak pulse power dissipation (8/20 s)(1) Tj initial = Tamb Value 15 8 25 30 3 125 -55 + 150 260 -40 + 125 Unit
VPP PPP Ip p Tj Tstg TL TOP
kV
W A C C C C
Repetitive peak pulse current typical value (8/20 s) Junction temperature Storage temperature range Maximum lead temperature for soldering during 10 s Operating temperature range
1. For a surge greater than the maximum values, the diode will fail in short-circuit.
Table 2.
Symbol VRM VBR VCL IRM IPP T VF Symbol VBR IRM VF Rd T(1) C
Electrical characteristics (Tamb = 25 C)
Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current @ VRM Peak pulse current Voltage temperature coefficient Forward voltage drop Test Condition IR = 1 mA VRM = 3 V IF = 10 mA 2 IR = 1 mA, VR =0 V DC, F = 1 MHz, Vosc = 30 mVRMS 12 Min 6.1 Typ Max 7.2 70 1 3 5 15 Unit V nA V 10-4/ C pF
Slope= 1/ Rd I PP VCL VBR VRM I RM IR VF V I
IF
1. VBR = T * (Tamb - 25 C) * VBR (25 C)
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ESDALC6V1M6, ESDALC6V1-5M6
Characteristics
Figure 2.
Relative variation of peak pulse power versus initial junction temperature
Figure 3.
Peak pulse power versus exponential pulse duration
PPP(W)
PP P [ Tj i n i t i a l ] /P P [ Tj i n i t i a l = 2 5 C] P
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150 T j (C)
1000
Tj initial = 25C
100
t P (s) 10 1 10 100
Figure 4.
Clamping voltage versus peak pulse current (typical values, 8/20 s waveform)
Figure 5.
Forward voltage drop versus peak forward current (typical values)
IPP(A)
100.0
8/20 s Tj initial =25C
1.E+00
IF M( A )
10.0
1.E-01
Tj =125C Tj =25C
1.E-02
1.0
V FM (V)
VCL(V) 0.1 0 10 20 30 40 50 60 70
1.E-03 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Figure 6.
Junction capacitance versus reverse voltage applied (typical values)
Figure 7.
Relative variation of leakage current versus junction temperature (typical values)
C(pF)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0.0 0.5 1.0 1.5 2.0
VR(V)
F=1MHz VOSC=30mVRMS Tj=25C
IR [ Tj] / IR [ Tj= 2 5 C ]
100
VR =3V
10
T j (C) 1 25 50 75 100 125
2.5
3.0
3.5
4.0
4.5
5.0
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Ordering information scheme
ESDALC6V1M6, ESDALC6V1-5M6
Figure 8.
S21 attenuation measurement results of each channel
dB
Figure 9.
Analog crosstalk measurements between channels
dB
0.00
0.00
-10.00
-30.00
-20.00
-60.00
-30.00
-90.00
f/Hz
-40.00 100.0k
-120.00
f/Hz
1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
1.0M
10.0M
100.0M
Figure 10. ESD response to IEC 6100-4-2 (+15 kV air discharge) on each channel
Figure 11. ESD response to IEC 6100-4-2 (-15 kV air discharge) on each channel
2
Ordering information scheme
Figure 12. Ordering information scheme
ESDA LC
ESD array Low capacitance Breakdown voltage 6V1 = 6.1 Volts min Number of lines blank = 4 line -5 = 5 line protection Package M6 = Micro QFN 6 leads
6V1
xx
M6
4/11
ESDALC6V1M6, ESDALC6V1-5M6
Package information
3
Package information
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Table 3. Package dimensions
Dimensions
D
N
Ref
E
Millimeters M in Typ Max 0.60 0.05 0.30 Min 0.020 0.000 0.007
Inches Typ 0.022 0.001 0.010 0.057 0.039 0.020 0.008 Max 0.024 0.002 0.012
1
2
A A1
0.50 0.55 0.00 0.02 0.18 0.25 1.45 1.00 0.50 0.20 0.30 0.35
A A1
b D(1)
1 2
L k b e
E(1) e(2) k L
0.40
0.012
0.014
0.016
1. 0.1 mm 2. 0.05 mm
Figure 13. Footprint dimensions in mm [inches]
0.50 [0.020] 0.25 [0.010]
0.65 [0.026] 0.30 1.60 [0.012] [0.063]
5/11
Package information Figure 14. Tape and reel specification
ESDALC6V1M6, ESDALC6V1-5M6
Dot identifying Pin A1 location 2.0+/-0.05 4.00+/-0.1 1.5 +/- 0.1 1.75 +/- 0.1 3.5 +/- 0.03
0.75
8.0 +/- 0.3
X: Marking
1.65
X
X
X
1.20 User direction of unreeling
4.00
Note:
Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
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ESDALC6V1M6, ESDALC6V1-5M6
Recommendation on PCB assembly
4
4.1
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 15. Stencil opening dimensions
L
T
W
b)
General design rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ---- 1.5 T L× W Aspect Area = --------------------------- 0.66 2T(L + W)
2.
Reference design a) b) Stencil opening thickness: 100 m Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 16. Recommended stencil window position
7 m
7 m 15 m
650 m
620 m 236 m 15 m 250 m
Footprint
Stencil window Footprint
7/11
Recommendation on PCB assembly
ESDALC6V1M6, ESDALC6V1-5M6
4.2
Solder paste
1. 2. 3. 4. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. "No clean" solder paste is recommended. Offers a high tack force to resist component movement during high speed. Solder paste with fine particles: powder particle size is 20-45 m.
4.3
Placement
1. 2. 3. 4. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. Standard tolerance of 0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5. 6.
4.4
PCB design preference
1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
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ESDALC6V1M6, ESDALC6V1-5M6
Recommendation on PCB assembly
4.5
Reflow profile
Figure 17. ST ECOPACK recommended soldering reflow profile for PCB mounting
Temperature (C)
260C max 255C 220C 180C 125 C
2C/s recommended 2C/s recommended 6C/s max 6C/s max
3C/s max 3C/s max
0 0 1 2 3 4 5
10-30 sec 90 to 150 sec 90 sec max
6
7
Time (min)
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
9/11
Ordering information
ESDALC6V1M6, ESDALC6V1-5M6
5
Ordering information
Table 4. Ordering information
Marking G(1) H(1) Package Micro QFN Micro QFN Weight 2.2 mg 2.2 mg Base qty 3000 3000 Delivery mode Tape and reel Tape and reel
Order code ESDALC6V1M6 ESDALC6V1-5M6
1. The marking can be rotated by 90 to differentiate assembly location
6
Revision history
Table 5.
Date 19-Sep-2005 10-Oct-2005 21-Dec-2005 01-Feb-2007
Document revision history
Revision 1 2 3 4 Initial release. Package title changed from DFN to QFN. No technical changes. Updated package dimensions in Table 1. Reformatted to current standard. Added note on marking rotation in section 3. Package information. Reformatted to current standards. Corrected inch measurements in Table 3 on page 5. Added Section 4: Recommendation on PCB assembly Changes
14-Feb-2008
5
10/11
ESDALC6V1M6, ESDALC6V1-5M6
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