ST7LITEUSx
8-bit MCU with single voltage Flash memory, ADC, timers
Features
Memories 1K bytes single voltage Flash Program memory with read-out protection, In-Circuit and InApplication Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55C. 128 bytes RAM. Clock, Reset and Supply Management 3-level low voltage supervisor (LVD) and auxiliary voltage detector (AVD) for safe poweron/off procedures Clock sources: internal trimmable 8MHz RC oscillator, internal low power, low frequency RC oscillator or external clock Five Power Saving Modes: Halt, Auto Wake Up from Halt, Active-Halt, Wait and Slow Interrupt Management 11 interrupt vectors plus TRAP and RESET 5 external interrupt lines (on 5 vectors) I/O Ports 5 multifunctional bidirectional I/O lines 1 additional Output line 6 alternate function lines 5 high sink outputs 2 Timers One 8-bit Lite Timer (LT) with prescaler including: watchdog, one realtime base and one 8-bit input capture. One 12-bit Auto-reload Timer (AT) with output compare function and PWM
DIP8
SO8 150"
DFN8
A/D Converter 10-bit resolution for 0 to VDD 5 input channels Instruction Set 8-bit data manipulation 63 basic instructions with illegal opcode detection 17 main addressing modes 8 x 8 unsigned multiply instruction Development Tools Full hardware/software development package Debug Module
Table 1. Device summary
Features Program memory - bytes RAM (stack) - bytes Peripherals A DC Operating Supply CPU Frequency Operating Temperature Packages ST7ULTRALITE ST7LITEUS2 ST7LITEUS5 1K 128 (64) LT Timer w/ Wdg, AT Timer w/ 1 PWM 10-bit 2.4V to 3.3V @fCPU=4MHz, 3.3V to 5.5V @fCPU=8MHz up to 8MHz RC -40C to +85C / -40C to 125C SO8 150", DIP8, DFN8, DIP161)
Note 1: For development or tool prototyping purposes only. Not orderable in production quantities.
Rev. 4
January 2007 1/108
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ST7LITEUSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SINTRODUCTION . . .. ... .. ... .. ... .. ... .. ... .. ... . ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... .. ... 1 1 T7LITEUSx . 4
2 PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 1 INTRODUCTION . 3 REGISTER & MEMORY . . . 8 2 PIN DESCRIPTION . . . .MAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3 REGISTER & MEMORY MAP 8 4.1 INTRODUCTI MEMORY 4 FLASH PROGRAM ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 M T N FEATURES 4.1 INAIRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 P AIN RAMMING . . . . . 4.2 MROGFEATURESMODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 ICC GRAMMING . . . . . . 12 4.3 PROINTERFACE MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 M C INTERFACE . . . . . . 4.4 ICEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 12 6 R EMO ED DOCUMENTATION 4.5 MELATRY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 LATED DOCUMENTATION 5 CENTRAL IPROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 REG STER DESCRIPTION 13 5.1 INTRODUCTION . . UNIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 .... 5 CENTRAL PROCESSING 2 M T N FEATURES 5.1 INAIRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 MAIN FEATURES 6 SUPPLY,U REGISTERS . . . . . .MANAGEMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 CP RESET AND CLOCK . . . . . . . . . . . . 14 6.1 INT RESET AND CLOCK MANAGEMENT . . 6 SUPPLY, ERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 19 6.2 REGIRNAL RC OSCILLATOR.ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1 INTE STER DESCRIPTION . . . . . . . . . . . . . 3 S ISTER DESCRIPTION . . . . . . . . 22 6.2 REGET SEQUENCE MANAGER. (RSM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 REGET SEQUENCE MANAGER. (RSM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 S ISTER DESCRIPTION . . . . . . . . 22 7 INTERRUPTS E. . DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 25 6.4 REGIST R . . . . . . . . . . . . 7.1 NON MASKABLE . . . . . . . . . . . . . . . . . . . . 7 INTERRUPTS . . . . . . . SOFTWARE.INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2 E ON RNAL INTERRUPTS . . . . . . . . . . . . 7.1 NXTEMASKABLE SOFTWARE.INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3 PERIPHER INTERRUPTS . 7.2 EXTERNALAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 SYSTEM INTEGRITY MANAGEMENT.(SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3 PERIPHERAL INTERRUPTS . . . . . . . . . . 25 8 POWER STEM INTEGRITY . . . . . . . . . . . . . .(SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 33 7.4 SYSAVING MODES MANAGEMENT . . . 8.1 IN SAVING MODES 8 POWERTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 34 33 8.2 SLOW DUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1 INTRO MODE . . 3 WAI W MODE 8.2 SLOT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4 ACTIVE-HAL . . . . . . . . . . . . . 8.3 WAIT MODE T .AND. HALT. MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 37 8.5 AUTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4 C O WAKE UP FROM HALT MODE 9 I/O.5 AUTO. WAKE .UP .FROM .HALT .MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 41 8 PORTS . . . . . . . . . . . . . . . . . . . . . 9 PORTS . . U . . . . 41 9 I/O.1 INTROD. .CTI.ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2 FUNCTI UCTION . . . . . . . . . . 9.1 INTRODONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 42 45 9.3 UUNCTID NAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2 F NUSE O I/O PINS . . . . . . . . . 4 L NU POWER MODES 9.3 UOWSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 46 45 9.5 INTERRUPTS MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4 LOW POWER . . . . . . 6 /O PORT IMPLEMENTATION 9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 46 10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 47 9.6 I/O PORT IMPLEMENTATION
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10.1 LITE TIMER (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 12-BIT AUTORELOAD TIMER (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.3 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.1010-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.2 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 95 14.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 15.1 LIMITATIONS IN USER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 15.2 LIMITATIONS IN ICC MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Please pay special attention to the Section "KNOWN LIMITATIONS" on page 104
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1 INTRODUCTION
The ST7ULTRALITE is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7ULTRALITE features FLASH memory with byte-by-byte In-Circuit Programming (ICP) and In-Application Programming (IAP) capability. Under software control, the ST7ULTRALITE device can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to Figure 1. General block diagram
Internal Clock
software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. For easy reference, all parametric data are located in section 12 on page 67. The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.
AWU RC OSC
8-MHz RC OSC
External Clock LVD VDD VSS PA3 / RESET POWER SUPPLY
ADDRESS AND DATA BUS
LITE TIMER with WATCHDOG PORT A 12-BIT AUTORELOAD TIMER
CONTROL 8-BIT CORE ALU 1K Byte FLASH MEMORY
PA5:0 (6 bits)
10-BIT ADC
RAM (128 Bytes)
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2 PIN DESCRIPTION
Figure 2. 8-pin SO and DIP package pinout
VDD PA5 (HS) / AIN4 / CLKIN PA4 (HS) / AIN3 PA3 / RESET
1 2 ei4 3 ei3 4
8 ei0 7 ei1 6 ei2 5
VSS PA0 (HS) / AIN0 / ATPWM / ICCDATA PA1 (HS) / AIN1 / ICCCLK PA2 (HS) / LTIC / AIN2
(HS) : High sink capability eix : associated external interrupt vector
Figure 3. 8-pin DFN package pinout
VDD PA5 (HS) / AIN4 / CLKIN PA4 (HS) / AIN3 PA3 / RESET
1 2 ei4 3 ei3 4
8 ei0 7 ei1 6 ei2 5
VS S PA0 (HS) / AIN0 / ATPWM / ICCDATA PA1 (HS) / AIN1 / ICCCLK PA2 (HS) / LTIC / AIN2
(HS) : High sink capability eix : associated external interrupt vector
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PIN DESCRIPTION (Cont'd) Figure 4. 16-pin package pinout (For development or tool prototyping purposes only. Package not orderable in production quantities.)
Reserved 1) VDD RESET ICCC LK PA5 (HS) / AIN4 / CLKIN PA4 (HS) / AIN3
1 2 3 4 5 ei4 6 ei3
16 15 ei0 14 ei1 13 12 11 e i 2 10 9
NC VSS PA0 (HS) / AIN0 / ATPWM PA1 (HS) / AIN1 NC ICCDA TA PA2 (HS) / LTIC / AIN2 NC
PA3 NC
7 8
Note 1: must be tied to ground
Notes: The differences versus the 8-pin packages are listed below: 1. The ICC signals (ICCCLK and ICCDATA) are mapped on dedicated pins. 2. The RESET signal is mapped on a dedicated pin. It is not multiplexed with PA3.
3. PA3 pin is always configured as output. Any change on multiplexed IO reset control registers (MUXCR1 and MUXCR2) will have no effect on PA3 functionality. Refer to "REGISTER DESCRIPTION" on page 24.
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PIN DESCRIPTION (Cont'd) Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply In/Output level: CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = High sink (on N-buffer only) Port and control configuration: Input:float = floating, wpu = weak pull-up, int = interrupt, ana = analog Output: OD = open drain, PP = push-pull The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 1. Device Pin Description
Level float Pin Name Output Input Pin No. 1 2 3 4 5 Type Port / Control Main Input Output Function (after reset) ana OD PP int Main power supply X X X X ei2 X ei4 ei3 X X X X X X X X X X Port A5 Port A4 Port A3 Port A2 Analog input 4 or External Clock Input Analog input 3 RESET 1) Analog input 2 or Lite Timer Input Capture Analog input 1 or In Circuit Communication Clock Caution: During normal operation this pin must be pulled-up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in pull-up Analog input 0 or Auto-Reload Timer PWM or In Circuit Communication Data
VDD PA5/AIN4/ CLKIN P A4/AI N 3 PA3/RESET 1)
S I/O CT HS I /O C T H S O
PA2/AIN2/LTIC I/O CT HS
6
PA1/AIN1/ ICCCLK
I/O CT HS
X
wpu
Alternate Function
ei1
X
X
X
Port A1
7 8
PA0/AIN0/ATPI/O CT HS W M/ I C C D A T A VSS S
X
ei0
X
X
X
Port A0 Ground
Note: 1. After a reset, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1. For further details, please refer to section 6.4 on page 24.
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3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM and 1 Kbytes of user program memory. The RAM space includes up to 64 bytes for the stack from 00C0h to 00FFh. The highest address bytes contain the user reset and interrupt vectors. Figure 5. Memory Map The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (FE00h-FFFFh). The size of Flash Sector 0 and other device options are configurable by Option byte. IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reseved area can have unpredictable effects on the device.
0000h 007Fh 0080h
HW Registers
0080h
(see Table 2)
00C0h
Short Addressing RAM (zero page) 64-Byte Stack
00FFh
RAM (128 Bytes)
00FFh 0100h
DEE0h DEE1h
RCCRH0 RCCRL0 RCCRH1 RCCRL1
Reserved
DEE2h 1K FLASH PROGRAM MEMORY DEE3h
FBFFh FC00h
see section 6.1 on page 17
FC00h FDFFh FE00h 0.5 Kbytes SECTOR 1 0.5 Kbytes SECTOR 0
Flash Memory (1K)
FFDFh FFE0h
FFFFh
Interrupt & Reset Vectors
(see Table 7)
FFFFh
Note: 1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes containing also the RC calibration values which are read-accessible only in user mode. If all the EEPROM data or Flash space (including the RC calibration values locations) has been erased (after the read-out protection removal), then the RC calibration values can still be obtained through these addresses.
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Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h to 0016h 0017h 0018h 0019h to 002Eh 0002Fh 0030h to 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh to 003Ch 003Dh 003Eh 003Fh 0040h to 0046h ITC AVD Clock controller EICR2 A VDTHCR C KCNTCSR ADC ITC MCC Clock and Reset A DCCSR A DCDRH A DCDRL E ICR1 M CCSR R CCR SICSR FLASH FC SR AU TOR E L OA D TIMER D CR0H D CR0L LITE TIMER LTCSR LTICR A T CSR C NT RH CNTRL ATRH ATRL P WM C R P WM 0 C S R Block Register Label P ADR P ADDR P A OR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Reserved area (8 bytes) Lite Timer Control/Status Register Lite Timer Input Capture Register Timer Control/Status Register Counter Register High Counter Register Low Auto-Reload Register High Auto-Reload Register Low PWM Output Control Register PWM 0 Control/Status Register Reserved area (3 bytes) PWM 0 Duty Cycle Register High PWM 0 Duty Cycle Register Low Reserved area (22 bytes) Flash Control/Status Register Reserved area (4 bytes) A/D Control Status Register A/D Data Register High A/D Data Register Low External Interrupt Control Register 1 Main Clock Control/Status Register RC oscillator Control Register System Integrity Control/Status Register Reserved area (2 bytes) External Interrupt Control Register 2 AVD Threshold Selection Register Clock Controller Control/Status Register Reserved area (7 bytes) 00h 03h 09h R/W R/W R/W 00h xxh 00h 00h 00h FFh 0000 0x00b R/W Read Only R/W R/W R/W R/W R/W 00h R/W 00h 00h R/W R/W 0xh 00h 00h 00h 00h 00h 00h 00h 00h R/W Read Only R/W Read Only Read Only R/W R/W R/W R/W Reset Status 00h 1) 08h 02h 2) Remarks R/W R/W R/W
Port A
AU TOR E L OA D TIMER
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Address 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h to 007Fh
Block MuxIOres e t AW U
Register Label MUXCR0 M UXCR1 A WU P R A WU C S R D MC R D MS R D MB K 1 H D MB K 1 L D MB K 2 H D MB K 2 L
Register Name Mux IO-Reset Control Register 0 Mux IO-Reset Control Register 1 AWU Prescaler Register AWU Control/Status Register DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low Reserved area (47 bytes)
Reset Status 00h 00h FFh 00h 00h 00h 00h 00h 00h 00h
Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DM 3)
Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For a description of the DM registers, see the ST7 ICC Protocol Reference Manual.
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4 FLASH PROGRAM MEMORY
4.1 Introduction The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming. The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features
ICP (In-Circuit Programming) IAP (In-Application Programming) ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Sector 0 size configurable by option byte Read-out and write protection
4.3 PROGRAMMING MODES The ST7 can be programmed in three different ways: Insertion in a programming tool. In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased. In-Circuit Programming. In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board. In-Application Programming. In this mode, sector 1 can be programmed or erased without removing the device from the application board and while the application is running.
4.3.1 In-Circuit Programming (ICP) ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps: Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. Download ICP Driver code in RAM from the ICCDATA pin Execute ICP Driver code in RAM to program the FLASH memory Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In Application Programming (IAP) This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
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FLASH PROGRAM MEMORY (Cont'd) 4.4 ICC interface ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are: RESET: device reset VSS: device power supply ground Figure 6. Typical ICC Interface
PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note 4) APPLICATION BOARD
ICCCLK: ICC output serial clock pin (see note 1) ICCDATA: ICC input serial data pin CLKIN: main clock input for external source VDD: application board power supply (see Note 3)
(See Note 3)
9 10
7 8
5 6
3 4
1 2
APPLICATION RESET SOURCE 3.3k (See Note 5) APPLICATION POWER SUPPLY See Note 2
See Note 1 and Caution See Note 1 CLKIN RESET ICCDATA ICCCLK VDD
APPLICATION I/O
ST7
Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up re-
sistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the CLKIN pin of the ST7 when ICC mode is selected with option bytes disabled (35-pulse ICC entry mode). When option bytes are enabled (38-pulse ICC entry mode), the internal RC clock (internal RC or AWU RC) is forced. If internal RC is selected in the option byte, the internal RC is provided. If AWU RC or external clock is selected, the AWU RC oscillator is provided.
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FLASH PROGRAM MEMORY (Cont'd) 5. A serial resistor must be connected to ICC connector pin 6 in order to prevent contention on PA3/ RESET pin. Contention may occur if a tool forces a state on RESET pin while PA3 pin forces the opposite state in output mode. The resistor value is defined to limit the current below 2mA at 5V. If PA3 is used as output push-pull, then the application must be switched off to allow the tool to take control of the RESET pin (PA3). To allow the programming tool to drive the RESET pin below VIL, special care must also be taken when a pull-up is placed on PA3 for application reasons. Caution: During normal operation, ICCCLK pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up. 4.5 Memory Protection There are two different types of memory protection: read-out protection and Write/Erase Protection which can be applied individually. 4.5.1 Read-out Protection Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Program memory is protected. In flash devices, this protection is removed by reprogramming the option. In this case, program memory is automatically erased, and the device can be reprogrammed. Read-out protection selection depends on the device type: In Flash devices it is enabled and removed through the FMP_R bit in the option byte. In ROM devices it is enabled by mask option specified in the Option List.
4.5.2 Flash Write/Erase Protection Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable. Write/erase protection is enabled through the FMP_W bit in the option byte. 4.6 Related Documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.7 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read / Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh)
7 0 0 0 0 0 OP T L AT 0 PG M
Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing operations. When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.
Table 3. FLASH Register Map and Reset Values
Address (Hex.) 002Fh Register Label FC SR Reset Value 0 0 0 0 0 7 6 5 4 3 2 OP T 0 1 LAT 0 0 PGM 0
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5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES
63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt
5.3 CPU REGISTERS The six CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions. Figure 7. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0
Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value
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CPU REGISTERS (cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
7 1 1 1 H I N Z 0 C
because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test inst ructions. Bit 0 = C Carry/borrow This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible
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CPU REGISTERS (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 00 FFh
15 0 7
1 1 SP5 SP4 SP3 SP2 SP1
8 0 0 0 0 0 0 0 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address. Figure 8. . Stack Manipulation Example
CALL Subroutine @ 00C0h Interrupt event P USH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8. When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
PO P Y
IRET
RET or RSP
SP SP CC A X PC H SP PCH @ 00FFh PCL P CL PCH PCL Y CC A X PCH PCL PCH PC L SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 00FFh Stack Lower Address = 00C0h
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6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. Main features Clock Management 8 MHz internal RC oscillator (enabled by option byte) External Clock Input (enabled by option byte) Reset Sequence Manager (RSM) System Integrity Management (SI) Main supply Low voltage detection (LVD) with reset generation (enabled by option byte) Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply 6.1 INTERNAL RC OSCILLATOR ADJUSTMENT The ST7 contains an internal RC oscillator with a specific accuracy for a given device, temperature and voltage. It can be selected as the start up clock through the CKSEL[1:0] option bits (see section 14.1 on page 95). It must be calibrated to obtain the frequency required in the application. This is done by software writing a 10-bit calibration value in the RCCR (RC Control Register) and in the bits [6:5] in the SICSR (SI Control Status Register). Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in Flash memory for 3.3 and 5V VDD supply voltages at 25C, as shown in the following table.
ST7LITEUS2/ ST7LITEU S5 Address DEE0h 1) (CR[9:2] bits) DEE1h 1) (CR[1:0] bits) DEE2h 1) (CR[9:2] bits) DEE3h 1) (CR[1:0] bits)
al), then the RC calibration values can still be obtained through these two address. Notes: In ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. Refer to note 5 in section 4.4 on page 12 for further details. See "ELECTRICAL CHARACTERISTICS" on page 67. for more information on the frequency and accuracy of the RC oscillator. To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN2326 for information on how to calibrate the RC frequency using an external reference signal. The ST7ULTRALITE also contains an Auto Wake Up RC oscillator. This RC oscillator should be enabled to enter Auto Wake-up from Halt mode. The Auto Wake Up RC oscillator can also be configured as the startup clock through the CKSEL[1:0] option bits (see section 14.1 on page 95). This is recommended for applications where very low power consumption is required. Switching from one startup clock to another can be done in run mode as follows (see Figure 9): Case 1: Switching from internal RC to AWU: 1. Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator 2. The RC_FLAG is cleared and the clock output is at 1. 3. Wait 3 AWU RC cycles till the AWU_FLAG is set 4. The switch to the AWU clock is made at the positive edge of the AWU clock signal 5. Once the switch is made, the internal RC is stopped Case 2: Switching from AWU RC to internal RC: 1. Reset the RC/AWU bit to enable the internal RC oscillator
RCCR R CCRH0 R CCRL0 R CCRH1 R CCRL1
Conditions VDD= 5 V TA=25C fRC=8MHz VDD=3.3V TA=25C fRC=8MHz
1. DEE0h, DEE1h, DEE2h and DEE3h are located in a reserved area but are special bytes containing also the RC calibration values which are read-accessible only in user mode. If all the Flash space (including the RC calibration value locations) has been erased (after the read-out protection remov-
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SUPPLY, RESET AND CLOCK MANAGEMENT (Cont'd) 2. Using a 4-bit counter, wait until 8 internal RC 3. When the external clock is selected, the AWU cycles have elapsed. The counter is running on RC oscillator is always on. internal RC clock. Figure 9. Clock Switching 3. Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC cycles) Internal RC Set RC/AWU 4. The switch to the internal RC clock is made at AWU RC Poll AWU_FLAG until set the positive edge of the internal RC clock signal 5. Once the switch is made, the AWU RC is stopped Reset RC/AWU Notes: AWU RC Internal RC Poll RC_FLAG until set 1. When the internal RC is not selected, it is stopped so as to save power consumption. 2. When the internal RC is selected, the AWU RC is turned on by hardware when entering Auto Wake-Up from Halt mode.
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6.2 REGISTER DESCRIPTION MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR ) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 0 0 S MS
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read / Write Reset Value: 0000 0x00 (0xh)
7 0 CR1 CR0 0 0 LVDR F AVD F 0 AVDI E
Bits 7:1 = Reserved, must be kept cleared. Bit 0 = SMS Slow Mode select This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock fOSC or fOSC/32. 0: Normal mode (fCPU = fOSC 1: Slow mode (fCPU = fOSC/32)
Bit 7 = Reserved, must be kept cleared. Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy. Refer to section 6.1 on page 17. Bits 4:3 = Reserved, must be kept cleared. Bits 2:0 = System Integrity bits. Refer to Section 7.4 SYSTEM INTEGRITY MANAGEMENT (SI).
RC CONTROL REGISTER (RCCR) Read / Write Reset Value: 1111 1111 (FFh)
7 CR9 CR 8 CR7 CR6 C R5 CR4 C R3 0 CR2
Bits 7:0 = CR[9:2] RC Oscillator Frequency Adjustment Bits These bits, as well as CR[1:0] bits in the SICSR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy. The application can store the correct value for each voltage range in Flash memory and write it to this register at start-up. 00h = maximum available frequency FFh = lowest available frequency Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h.
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REGISTER DESCRIPTION (Cont'd) AVD THRESHOLD SELECTION REGISTER (AVD TH CR) Read / Write Reset Value: 0000 0011 (03h)
7 0 CK1 CK0 0 0 0 0 0 AVD1 AV D0 0 0 0
CLOCK CONTROLLER CONTROL/STATUS REGISTER (CKCNTCSR) Read / Write Reset Value: 0000 1001 (09h)
7 AWU_ FLAG RC_ FLAG 0 0 R C/ AW U
Bits 7:4 = Reserved, must be kept cleared. Bit 7 = Reserved, must be kept cleared. Bits 6:5 = CK[1:0] internal RC Prescaler Selection These bits are set by software and cleared by hardware after a reset. These bits select the prescaler of the internal RC oscillator. See Figure 10 on page 21 and the following table and note: Table 4. Internal RC Prescaler Selection bits
CK1 CK0 0 0 1 1 0 1 0 1 fOSC f RC fRC/2 fRC/4 fRC/8
Bit 3 = AWU_FLAG AWU Selection This bit is set and cleared by hardware 0: No switch from AWU to RC requested 1: AWU clock activated and temporization completed
Bit 2 = RC_FLAG RC Selection This bit is set and cleared by hardware 0: No switch from RC to AWU requested 1: RC clock activated and temporization completed Bit 1 = Reserved, must be kept cleared. Bit 0 = RC/AWU RC/AWU Selection 0: RC enabled 1: AWU enabled (default value)
Note: If the internal RC is used with a supply operating range below 3.3V, a division ratio of at least 2 must be enabled in the RC prescaler. Bits 4:2 = Reserved, must be kept cleared. Bits 1:0 = AVD Threshold Selection bits. Refer to Section 7.4 SYSTEM INTEGRITY MANAGEMENT (SI). Table 5. Clock Register Map and Reset Values
Address (Hex.) 0038h 0039h 003Ah 003Eh 003Fh Register Label M CCSR Reset Value R CCR Reset Value SICSR Reset Value A VDTHCR Reset Value C KCNTCSR Reset Value 0 CR9 1 0 0 0 0 CR8 1 CR1 CK1 0 0 0 CR 7 1 CR0 C K0 0 0 7 6 5
4
3
2
1
0 SMS 0 CR2 1 AVDIE 0 AVD 2 1 RC/AWU 1
0 CR6 1 0 0 0
0 CR5 1 0 0
0 CR4 1 LVD RF x 0
0 CR 3 1 AVDF 0 AVD1 1 0
AWU_FLAG RC_FLAG 1 0
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SUPPLY, RESET AND CLOCK MANAGEMENT (Cont'd) Figure 10. Clock Management Block Diagram
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2
RCCR SIC S R
CR1
CR0
Tunable internal RC Oscillator
RC/AWU CKCNTCSR
8MHz(fRC) Prescaler
8MHz 4MHz 2MHz 1MHz
Clock Controller RC OSC AWU CK Ext Clock
fOSC
AWU RC
33kHz
CKSEL[1:0] Option bits
CLKIN
f CLKIN
/2 DIVIDER
13-BIT LITE TIMER COUNTER fOSC fOSC 0
fLTIMER (1ms timebase @ 8 MHz fOSC)
fCPU TO CPU AND PERIPHER ALS
/32 DIVIDER
fOSC/32
1
SMS MCCSR
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6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 12: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Figure 12. These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 11: Figure 11. RESET Sequence Phases Active Phase depending on the RESET source 64 CPU clock cycle delay RESET vector fetch Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior. The 64 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock c ycles.
RESET
Active Phase INTERNAL RESET 64 CLOCK CYCLES FETCH VECTOR
Figure 12. Reset Block Diagram
VDD
RO N
RESE T
FILTER INTERNAL RESET
WATCHDOG RESET PULSE GENERATOR ILLEGAL OPCODE RESET 1) LVD RESET
Note 1: See "Illegal Opcode Reset" on page 64. for more details on illegal opcode reset conditions.
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RESET SEQUENCE MANAGER (Cont'd) 6.3.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 13). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 6.3.3 External Power-On RESET If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fCLKIN frequency. Figure 13. RESET Sequences VDD
VIT+(LVD) VIT-(LVD)
A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 6.3.4 Internal Low Voltage Detector (LVD) R ESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: Power-On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD
LVD RESET
EXTERNAL RESET
WATCHDOG RESET
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
th(RSTL)in
EXTERNAL RESET SOURCE
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (64 TCPU) VECTOR FETCH
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6.4 REGISTER DESCRIPTION MULTIPLEXED IO RESET CONTROL REGISTER 1 (MUXCR1) Read / Write once only Reset Value: 0000 0000 (00h)
7 MIR1 MIR1 MIR1 MIR1 MIR1 MIR1 MIR 5 4 3 2 1 0 9 0 MIR 8
MULTIPLEXED IO RESET CONTROL REGISTER 0 (MUXCR0) Read / Write once only Reset Value: 0000 0000 (00h)
7 0
MIR7 MIR6 MIR5 MIR4 MIR3 MIR2 MIR1 MIR0
Bits 15:0 = MIR[15:0]
This 16-bit register is read/write by software but can be written only once between two reset events. It is cleared by hardware after a reset; When both MUXCR0 and MUXCR1 registers are at 00h, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1. These registers are one-time writable only. To configure PA3 as general purpose output: After power-on / reset, the application program has to configure the I/O port by writing to these registers as described above. Once the pin is configured as an I/O output, it cannot be changed back to a reset pin by the application code. To configure PA3 as RESET: An internally generated reset (such as POR, LVD, WDG, illegal opcode) will clear the two registers and the pin will act again as a reset function. Otherwise, a power-down is required to put the pin back in reset configuration.
Table 6. Multiplexed IO Register Map and Reset Values
Address (Hex.) 0047h 0048h Register Label MUXCR0 Reset Value M UXCR1 Reset Value 7 MIR7 0 MIR15 0 6 MIR6 0 MIR14 0 5 MIR5 0 MIR13 0 4 MIR4 0 MIR12 0 3 MIR3 0 MIR11 0 2 MIR2 0 MIR10 0 1 MIR1 0 MIR9 0 0 MIR0 0 MIR8 0
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7 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: Maskable hardware interrupts as listed in Table 7, "Interrupt Mapping," on page 26 and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 14. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. The I bit of the CC register is set to prevent additional interrupts. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit is cleared and the main program resumes. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping table). 7.1 NON MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It is serviced according to the flowchart in Figure 14. 7.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the HALT low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described in the I/O ports section), a low level on an I/O pin, configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity. 7.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: The I bit of the CC register is cleared. The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: Writing "0" to the corresponding bit in the status register or Access to the status register while the flag is set followed by a read or write of an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (cont'd) Figure 14. Interrupt Processing Flowchart
FROM RESET I BIT SET? Y N
N
INTERRUPT PENDING? Y
FETCH NEXT INSTRUCTION
N
IRET? Y
STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT
Table 7. Interrupt Mapping
N Source Block RES ET TRAP 0 1 2 3 4 5 6
2)
Description Reset Software Interrupt Auto Wakeup Interrupt External Interrupt 0 External Interrupt 1 External Interrupt 2 Not used External Interrupt 3 External Interrupt 4 AVD interrupt AT TIMER Output Compare Interrupt AT TIMER Overflow Interrupt
2)
Register Label N/A AW UCSR
Priority Order Highest Priority
Exit from HALT yes no yes 1) yes
Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
AW U e i0 ei1 ei2 ei3 ei4
2)
N/A
no yes no
2)
7 8 9 10 11 12 13
SI AT TIMER
SICSR PWMxCS R or ATCSR ATCSR LTCSR LTCSR Lowest Priority
no no yes 3) no yes 3) no no
LITE TIMER
LITE TIMER Input Capture Interrupt LITE TIMER RTC1 Interrupt Not used Not used
Notes: 1. This interrupt exits the MCU from "Auto Wake-up from HALT" mode only. 2. This interrupt exits the MCU from "WAIT" and "ACTIVE-HALT" modes only. Moreover, IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in HALT and AWUFH mode 3. These interrupts exit the MCU from "ACTIVE-HALT" mode only.
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INTERRUPTS (Cont'd) EXTERNAL INTERRUPT CONTROL REGISTER 1 (EICR1) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 IS21 IS20 IS11 IS10 IS01 0 IS00
EXTERNAL INTERRUPT CONTROL REGISTER 2 (EICR2) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 IS41 IS40 IS31 0 IS30
Bits 7:6 = Reserved Bits 5:4 = IS2[1:0] ei2 sensitivity These bits define the interrupt sensitivity for ei2 according to Table 8. Bits 3:2 = IS1[1:0] ei1 sensitivity These bits define the interrupt sensitivity for ei1 according to Table 8. Bits 1:0 = IS0[1:0] ei0 sensitivity These bits define the interrupt sensitivity for ei0 according to Table 8. Notes: 1. These 8 bits can be written only when the I bit in the CC register is set. 2. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Refer to section "External interrupt function" on page 41.
Bits 7:4 = Reserved Bits 3:2 = IS4[1:0] ei4 sensitivity These bits define the interrupt sensitivity for ei1 according to Table 8. Bits 1:0 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei0 according to Table 8. Notes: 1. These 8 bits can be written only when the I bit in the CC register is set. 2. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Refer to section "External interrupt function" on page 41. 3. IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in HALT and AWUFH modes.
Table 8. Interrupt Sensitivity Bits
ISx1 ISx0 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
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7.4 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register. Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to "Illegal Opcode Reset" on page 64 for further details. 7.4.1 Low Voltage Detector (LVD) The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: VIT+(LVD) when VDD is rising VIT-(LVD) when VDD is falling The LVD function is illustrated in Figure 15. The voltage threshold can be configured by option byte to be low, medium or high. See section 14.1 on page 95. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD), the MCU can only be in two modes: under full software control Figure 15. Low Voltage Detector vs Reset
VDD
in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 63 on page 87 and note 4. The LVD is an optional function which can be selected by option byte. See section 14.1 on page 95. It allows the device to be used without any external RESET circuitry. If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly. Make sure the right combination of LVD and AVD thresholds is used as LVD and AVD levels are not correlated. Refer to section 12.3.2 on page 70 and section 12.3.3 on page 70 for more details. Caution: If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will clear the watchdog flag.
Vhys V I T + (LVD) VIT-(LVD)
RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) Figure 16. Reset and Supply Management Block Diagram
WATCHDOG TIMER (WDG)
STATUS FLAG
SYSTEM INTEGRITY MANAGEMENT RESET SEQUENCE RESET MANAGER (RSM) SICSR 0 7 1 1 0 0 LVD AVD AVD RF F IE 0 AVD Interrupt Request
LOW VOLTAGE VSS VDD DETECTOR (LVD)
AUXILIARY VOLTAGE DETECTOR (AVD)
7.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply voltage (VAVD). The VIT-(AVD) reference value for falling voltage is lower than the VIT+(AVD) reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only.
7.4.2.1 Monitoring the VDD Main Supply. The AVD threshold is selected by the AVD[1:0] bits in the AVDTHCR register. If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit is set). In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 17. The interrupt on the rising edge is used to inform the application that the VDD warning state is over Note: Make sure the right combination of LVD and AVD thresholds is used as LVD and AVD levels are not correlated. Refer to section 12.3.2 on page 70 and section 12.3.3 on page 70 for more details.
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) Figure 17. Using the AVD to Monitor VDD VDD Early Warning Interrupt (Power has dropped, MCU not not yet in reset)
Vh y s t
VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD)
AVDF bit AVD INTERRUPT REQUES T IF AVDIE bit = 1
0
1
RES ET
1
0
INTERRUPT Cleared by reset
INTERRUPT Cleared by hardware
LVD RESET
7.4.3 Low Power Modes
Mode WAIT H AL T Description No effect on SI. AVD interrupts cause the device to exit from Wait mode. The SICSR register is frozen. The AVD remains active but the AVD interrupt cannot be used to exit from Halt mode.
7.4.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt Event AVD event Enable Event Control Flag Bit AVDF AVDIE Exit from Wait Yes Exit from Halt No
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read / Write Reset Value: 0000 0x00 (0xh)
7 0 C R1 CR0 0 0 0 LVDRF AVDF AVDIE
Bit 7 = Reserved, must be kept cleared. Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy. Refer to section 6.1 on page 17. Bits 4:3 = Reserved, must be kept cleared. Bit 2 = LVDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared when read. See WDGRF flag description in Section 10.1 for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined. Note: If the selected clock source is one of the two internal ones, and if VDD remains below the selected LVD threshold during less than TAWU (33us typ.), the LVDRF flag cannot be set even if the device is reset by the LVD. If the selected clock source is the external clock (CLKIN), the flag is never set if the reset occurs during Halt mode. In run mode the flag is set only if fCLKIN is greater than 10MHz. Bit 1 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is generated when the AVDF bit is set. Refer to Figure 17 for additional details 0: VDD over AVD threshold 1: VDD under AVD threshold
Bit 0 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled AVD THRESHOLD SELECTION REGISTER (AVD TH CR) Read / Write Reset Value: 0000 0011 (03h)
7 0 CK1 C K0 0 0 0 0 AVD1 AVD0
Bit 7 = Reserved, must be kept cleared. Bits 6:5 = CK[1:0] internal RC Prescaler Selection Refer to Section 6.1 INTERNAL RC OSCILLATOR ADJUSTMENT on page 17. Bits 4:2 = Reserved, must be kept cleared. Bits 1:0 = AVD[1:0] AVD Threshold Selection These bits are set and cleared by software and set by hardware after a reset. They select the AVD threshold. Table 9. AVD Threshold Selection bits
AVD1 AVD0 0 0 1 1 0 1 0 1 Functionality Low Medium High AVD off
Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.
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REGISTER DESCRIPTION (Cont'd) Table 10. System Integrity Register Map and Reset Values
Address (Hex.) 003Ah 003Eh Register Label SICSR Reset Value A VDTHCR Reset Value 7 6 5 4 3 2 LVDR F x 0 1 AVDF 0 AVD1 1 0 AVD IE 0 A VD2 1
0 0
1 CK1 0
1 CK0 0
0 0
0 0
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8 POWER SAVING MODES
8.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 18): Slow Wait (and Slow-Wait) Active Halt Auto Wake up From Halt (AWUFH) Halt After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency (fOSC). From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 18. Power Saving Mode Transitions
High RUN SLOW WAIT SLOW WAIT ACTIVE HALT HALT Low PO WER CONS UMPTION
fOSC
8.2 SLOW MODE This mode has two targets: To reduce power consumption by decreasing the internal clock in the device, To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by the SMS bit in the MCCSR register which enables or disables Slow mode. In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked at this lower frequency. Notes: SLOW-WAIT mode is activated when entering WAIT mode while the device is already in SLOW mode. Figure 19. SLOW Mode Clock Transition
fOSC/32 fCPU fOSC
SMS
NORMAL RUN MODE REQUEST
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POWER SAVING MODES (Cont'd) 8.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 20. Figure 20. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS CPU I BI T ON ON OFF 0
WFI I N S T R U C T I O N
N RESE T N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I BI T ON OFF ON 0 Y
64 CPU CLOCK CYCLE D EL AY
OSCILLATOR PERIPHERALS CPU I BI T
ON ON ON X 1)
FETCH RESE T VECTO R OR SERVICE INTERRUPT
Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 8.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the LTCSR/ATCSR register status as shown in the following table:.
ATCSR LTCSR ATCSR ATCSR OVFIE TBIE bit CK1 bit CK0 bit bit 0 0 0 1 x x 0 1 x 1 x x 1 x 0 0 x 1 x 1 AC TIVE-HALT mode enabled H A L T INSTR UCTIO N (Active Halt enabled) AC TIVE-HALT mode disabled Meaning
Figure 21. ACTIVE-HALT Timing Overview
RUN ACTIVE HA LT 64 CPU CYCLE DELAY 1) RUN
RESET OR HA LT INTER RUPT IN STRUCTION [Active Halt Enabled]
FE TCH VECTOR
Figure 22. ACTIVE-HALT Mode Flow-chart
OSCILLATOR ON PERIPHERALS 2) OFF CP U OFF I BI T 0
8.4.1 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the `HALT' instruction when active halt mode is enabled. The MCU can exit ACTIVE-HALT mode on reception of a Lite Timer / AT Timer interrupt or a RESET. When exiting ACTIVE-HALT mode by means of a RESET, a 64 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by fetching the reset vector which woke it up (see Figure 22). When exiting ACTIVE-HALT mode by means of an interrupt, the CPU immediately resumes operation by servicing the interrupt vector which woke it up (see Figure 22). When entering ACTIVE-HALT mode, the I bit in the CC register is cleared to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In ACTIVE-HALT mode, only the main oscillator and the selected timer counter (LT/AT) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). Caution: As soon as ACTIVE-HALT is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET if the WDGHALT bit is reset. This means that the device cannot spend more than a defined delay in this power saving mode.
N RE SET N Y INTERRUPT 3) Y OSCILLATOR ON PERIPHERALS 2) OFF CP U ON I BI T X 4) 64 CPU CLOC K CYC LE DELAY OSCILLATOR PERIPHERALS CP U I BI T S ON ON ON X 4)
FETC H RES ET VEC TOR OR SERVICE INTERRUPT
Notes: 1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET. 2. Peripherals clocked with an external clock source can still be active. 3. Only the Lite Timer RTC and AT Timer interrupts can exit the MCU from ACTIVE-HALT mode. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 8.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when active halt mode is disabled. The MCU can exit HALT mode on reception of either a specific interrupt (see Table 7, "Interrupt Mapping," on page 26) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the main oscillator is immediately turned on and the 64 CPU cycle delay is used to stabilize it. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 24). When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see section 14.1 on page 95 for more details). Figure 23. HALT Timing Overview
RUN HALT 64 CPU CYCLE D ELAY RESET OR INTER RUPT FE TCH VECTOR RUN
Figure 24. HALT Mode Flow-chart
H AL T INSTRUCTION (Active Halt disabled) ENABLE W D GH A L T 1 ) 1 W ATCHDO G RE SET OSCILLATOR OFF PERIPHERALS 2) OFF CP U OFF I BI T 0 N RE SET N Y INTERRUPT 3) Y OSCILLATOR PERIPHERALS CP U I BI T ON OFF ON X 4) 0 W ATCHDOG DISABLE
64 CPU CLOC K CYC LE DELAY 5) OSCILLATOR PERIPHERALS CP U I BI T S ON ON ON X 4)
FETC H RES ET VEC TOR OR SERVICE INTERRUPT
HA LT IN STRUCTION [Active Halt disabled]
Note: 1. A reset pulse of at least 42s must be applied when exiting from HALT mode.
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 7, "Interrupt Mapping," on page 26 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 5. The CPU clock must be switched to 1MHz (RC/8) or AWU RC before entering HALT mode.
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POWER SAVING MODES (Cont'd) 8.4.2.1 HALT Mode Recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode. When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).
Figure 25. AWUFH Mode Block Diagram AWU RC oscillator fAWU_RC to 8-bit Timer input capture
/64 divider
AWU F H prescaler/1 .. 255
AWUFH interrupt (ei0 source)
8.5 AUTO WAKE UP FROM HALT MODE Auto Wake Up From Halt (AWUFH) mode is similar to Halt mode with the addition of a specific internal RC oscillator for wake-up (Auto Wake-Up from Halt oscillator) which replaces the main clock which was active before entering HALT mode. Compared to ACTIVE-HALT mode, AWUFH has lower power consumption (the main clock is not kept running), but there is no accurate realtime clock available. It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set.
As soon as HALT mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the AWUPR register. The output of this prescaler provides the delay time. When the delay has elapsed, the following actions are performed: the AWUF flag is set by hardware, an interrupt wakes-up the MCU from Halt mode, the main oscillator is immediately turned on and the 64 CPU cycle delay is used to stabilize it. After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU flag and its associated interrupt are cleared by software reading the AWUCSR register. To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency fAWU_RC and then calculating the right prescaler value. Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run mode. This connects fAWU_RC to the input capture of the 8-bit lite timer, allowing the fAWU_RC to be measured using the main oscillator clock as a reference timebase.
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POWER SAVING MODES (Cont'd) Similarities with Halt mode The following AWUFH mode behaviour is the same as normal Halt mode: The MCU can exit AWUFH mode by means of any interrupt with exit from Halt capability or a reset (see Section 8.4 ACTIVE-HALT AND HALT MODES). When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. Figure 26. AWUF Halt Timing Diagram tAWU RUN MODE
f CPU fAWU_RC
In AWUFH mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator). The compatibility of watchdog operation with AWUFH mode is configured by the WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the watchdog system is enabled, can generate a watchdog RESET.
HALT MODE
64 tCPU
RUN MODE
Clear by software
AWUFH interrupt
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Figure 27. AWUFH Mode Flow-chart
HA LT INSTRUCTION (Active-Halt disabled) (AWUCSR.AWUEN=1) ENABLE W D GH A L T 1 ) 1 W ATCHDO G RE SET AWU RC OSC ON MAIN OSC OFF PERIPHERALS 2) OFF CP U OFF I[1:0] BITS 10 0 W ATCHDOG DISABLE
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 7, "Interrupt Mapping," on page 26 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
N RE SET N Y INTERRUPT 3) Y AWU RC OSC OFF MAIN OSC ON PERIPHERA LS OFF CP U ON I[1:0] BITS XX 4) 64 CPU CLOCK C YCL E DE LAY AWU RC OSC OFF MAIN OSC ON PERIPHERA LS O N CP U ON I[1:0] BITS XX 4) FETC H RES ET VEC TOR OR SERVICE INTERRUPT
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POWER SAVING MODES (Cont'd) 8.5.1 Register Description AWUFH CONTROL/STATUS REGISTER (AWU CSR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 AWU AWU A W U F M EN
AWUFH PRESCALER REGISTER (AWUPR) Read / Write Reset Value: 1111 1111 (FFh)
7 0
A W U A W U A W U A W U A W U A WU A WU A W U P R7 P R6 P R5 PR4 PR3 PR2 PR1 PR0
Bits 7:3 = Reserved. Bit 2= AWUF Auto Wake Up Flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value. 0: No AWU interrupt occurred 1: AWU interrupt occurred Bit 1= AWUM Auto Wake Up Measurement This bit enables the AWU RC oscillator and connects its output to the input capture of the 8-bit Lite timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compensate this dispersion by providing the right value in the AWUPRE register. 0: Measurement disabled 1: Measurement enabled Bit 0 = AWUEN Auto Wake Up From Halt Enabled This bit enables the Auto Wake Up From Halt feature: once HALT mode is entered, the AWUFH wakes up the microcontroller after a time delay dependent on the AWU prescaler value. It is set and cleared by software. 0: AWUFH (Auto Wake Up From Halt) mode disabled 1: AWUFH (Auto Wake Up From Halt) mode enabled Note: whatever the clock source, this bit should be set to enable the AWUFH mode once the HALT instruction has been executed. Table 11. AWU Register Map and Reset Values
Address (Hex.) 0049h 004Ah
Bits 7:0= AWUPR[7:0] Auto Wake Up Prescaler These 8 bits define the AWUPR Dividing factor (as explained below:
AW UPR[7:0] 00h 01h ... FEh FFh Dividing factor Forbidden 1 ... 254 255
In AWU mode, the period that the MCU stays in Halt Mode (tAWU in Figure 26 on page 38) is defined by
t
AWU
1 = 64 × A W U P R × ------------------------- + t RCSTRT f AWURC
This prescaler register can be programmed to modify the time that the MCU stays in Halt mode before waking up automatically. Note: If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately after a HALT instruction, or the AWUPR remains unchanged.
Register 7 6 5 4 3 2 1 0 Label A WU P R A W U P R 7 A W U P R 6 A W U P R 5 A W U P R 4 A W U P R 3 A WU P R 2 A W U P R 1 A W U P R 0 Reset Value 1 1 1 1 1 1 1 1 A WU C S R 0 0 0 0 0 A WU F A WU M A WU E N Reset Value
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9 I/O PORTS
9.1 INTRODUCTION The I/O port offers different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. An I/O port contains up to 6 pins. Each pin (except PA3/RESET) can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: Data Register (DR) Data Direction Register (DDR) and one optional register: Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 28 9.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. PA3 cannot be configured as input. 9.2.1.1 External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. For this reason if one of the interrupt pins is tied low, it may mask the others. External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by the OR register. To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the OR register bit and configuring the appropriate sensitivity again. Caution: In case a pin level change occurs during these operations (asynchronous signal input), as interrupts are generated according to the current sensitivity, it is advised to disable all interrupts before and to reenable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge. This corresponds to the following steps: 1. To enable an external interrupt: set the interrupt mask with the SIM instruction (in cases where a pin level change could occur) select rising edge enable the external interrupt through the OR register select the desired sensitivity if different from rising edge reset the interrupt mask with the RIM instruction (in cases where a pin level change could occur) 2. To disable an external interrupt: set the interrupt mask with the SIM instruction SIM (in cases where a pin level change could
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occur) select falling edge disable the external interrupt through the OR register select rising edge 9.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VS S VDD Open-drain Vss Floating
Note: When switching from input to output mode, the DR register has to be written first to drive the
correct level on the pin as soon as the port is configured as an output. 9.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming under the following conditions: When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in floating input mode. In this case, the pin state is also digitally readable by addressing the DR register. Notes: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
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Figure 28. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE O UT PUT 1 0 ALTERNATE EN ABLE DR VDD P-BUFFER (see table below) PULL-UP (see table below) VDD
DDR PULL-UP CON DITION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIG GER ANALO G INPUT DIO D ES (see table below) PA D
OR
EXTE RNAL INTERR UPT SOURCE (eix)
Table 12. I/O Port Mode Options
Configuration Mode Input O u tput Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) Pull-Up Off On Off P-Buffer Off On Off On On Diodes to VDD t o VS S
Legend:NI - not implemented Off - implemented not activated On - implemented and activated
DATA BUS
DR SEL
1 0
ALTERNATE INPUT FROM OTHE R BITS
POLA RITY SELECTION
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I/O PORTS (Cont'd) Table 13. I/O Port Configurations
Hardware Configuration
VDD RPU PAD PULL-UP CONDITION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
ALTERNATE INPUT FROM OTHER PINS INTERRUPT CONDITION POLARITY SELECTION ANALOG INPUT EXTERNAL INTERRUPT SOURCE (eix)
INPUT 1)
VDD
DR REGISTER ACCESS
OPEN-DRAIN OUTPUT 2)
RPU PAD DR REGISTER R/W DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
VDD
DR REGISTER ACCESS
PUSH-PULL OUTPUT 2)
RPU PAD DR REGISTER R/W DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.3 UNUSED I/O PINS Unused I/O pins must be connected to fixed voltage levels. Refer to Section 12.8. 9.4 LOW POWER MODES
Mode WAIT H AL T Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode.
9.5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event External interrupt on selected external event Enable Event Control Flag Bit DDRx OR x Exit from Wait Yes Exit from Halt Yes
9.6 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 29. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 29. Interrupt I/O Port State Transitions
01
INPUT floating/pull-up interrupt
00
INPUT floating (reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
XX
= DDR, OR
The I/O port register configurations are summarised in the following table: Table 14. Port Configuration
Port Port A Pin name PA0:2, PA4:5 PA3 Input (DDR=0) OR = 0 OR = 1 floating pull-up interrupt Output (DDR=1) OR = 0 OR = 1 open drain push-pull open drain push-pull
Note: after reset, to configure PA3 as a general purpose output, the application has to program the MUXCR0 and MUXCR1 registers. See section 6.4 on page 24
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I/O PORTS (Cont'd) Table 15. I/O Port Register Map and Reset Values
Address (Hex.) 0000h 0001h 0002h Register Label P ADR Reset Value P ADDR Reset Value P A OR Reset Value 7 M SB 0 M SB 0 M SB 0 6 5 4 3 2 1 0 LSB 0 LSB 0 LSB 0
0 0 0
0 0 0
0 0 0
0 1 0
0 0 0
0 0 1
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10 ON-CHIP PERIPHERALS
10.1 LITE TIMER (LT) 10.1.1 Introduction The Lite Timer can be used for general-purpose timing functions. It is based on a free-running 13bit upcounter with two software-selectable timebase periods, an 8-bit input capture register and watchdog function. 10.1.2 Main Features Realtime Clock 13-bit upcounter 1 ms or 2 ms timebase period (@ 8 MHz fOSC) Maskable timebase interrupt Input Capture 8-bit input capture register (LTICR) Maskable interrupt with wakeup from Halt Mode capability Figure 30. Lite Timer Block Diagram
fLTIMER
To 12-bit AT TImer
Watchdog Enabled by hardware or software (configurable by option byte) Optional reset on HALT instruction (configurable by option byte) Automatically resets the device unless disable bit is refreshed Software reset (Forced Watchdog reset) Watchdog reset status flag
fWDG fOSC 13-bit UPCOUNTER /2 fLTIMER 1
WA TCHDOG
WATCHDOG RESET
Timebase 1 or 2 ms 0 (@ 8MHz fOSC)
LTICR
8 MSB
LTIC
8-bit INPUT CAPTURE REGISTER LTCSR
ICIE 7 ICF TB TBIE TBF WDG RF WDGE WDGD 0
LTTB INTERRUPT REQUEST LTIC INTERRUPT REQUEST
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LITE TIMER (Cont'd) 10.1.3 Functional Description The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of fOSC. A counter overflow event occurs when the counter rolls over from 1F39h to 00h. If fOSC = 8 MHz, then the time period between two counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the LTCSR register. When the timer overflows, the TBF bit is set by hardware and an interrupt request is generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register. 10.1.3.1 Watchdog The watchdog is enabled using the WDGE bit. The normal Watchdog timeout is 2ms (@ fosc = 8 MHz ), after which it then generates a reset. To prevent this watchdog reset occuring, software must set the WDGD bit. The WDGD bit is cleared by hardware after tWDG. This means that software must write to the WDGD bit at regular intervals to prevent a watchdog reset occurring. Refer to Figure 31. If the watchdog is not enabled immediately after reset, the first watchdog timeout will be shorter than 2ms, because this period is counted starting from reset. Moreover, if a 2ms period has already elapsed after the last MCU reset, the watchdog reset will take place as soon as the WDGE bit is set. For these reasons, it is recommended to enable the Watchdog immediately after reset or else to set the WDGD bit before the WGDE bit so a watchdog reset will not occur for at least 2ms. Note: Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals. Figure 31. Watchdog Timing Diagram
A Watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the WDGRF bit has to be set. The WDGRF bit also acts as a flag, indicating that the Watchdog was the source of the reset. It is automatically cleared after it has been read. Caution: When the WDGRF bit is set, software must clear it, otherwise the next time the watchdog is enabled (by hardware or software), the microcontroller will be immediately reset. Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGE bit in the LTCSR is not used. Refer to the Option Byte description in the "device configuration and ordering information" section. Using Halt Mode with the Watchdog (option) If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be used when the watchdog is enabled. In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite Timer stops counting and is no longer able to generate a Watchdog reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 64 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state). If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
HARDWARE CLEARS WDGD BIT tWDG (2ms @ 8MHz fOSC)
fWDG WDGD BIT INTERN AL WATCHDOG RESET
SOFTWARE SETS WDGD BIT WATCHDOG RESET
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LITE TIMER (Cont'd) Input Capture The 8-bit input capture register is used to latch the free-running upcounter after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and the LTICR register contains the MSB of the free-running upcounter. An interrupt is generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register. The LTICR is a read only register and always contains the data from the last input capture. Input capture is inhibited if the ICF bit is set. 10.1.4 Low Power Modes
M ode WAIT A CTIVE-HALT HALT Description No effect on Lite timer No effect on Lite timer Lite timer stops counting
10.1.5 Interrupts
Interrupt Event Timebase Event IC Event Event Flag TBF ICF Enable Control Bit TBIE ICIE Exit Exit from from Wait Halt Yes Yes No No Exit from ActiveHalt Yes No
Note: The TBF and ICF interrupt events are connected to separate interrupt vectors (see Interrupts chapter). They generate an interrupt if the enable bit is set in the LTCSR register and the interrupt mask in the CC register is reset (RIM instruction).
Figure 32. Input Capture Timing Diagram
125ns (@ 8MHz fOSC)
fCPU fOSC CLEA RED BY S/W READING LTIC REGISTER
13-bit COUNTER
0001h
0002h
0003h
0004h
0005h
0006h
0007h
LTIC PIN ICF FLAG LTIC R R EGIST E R xxh 04h 07h
t
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LITE TIMER (Cont'd) 10.1.6 Register Description LITE TIMER CONTROL/STATUS REGISTER (LTCSR) Read / Write Reset Value: 0000 0x00 (0xh)
7 ICIE ICF TB TBIE TBF 0 W DG WD G WDG E R D
Bit 2 = WDGRF Force Reset/ Reset Status Flag This bit is used in two ways: it is set by software to force a watchdog reset. It is set by hardware when a watchdog reset occurs and cleared by hardware or by software. It is cleared by hardware only when an LVD reset occurs. It can be cleared by software after a read access to the LTCSR register. 0: No watchdog reset occurred. 1: Force a watchdog reset (write), or, a watchdog reset occurred (read). Bit 1 = WDGE Watchdog Enable This bit is set and cleared by software. 0: Watchdog disabled 1: Watchdog enabled Bit 0 = WDGD Watchdog Reset Delay This bit is set by software. It is cleared by hardware at the end of each tWDG period. 0: Watchdog reset not delayed 1: Watchdog reset delayed LITE TIMER INPUT CAPTURE REGISTER (LTICR) Read only Reset Value: 0000 0000 (00h)
7 0
Bit 7 = ICIE Interrupt Enable. This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled Bit 6 = ICF Input Capture Flag. This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred Note: After an MCU reset, software must initialise the ICF bit by reading the LTICR register Bit 5 = TB Timebase period selection. This bit is set and cleared by software. 0: Timebase period = tOSC * 8000 (1ms @ 8 MHz) 1: Timebase period = tOSC * 16000 (2ms @ 8 MHz) Bit 4 = TBIE Timebase Interrupt enable. This bit is set and cleared by software. 0: Timebase (TB) interrupt disabled 1: Timebase (TB) interrupt enabled Bit 3 = TBF Timebase Interrupt Flag. This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No counter overflow 1: A counter overflow has occurred
IC R7 ICR6 ICR5 ICR4 IC R3 ICR2 ICR1 ICR0
Bits 7:0 = ICR[7:0] Input Capture Value These bits are read by software and cleared by hardware after a reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling edge occurs on the LTIC pin.
Table 16. Lite Timer Register Map and Reset Values
Address (Hex.) Register Label 0B 0C LTCSR Reset Value LTICR Reset Value 7 ICIE 0 ICR7 0 6 ICF 0 ICR6 0 5 TB 0 ICR5 0 4 TBIE 0 ICR4 0 3 TBF 0 ICR3 0 2 WDG R F x ICR2 0 1 W D GE 0 ICR1 0 0 WD GD 0 ICR0 0
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10.2 12-BIT AUTORELOAD TIMER (AT) 10.2.1 Introduction The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based on a freerunning 12-bit upcounter with a PWM output channel. 10.2.2 Main Features 12-bit upcounter with 12-bit autoreload register (ATR) Maskable overflow interrupt Figure 33. Block Diagram
7 ATCSR 0 0 0 CK1 CK 0 0 OVF O V F I E C M P I E OVF INTERRUPT REQUEST
PWM signal generator Frequency range 2KHz-4MHz (@ 8 MHz fCPU) Programmable duty-cycle Polarity control Maskable Compare interrupt Output Compare Function
fLTIMER (1 ms timebase @ 8MHz) f CPU
CMPF0 fCOUNTER CNTR 12-BIT UPCOUNTER
CMP INTERRUPT REQUEST
Update on OVF Event
12-BIT AUTORELOAD VALUE
ATR OE0 bit PWM GENERATION OE0 bit CMPF0 bit 0 COM PPARE OP0 bit fPWM POLARITY OUTPUT CONTROL DCR0H DCR0L
Preload
Preload on OVF Event IF OE0=1
PW M0
1
12-BIT DUTY CYCLE VALUE (shadow)
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12-BIT AUTORELOAD TIMER (Cont'd) 10.2.3 Functional Description PWM Mode This mode allows a Pulse Width Modulated signals to be generated on the PWM0 output pin with minimum core processing overhead. The PWM0 output signal can be enabled or disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is configured as output pushpull alternate function. Note: CMPF0 is available in PWM mode (see PWM0CSR description on page 55). PWM Frequency and Duty Cycle The PWM signal frequency (fPWM) is controlled by the counter period and the ATR register value. fPWM = fCOUNTER / (4096 - ATR) Following the above formula, if fCPU is 8 MHz, the maximum value of fPWM is 4 Mhz (ATR register value = 4094), and the minimum value is 2 kHz (ATR register value = 0). Note: The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case. At reset, the counter starts counting from 0. Software must write the duty cycle value in the DCR0H and DCR0L preload registers. The DCR0H register must be written first. See caution below.
When a upcounter overflow occurs (OVF event), the ATR value is loaded in the upcounter, the preloaded Duty cycle value is transferred to the Duty Cycle register and the PWM0 signal is set to a high level. When the upcounter matches the DCRx value the PWM0 signals is set to a low level. To obtain a signal on the PWM0 pin, the contents of the DCR0 register must be greater than the contents of the ATR register. The polarity bit can be used to invert the output signal. The maximum available resolution for the PWM0 duty cycle is: Resolution = 1 / (4096 - ATR) Note: To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum resolution and assuming that DCR=ATR, a 0% or 100% duty cycle can be obtained by changing the polarity . Caution: As soon as the DCR0H is written, the compare function is disabled and will start only when the DCR0L value is written. If the DCR0H write occurs just before the compare event, the signal on the PWM output may not be set to a low level. In this case, the DCRx register should be updated just after an OVF event. If the DCR and ATR values are close, then the DCRx register shouldbe updated just before an OVF event, in order not to miss a compare event and to have the right signal applied on the PWM output.
Figure 34. PWM Function
4095 DUTY CYCLE R EGIST ER (DCR0)
COUNTER
AUT O-RELO A D RE GISTER (ATR) 000
t
PWM0 OUTPUT
WITH OE0=1 AND OP0=0 WITH OE0=1 AND OP0=1
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12-BIT AUTORELOAD TIMER (Cont'd) Figure 35. PWM Signal Example
fCOUNTER ATR= FFDh PWM0 OUTPUT WITH OE0=1 AND OP0=0 COUNTER FFDh FFEh FFFh FFDh FF Eh FFFh FFDh FFEh
DCR0=FFEh
t
Output Compare Mode To use this function, the OE bit must be 0, otherwise the compare is done with the shadow register instead of the DCRx register. Software must then write a 12-bit value in the DCR0H and DCR0L registers. This value will be loaded immediately (without waiting for an OVF event). The DCR0H must be written first, the output compare function starts only when the DCR0L value is written. When the 12-bit upcounter (CNTR) reaches the value stored in the DCR0H and DCR0L registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is generated if the CMPIE bit is set. Note: The output compare function is only available for DCRx values other than 0 (reset value). Caution: At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L value has not yet been written (in this case, the shadow register will contain the new DCR0H value and the old DCR0L value), then: If OE=1 (PWM mode): the compare is done between the timer counter and the shadow register (and not DCRx) if OE=0 (OCMP mode): the compare is done between the timer counter and DCRx. There is no PWM signal.
The compare between DCRx or the shadow register and the timer counter is locked until DCR0L is written. 10.2.4 Low Power Modes Mode Description The input frequency is divided SLOW by 32 WAIT No effect on AT timer AT timer halted except if CK0=1, A CT I V E - H A L T CK1=0 and OVFIE=1 HALT AT timer halted 10.2.5 Interrupts
Interrupt Event 1) O v erflow Event CMP Event Enable Exit Exit Event Control from from Flag Bit Wait Halt O VF OV F I E Yes No No Exit from ActiveHalt Yes2) No
CM PFx CMPIE Yes
Note 1: The interrupt events are connected to separate interrupt vectors (see Interrupts chapter). They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction). Note 2: only if CK0=1and CK1=0
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12-BIT AUTORELOAD TIMER (Cont'd) 10.2.6 Register Description TIMER CONTROL STATUS REGISTER (ATCS R) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 CK1 CK0 OVF 0 OVFIE CMPIE
Bit 0 = CMPIE Compare Interrupt Enable. This bit is read/write by software and clear by hardware after a reset. It allows to mask the interrupt generation when CMPF bit is set. 0: CMPF interrupt disabled 1: CMPF interrupt enabled
COUNTER REGISTER HIGH (CNTRH) Read only Reset Value: 0000 0000 (00h)
15 0 0 0 0 CN11 CN10 CN9 8 CN8
Bits 7:5 = Reserved, must be kept cleared.
Bits 4:3 = CK[1:0] Counter Clock Selection. These bits are set and cleared by software and cleared by hardware after a reset. They select the clock frequency of the counter.
Counter Clock Selection OFF fLTIMER (1 ms timebase @ 8 MHz) fCPU Reserved CK1 0 0 1 1 CK 0 0 1 0 1
COUNTER REGISTER LOW (CNTRL) Read only Reset Value: 0000 0000 (00h)
7 CN7 CN6 CN5 CN4 CN3 CN2 CN1 0 CN0
Bit 2 = OVF Overflow Flag. This b |
