where: S = start, Sr = repeated start, P = stop, A= acknowledge, nA = negative acknowledge addr = 7-bit slave address, w = write bit (0), r = read bit (1), index = 8-bit register address, data = 8-bit register data, [] = optional.
7/17
Application information
V M6 101
2.4.2
Alternate slave address selection
After power-on or after resuming from power-down, the 7-bit slave address is 0x10. If another slave device shares the same address, it is possible to remap the VM6101 to address 0x11 by performing the following operations: 1. 2. 3. Connect the INT pin to a pull-up resistor to VDD (1 M typ.). After power-on or power-down resume, issue a write command to set the ADDR_SEL bit of CONTROL register (i.e. write 0x10 at register address 0x02, slave address 0x10). At this time, the VM6101 samples the INT pin and sets its slave address accordingly: INT sampled low: 7-bit address = 0x10, INT sampled high: 7-bit address = 0x11.
Two VM6101 can thus coexist on the same bus; one should have its INT pin pulled low, the other one should have its INT pin pulled high (see Figure 5.).
3
Application information
Figure 5. Application diagram
+3.3V
+3.3V NC
VDD AMUX TEST GND
SCL SDA INT PD 1M
Rb
Rb
VM6101
Host Microcontroller SCL SDA GPIO0 GPIO1 GPIO2 GPIO3
I²C 7-bit addr = 0x10 +3.3V NC VM6101 VDD AMUX TEST GND SCL SDA INT PD 1M Optional +3.3V
I²C 7-bit addr = 0x11
Note: Rb value depends on bus capacitive load
8/17
VM6101
Register description
4
Note:
Register description
RO = Read Only; RW = Read/Write. Reserved bits must be written with 0s and return 0 upon read; Reserved bytes must not be accessed otherwise unpredictable results my occur.
Table 3.
Addr. 0x00 0x00 0x01 0x02
Register description
Bits [3:0] [7:4] [7:0] [6:0] [1:0] Def. 1 0 0x04 0x04 0 Name REVISION MASK N_PIXEL CONTROL CHSEL Chip revision (RO). Mask code (RO). (RO) Control register (RW) Channel select for comparator and PWM logic: 0: Y 1: R 2: G 3: B INT pin function select: 0: PWM generator output 1: Comparator logic output PWM polarity: 0: Normal (Thin pulse for low values, Wide pulses for high values) 1: Inverted. Address Select: when written with `1', the INT pin goes high impedance; after a duration T (defined below), the INT pin is sampled and returns to low impedance. The device slave address is set accordingly: INT sampled low: address = 0x20 INT sampled high: address = 0x22. Address select sampling window duration: 0: T = 160 s (default) 1: T = 80 s 2: T = 40 s 3: T = 20 us This duration allows for INT pin pull-up rise time. Reserved Reserved (RO). Y_STATUS Y-channel status register (RO). Reading this register will cause Y_CNT to be transferred to serial interface buffer. 5 MSBs are read as zeros. This bit is set after reset. Cleared after first read of STATUS register. This bit is set upon counter overflow: current counter values are invalid. When set, indicates that a new count value is available in the 4 registers here below. Description
2
1
INT_FSEL
3
0
PWM_POL
4
0
ADDR_ SEL
[6:5]
0
ADDR_SELW
7 0x03 0x04 [7:0] [2:0]
0 0 0x01
0 1 2
1 0 0
RESET OVERFLOW READY
9/17
Register description Table 3.
Addr. 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
VM6101
Register description (continued)
Bits [2:0] [7:0] [7:0] [7:0] [7:0] [2:0] [7:0] [7:0] [7:0] [7:0] [2:0] [7:0] [7:0] [7:0] [7:0] [2:0] [7:0] [7:0] [7:0] [5:0] 0 1 Def. 0 0 0 0 0x01 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x03 1 1 0 0 0 0 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0 Name Y_CNT3 Y_CNT2 Y_CNT1 Y_CNT0 R_STATUS R_CNT3 R_CNT2 R_CNT1 R_CNT0 G_STATUS G_CNT3 G_CNT2 G_CNT1 G_CNT0 B_STATUS B_CNT3 B_CNT2 B_CNT1 B_CNT0 TH_CFG EN_LO POL_LO EN_HI POL_HI INT_POL HYST TH_LO3 TH_LO2 TH_LO1 TH_LO0 TH_HI3 TH_HI2 TH_HI1 TH_HI0 Description Y channel count bits [26:24] (RO). 5 MSBs are read as zeros. Y channel count bits [23:16] (RO) Y channel count bits [15:8] (RO) Y channel count bits [7:0] (RO) R channel status register (RO). Refer to Y Channel for description. R channel count bits [26:24] (RO). 5 MSBs are read as zeros. R channel count bits [23:16] (RO) R channel count bits [15:8] (RO) R channel count bits [7:0] (RO) G channel status register (RO). Refer to Y Channel for description. G channel count bits [26:24] (RO). 5 MSBs are read as zeros. G channel count bits [23:16] (RO) G channel count bits [15:8] (RO) G channel count bits [7:0] (RO) B channel status register (RO). Refer to Y Channel for description. B channel count bits [26:24] (RO). 5 MSBs are read as zeros. B channel count bits [23:16] (RO) B channel count bits [15:8] (RO) B channel count bits [7:0] (RO) Comparator logic configuration (RW). 2 MSBs are reserved. Refer to Section 2.2: Comparator logic for programming details. Enable low threshold comparator (1 = enable, 0 = disable) Low threshold comparator output polarity Enable high threshold comparator (1 = enable, 0 = disable) High threshold comparator output polarity INT pin output polarity Enable hysteresis function Low threshold bits [26:24] (RW). 5 MSBs are read as zeros. Low threshold bits [23:16] (RW) Low threshold bits [15:8] (RW) Low threshold bits [7:0] (RW) High threshold bits [26:24] (RW). 5 MSBs are read as zeros. High threshold bits [23:16] (RW) High threshold bits [15:8] (RW) High threshold bits [7:0] (RW)
0x18
2 3 4 5
0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20
[2:0] [7:0] [7:0] [7:0] [2:0] [7:0] [7:0] [7:0]
10/17
VM6101 Table 3.
Addr. 0x21
Register description Register description (continued)
Bits [3:0] Def. 0x00 Name PWM_FREQ Description PWM output frequency (RW)(4 MSBs are reserved): n = 0 to 15 fPWM = fOSC * 2n-18, where fOSC = 3.6 MHz. PWM sensitivity (RW)(3 MSBs are reserved): n = 0 to 26 0 = high sensitivity, 26 = low sensitivity. Practical values lie between 9 and 18. Refer to Figure 4: PWM duty cycle versus illumination for typical behavior. Reserved.
0x22
[4:0]
0x00
PWM_SENS
0x22 ... 0x27 0x28 0x29 0x2A ... 0xFF
[7:0]
[7:0] [7:0] [7:0]
0x04 0x00
TEST_MOD TEST_SEL
Reserved (RW). Reserved (RW). Reserved.
11/17
Optical characteristics
VM6101
5
Table 4.
Symbol E Ev
Optical characteristics
Optical characteristics (1)
Parameter Irradiance range Illuminance range Conditions Min 0.0001 0.03 Typ Max 800 170k Unit Wm-2 lx
1. Using typical operating conditions: TA = 25 C, VDD = 3.3 V
Figure 6.
Spectral response
1.0 Red
1.2 Normalized response 1.0 0.8 0.6 0.4 0.2 0.0
Normaliz ed Sensitivity
0.8 Blue
Angular response
Gr een
Y
0.6
0.4
0.2
-90
0.0 400 -60
500 600 700 800 -30 0 Wave le n g t h (nm ) 60 30 Incident light angle (degrees)
900 90
1000
Figure 7.
1.2
Angular response
Figure 8.
Relative output versus temperature
1.1.100 2
G 1.3 1.0 R 1.3 1.050 B 1.2 0.1.2 8 Y 1.1 0.1..1 00 6 10 1.0 1.0 0.4 0.9 0.9 0.950 0.8 0.2 0.8 0.7 0.0.7 0 -10 0.900 0 10 20 30 40 50 60 70 80 - 90 0 -0 0 10 30 0 30 4030 0 60 7090 0 6 -1 -10 0 -10 20 0 30 40 50 060 70 80 2 56 8 Temperature (C) Tempeperate re (C) Temratur u (C)
Normalized sensitivity
1.0 0.8 0.6 0.4 0.2 0.0 -90 -60 -30 0 30 60 90 Incident light angle (degrees)
12/17
NNrmalazied d response oorm i l z e response Normalioemalized sensitivity N zr d sensitivity
VM6101
Electrical characteristics
6
Table 5.
Symbol VDD VIN TSTG TL ESDHBM ESDMM ESDCDM
Electrical characteristics
Absolute maximum ratings (Note 1, Note 2)
Parameter Supply voltage DC input voltage, all I/O pins Storage temperature Solder reflow peak temperature, JEDEC J STD-020 Human body model ESD rating, all pins, JESD22-A114-B Machine model ESD rating, all pins, JESD22-A115-B Charged device model ESD rating, all pins, JESD22-C101-C Min -0.5 -0.5 -4 0 Max 3.7 VDD + 0.5 85 245 2 200 500 Unit V V C C kV V V
Table 6.
Symbol TA VDD VIL
Recommended operating conditions
Parameter Operating temperature Supply voltage Input low voltage (SCL, SDA) Input low voltage (PD) Min 0 3.0 0 0 0.7 VDD 2 .0 4 4 Max 70 3.6 0.3 VDD 0.8 VDD Unit C V V V V V mA mA
VIH
Input high voltage (SCL, SDA) Input high voltage (PD)
IOL IOH
Output low current Output high current
Table 7.
Symbol VOL VOH IIL IDDPD IDD
DC electrical characteristics (Note 3)
Parameter Output low voltage (SDA, INT) Output high voltage (INT) Input leakage current Supply current, power-down Supply current, active Conditions IOL = max, VDD = min IOH = max, VDD = min All I/O pins PD low (Note 4) PD high (Note 4) 2 .4 -1 +1 1.0 1.1 Min Max 0.4 Unit V V A A mA
Table 8.
Symbol fOSC
AC electrical characteristics (Note 3)
Parameter Internal oscillator frequency Conditions Min Typ 3.6 Max Unit MHz
13/17
Electrical characteristics Table 9.
Symbol fSCL tLOW tHIGH tSU;STA tHD;STA tSU;DAT tHD;DAT tSU;STO tBUF tR tF Cb SCL clock frequency SCL clock low period SCL clock high period (Repeated) START condition setup time (Repeated) START condition hold time Data setup time Data hold time STOP condition setup time Bus free condition between START and STOP conditions Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Capacitive load for each bus line
VM6101
Serial interface timing (Note 3)
Parameter Min 0 4.7 4 .0 4.7 4.0 250 300 4.0 4 .7 300 300 400 Max 100 Unit kHz s s s s ns ns ns s ns ns pF
Figure 9.
Serial interface timing waveforms
Stop
SDA
Star t
Star t
Stop
tBUF S CL
tLOW
tR
tF
tHD;STA
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
tSU;STO
Note:
1
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Unless otherwise specified, all voltages are referenced to ground. Over recommended operating conditions, unless otherwise specified. Using typical operating conditions: TA = 25 C, VDD = 3.3 V
2 3 4
14/17
VM6101
Mechanical information
7
Mechanical information
Figure 10. 8-lead MLPD package outline
Symbol A A3 b D D2 E E2 e L 0.55 0.25 2.90 2.20 2.90 1.00 Min 0.65 Typ 0 .7 0.20 0.30 3.00 0.35 3.10 Max 0.75
2.350.652.45 0.7 3.00 1.15 3.10 1.25
2.20
0.65
2.35
1 0.60 .00 0.65 1.15 0.60
All dimensions in millimeters 0.55
Figure 11. Recommended PCB layout
15/17
Ordering information
VM6101
8
Ordering information
Table 10. Ordering information
Order code VM6101V008 VM6101V008/TR STV-6101-R01 Description 8-lead MLPD 3 x 3 x 0.7 mm, RoHS compliant, tray packing. 8-lead MLPD 3 x 3 x 0.7 mm, RoHS compliant, 13" tape and reel, 5000 parts/reel. VM6101 evaluation board
9
Revision history
Table 11.
Date 05-Jun-2006 14-Dec-2006 27-Apr-2007
Document revision history
Revision 1 2 3 Initial release Global update Updated Chapter 6: Electrical characteristics Chapter 4: Register description Updated the datasheet status to `New for New Design'. Changes
06-Jun-2008
4
16/17
VM6101
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
17/17
