Obsolete Product Datasheets | Application Specific for Imaging | Sensors for Imaging | Ambient Light Sensors

I2C color light sensor

Obsolete Product Datasheet

Format: (212 kb)

Last Updated: 06/06/2008

Pages: 17

Untitled Document

Generic Part Number

Orderable Part Number

Status

VM6101

VM6101V008

Obsolete

Related Information

Additional Information: Ambient light sensor

Additional Information: Ambient light sensor demonstration board

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VM6101
I²C color light sensor
Not For New Design

Features

Pinou t
VM6101V008 8-lead MLPD Top view SDA 1 SCL 2 INT GND
y x RB YG

4-channel Y+RGB photosensor, with integrated infrared filter Wide dynamic range light to frequency converters 2-wire serial interface, I²C and SMBus compatible PWM output for direct LCD backlight control Comparator logic with two programmable thresholds and hysteresis function Power down input 3.0 V to 3.6 V supply range Built-in clock generator, precision voltage and current references 3 4

8 TEST 7 AMUX 6 5
PD

Low profile Pb-free package (RoHS compliant)

Appl ication s

General purpose color measurement Automatic backlighting control Panel lighting White goods

bs O

let o

ro P e

du

(s) ct

eP Description let so Ob -

Optical center location: (+70, +35) m relative to package center.

Sensitive area: 220 x 240 m

od r

uc

VDD

s) t(

The VM6101 is a high dynamic range 4-channel CMOS photosensor suitable for ambient light sensing as well as color light sensing. Light intensity is converted linearly to a variable frequency signal. The signal period is readable through the two-wire serial interface. A direct PWM output is provided for power saving LCD backlighting applications, where backlighting intensity adapts to the ambient light level. Alternatively, this output can be used as an ambient light level detector output, with two user programmable thresholds. A power down input puts the VM6101 in ultra low power mode. The VM6101 is housed in an compact 8-lead surface mount clear plastic package, compliant to RoHS directive.

June 2008

Rev 4

1/17
www.st.com
17

This is information on a product still in production but not recommended for new designs.

Contents

VM6101

Contents
1 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 2. 2 2. 3 2. 4 Light measurement channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Comparator logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PWM generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Two-wire serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4.1 2.4.2 Message types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Alternate slave address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 4 5 6 7 8 9

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Optical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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VM6101

Pin description

1

Pin description
Table 1.
Pin 1 2 3

Pin description
Name SDA SCL INT Type I/O I/O I/O Description Serial interface data. Requires external pull-up to VDD. Serial interface clock. Requires external pull-up to VDD. Dual function output: - Comparator logic output - PWM generator output Input for serial interface 7-bit address select: - low = address 0x10 (default) - high = address 0x11 Requires external pull-up or pull-down resistor (1 M typically).

4 5 6

GND VDD PD

PWR Ground PWR Positive power supply AIN Power down control: - low = force low power standby - high = normal operation Reser ved. Do not connect. Reser ved. Connect to GND.

7 8

AMUX TEST

AIO AIN

2

Functional description
Figure 1.

Functional block diagram

O

bs

let o

Pr e

du o
Y R G B

(s) ct
Light to Frequency Conver ter (x4) Power-on Reset

so Ob 27-bit Counter

te le

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Register Bank

Serial Interface

SCL SDA

(x4) PWM Generator 3.6 MHz Oscillator Comparator Logic Pin Function Mux

PD VDD GND

INT

3/17

Functional description

VM6101

2.1

Light measurement channels
The VM6101 has four independent wide dynamic range photosensors and current-tofrequency converters. Each channel produces a digital output with a frequency proportional to the incoming light level on the photosensor. By construction, the device ensures automatic exposure control. Figure 2. Light-to-Frequency converter (L2F)

The output period is measured using a 27-bit free-running counter and the internal 3.6 MHz oscillator clock; counter values are then read through the serial interface. The typical light response is shown in Figure 3. below, obtained using a CIE D65 white point light source (~ daylight illumination) and no light diffuser. Figure 3. Light response

O u t pu t (count)

bs O

let o

10 0 01.0E+05

100001.0E+04

10001.0E+03 1 1

O ut p ut (count)

Pr e

du o

10 0 0001.0E+07

B G 6 10 0 001.0E+0R Y

(s) ct

so Ob B G R Y

te le

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uc d

s) t(

10

10

100 100

1 1000 000

Il an c i an L u m inlumen(lx)ce (lx)

4/17

VM6101 The light response can be approximated by:

Functional description

Y channel: R channel: G channel: B channel:

EvY = 1.58e6 x count -0.960 EvR = 3.34e6 x count -0.902 EvG = 4.92e6 x count -0.944 EvB = 8.03e6 x count -0.973

The response time is: t = count / fOSC + serial interface read time (about 200 s) Example: t = 9.3 ms for 300 lx. Each channel provides three status flags and a counter value:

RESET: This flag is set upon reset or power-down resume. The counter value is invalid and should be discarded. This flag is cleared after a status read operation. OVERFLOW: at least one counter overflow occurred: the counter value is invalid and should be discarded. This flag is cleared when a new valid counter value is available. READY: a new counter value is available. This flag is cleared immediately after the status register read. CNT: a 27-bit counter value, mapped in 4 consecutive bytes, MSB first and right justified.

Channel readout must always start by reading the corresponding status register. The suggested read operation is a 5-byte read operation starting at the status register address. Refer to Chapter 4: Register description for details.

2.2

Comparator logic

This function compares the light level (i.e. channel counter CNT) with two programmable thresholds (TH_LO and TH_HI) and drives the INT pin accordingly. The following table shows available configurations using TH_CFG register setup:

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5/17

Functional description Table 2.
EN_HI: EN_LO 00 01 0 POL_LO xor (CNT < TH_LO)
1 0 TH_LO TH_HI

VM6101 Threshold module configurations (TH_CFG register usage)
INT output 0 INT versus CNT (assumes INT_POL = 0)

(POL_LO = 0) 10 POL_HI xor (CNT < TH_HI)
1 0 TH_LO TH_HI

(POL_HI = 0) 11 HYST = 0: (POL_LO xor (CNT < TH_LO)) and (POL_HI xor (CNT < TH_HI))
1 0 TH_LO TH_HI

(POL_LO = 1, POL_HI = 0) HYST = 1: see diagram
1 0

(POL_LO = 1, POL_HI = 0)
Notes

1. Upon reset, the comparator logic is enabled (EN_HI:EN_LO = 01) with POL_LO = 1 and TH_LO = 0x0008. The INT pin is high when Y channel count > 8. 2. Assuming CONTROL= 0x04, i.e. comparator mode using Y channel count (default value for CONTROL register).

2.3

O

so b

(s) PWM generator t uc od Pr ete l

3. Ensure TH_LO < TH_HI otherwise unpredictable results may occur.

so Ob -

te le

ro P

TH_LO TH_HI

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s) t(

The pulse width modulator (PWM) generates a signal which may be used to directly control LCD backlight driver ICs according to ambient light level. There are three registers to control the PWM generator operation: PWM_FREQ register bits [4:0] sets the period of the PWM signal. This is adjustable from 12Hz to 400kHz. PWM_SENS register bits [4:0] sets the sensitivity of the PWM signal to light level. CONTROL register bit 2 = 0 to select PWM output at INT pin. CONTROL register bit 3 controls the polarity of the PWM output (default = 0).

For more details please refer to Chapter 4: Register description. The curve below shows typical PWM output duty cycle (default polarity) as a function of illumination, with sensitivity setting ranging from 9 to 18, corresponding to typical use cases (10 to 10000 lx illumination).

6/17

VM6101 Figure 4. PWM duty cycle versus illumination
1.2 1.2 1.0 1.0 0.8 PW M_SENS = 9 0.8 PW M_SENS = 9 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 -0.2 -0.1E+00 2 10E+00 1E+00 10E+00

Functional description

Du cycle Duty ty cycle

PW M_SENS = 18 PW M_SENS = 18

100E+00 1E+03 100E+0minance1(lx)03 E+ Illu 0 Illumination (lx)

10E+03 10E+03

100E+03 100E+03

2.4

Two-wire serial interface
The VM6101 two-wire serial interface supports the following features:

Standard-mode (100 kHz) I²C slave controller supporting 8-bit addressing (7-bit address = 0x10 or 0010 000). SMBus compliant. Data and clock deglitching filters (double sampling) 8-bit index, i.e. 256 on-chip register address space Multiple read or write with index auto-increment Alternate address (0x11) selectable

2.4.1

Message types

The VM6101 registers are accessed by serial bus byte-oriented transactions. The following message types are supported:

Master write: [...]

bs O

let o

Pr e

Master read: ~~[...]~~
~~Combined format: ~~[...]~~~~

du o

(s) ct

so Ob -

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where: S = start, Sr = repeated start, P = stop, A= acknowledge, nA = negative acknowledge addr = 7-bit slave address, w = write bit (0), r = read bit (1), index = 8-bit register address, data = 8-bit register data, [] = optional.

7/17

Application information

V M6 101

2.4.2

Alternate slave address selection
After power-on or after resuming from power-down, the 7-bit slave address is 0x10. If another slave device shares the same address, it is possible to remap the VM6101 to address 0x11 by performing the following operations: 1. 2. 3. Connect the INT pin to a pull-up resistor to VDD (1 M typ.). After power-on or power-down resume, issue a write command to set the ADDR_SEL bit of CONTROL register (i.e. write 0x10 at register address 0x02, slave address 0x10). At this time, the VM6101 samples the INT pin and sets its slave address accordingly: INT sampled low: 7-bit address = 0x10, INT sampled high: 7-bit address = 0x11.

Two VM6101 can thus coexist on the same bus; one should have its INT pin pulled low, the other one should have its INT pin pulled high (see Figure 5.).

3

Application information
Figure 5. Application diagram
+3.3V

+3.3V NC

VDD AMUX TEST GND

SCL SDA INT PD

Rb

Rb

VM6101

1M

I²C 7-bit addr = 0x10 +3.3V NC VM6101 VDD AMUX TEST GND

SCL

bs O

let o

ro P e

I²C 7-bit addr = 0x11 Optional

du

SDA PD

INT

(s) ct
1M

+3.3V

Ob -

so

te le

ro P
SCL SDA GPIO0 GPIO1 GPIO2 GPIO3

uc d

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Host Microcontroller

Note: Rb value depends on bus capacitive load

8/17

VM6101

Register description

4
Note:

Register description
RO = Read Only; RW = Read/Write. Reserved bits must be written with 0s and return 0 upon read; Reserved bytes must not be accessed otherwise unpredictable results my occur.

Table 3.
Addr. 0x00 0x00 0x01 0x02

Register description
Bits [3:0] [7:4] [7:0] [6:0] [1:0] Def. 1 0 0x04 0x04 0 Name REVISION MASK N_PIXEL CONTROL CHSEL Chip revision (RO). Mask code (RO). (RO) Control register (RW) Channel select for comparator and PWM logic: 0: Y 1: R 2: G 3: B INT pin function select: 0: PWM generator output 1: Comparator logic output Description

2

1

INT_FSEL

3

0

PWM_POL

PWM polarity: 0: Normal (Thin pulse for low values, Wide pulses for high values) 1: Inverted. Address Select: when written with `1', the INT pin goes high impedance; after a duration T (defined below), the INT pin is sampled and returns to low impedance. The device slave address is set accordingly: INT sampled low: address = 0x20 INT sampled high: address = 0x22.

4

0

ADDR_ SEL

[6:5]

0

ADDR_SELW

0x03

O

0x04

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let o
7 [7:0] [2:0] 0 1 2

ro P e
0 0 0x01 1 0 0

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(s) ct

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Address select sampling window duration: 0: T = 160 s (default) 1: T = 80 s 2: T = 40 s 3: T = 20 us This duration allows for INT pin pull-up rise time. Reserved Reserved (RO).

Y_STATUS

Y-channel status register (RO). Reading this register will cause Y_CNT to be transferred to serial interface buffer. 5 MSBs are read as zeros. This bit is set after reset. Cleared after first read of STATUS register. This bit is set upon counter overflow: current counter values are invalid. When set, indicates that a new count value is available in the 4 registers here below.

RESET OVERFLOW READY

9/17

Register description Table 3.
Addr. 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17

VM6101

Register description (continued)
Bits [2:0] [7:0] [7:0] [7:0] [7:0] [2:0] [7:0] [7:0] [7:0] [7:0] [2:0] [7:0] [7:0] [7:0] [7:0] [2:0] [7:0] [7:0] [7:0] [5:0] 0 1 Def. 0 0 0 0 0x01 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x03 1 1 0 0 0 0 Name Y_CNT3 Y_CNT2 Y_CNT1 Y_CNT0 R_STATUS R_CNT3 R_CNT2 R_CNT1 R_CNT0 G_STATUS G_CNT3 G_CNT2 G_CNT1 G_CNT0 B_STATUS B_CNT3 B_CNT2 B_CNT1 B_CNT0 TH_CFG EN_LO POL_LO EN_HI Description Y channel count bits [26:24] (RO). 5 MSBs are read as zeros. Y channel count bits [23:16] (RO) Y channel count bits [15:8] (RO) Y channel count bits [7:0] (RO) R channel status register (RO). Refer to Y Channel for description. R channel count bits [26:24] (RO). 5 MSBs are read as zeros. R channel count bits [23:16] (RO) R channel count bits [15:8] (RO) R channel count bits [7:0] (RO) G channel status register (RO). Refer to Y Channel for description. G channel count bits [26:24] (RO). 5 MSBs are read as zeros. G channel count bits [23:16] (RO) G channel count bits [15:8] (RO) G channel count bits [7:0] (RO)

B channel status register (RO). Refer to Y Channel for description. B channel count bits [26:24] (RO). 5 MSBs are read as zeros. B channel count bits [23:16] (RO) B channel count bits [15:8] (RO) B channel count bits [7:0] (RO) Comparator logic configuration (RW). 2 MSBs are reserved. Refer to Section 2.2: Comparator logic for programming details. Enable low threshold comparator (1 = enable, 0 = disable) Low threshold comparator output polarity

0x18

2 3 4

0x19 0x1a

O

0x1b 0x1c

bs
0x1f

let o
5 [2:0] [7:0] [7:0] [7:0] [2:0] [7:0] [7:0] [7:0]

Pr e
0x00 0x00 0x00 0x08 0x00 0x00 0x00 0

POL_HI

INT_POL HYST

du o

(s) ct

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Enable high threshold comparator (1 = enable, 0 = disable)

High threshold comparator output polarity INT pin output polarity Enable hysteresis function Low threshold bits [26:24] (RW). 5 MSBs are read as zeros. Low threshold bits [23:16] (RW) Low threshold bits [15:8] (RW) Low threshold bits [7:0] (RW) High threshold bits [26:24] (RW). 5 MSBs are read as zeros. High threshold bits [23:16] (RW) High threshold bits [15:8] (RW) High threshold bits [7:0] (RW)

TH_LO3 TH_LO2 TH_LO1

TH_LO0 TH_HI3 TH_HI2 TH_HI1 TH_HI0

0x1d 0x1e

0x20

10/17

VM6101 Table 3.
Addr. 0x21

Register description Register description (continued)
Bits [3:0] Def. 0x00 Name PWM_FREQ Description PWM output frequency (RW)(4 MSBs are reserved): n = 0 to 15 fPWM = fOSC * 2n-18, where fOSC = 3.6 MHz. PWM sensitivity (RW)(3 MSBs are reserved): n = 0 to 26 0 = high sensitivity, 26 = low sensitivity. Practical values lie between 9 and 18. Refer to Figure 4: PWM duty cycle versus illumination for typical behavior. Reserved.

0x22

[4:0]

0x00

PWM_SENS

0x22 ... 0x27 0x28 0x29 0x2A ... 0xFF

[7:0]

[7:0] [7:0] [7:0]

0x04 0x00

TEST_MOD TEST_SEL

Reserved (RW). Reserved (RW). Reserved.

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Optical characteristics

VM6101

5
Table 4.
Symbol E Ev

Optical characteristics
Optical characteristics (1)
Parameter Irradiance range Illuminance range Conditions Min 0.0001 0.03 Typ Max 800 170k Unit Wm-2 lx

1. Using typical operating conditions: TA = 25 C, VDD = 3.3 V

Figure 6.

Spectral response
1.0 Red

1.2 Normalized response 1.0 0.8 0.6 0.4 0.2 0.0

Normaliz ed Sensitivity

0.8 Blue

Angular response
Gr een

Y

0.6

0.4

0.2

-90

0.0 400 -60

500 600 700 800 -30 0 Wave le n g t h (nm ) 60 30 Incident light angle (degrees)

Figure 7.
1.2

Angular response

Normalized sensitivity

1.0 0.8 0.6

bs O

let o
0.4 0.2 0.0 -90

Pr e
-30

du o
0 30

-60

60

90

Incident light angle (degrees)

12/17

NNrmalazied d response oorm i l z e response Normalioemalized sensitivity N zr d sensitivity

ct

(s)

so Ob Figure 8.

te le

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900 90

1000

Relative output versus temperature

1.1.100 2

G 1.3 1.0 R 1.3 1.050 B 1.2 0.1.2 8 Y 1.1 0.1..1 00 6 10 1.0 1.0 0.4 0.9 0.9 0.950 0.8 0.2 0.8 0.7 0.0.7 0 -10 0.900 0 10 20 30 40 50 60 70 80 - 90 0 -0 0 10 30 0 30 4030 0 60 7090 0 6 -1 -10 0 -10 20 0 30 40 50 060 70 80 2 56 8 Temperature (C) Tempeperate re (C) Temratur u (C)

VM6101

Electrical characteristics

6
Table 5.
Symbol VDD VIN TSTG TL ESDHBM ESDMM ESDCDM

Electrical characteristics
Absolute maximum ratings (Note 1, Note 2)
Parameter Supply voltage DC input voltage, all I/O pins Storage temperature Solder reflow peak temperature, JEDEC J STD-020 Human body model ESD rating, all pins, JESD22-A114-B Machine model ESD rating, all pins, JESD22-A115-B Charged device model ESD rating, all pins, JESD22-C101-C Min -0.5 -0.5 -4 0 Max 3.7 VDD + 0.5 85 245 2 200 500 Unit V V C C kV V V

Table 6.
Symbol TA VDD VIL

Recommended operating conditions
Parameter Operating temperature Supply voltage Input low voltage (SCL, SDA) Input low voltage (PD) Min 0 3.0 Max

VIH

Input high voltage (SCL, SDA) Input high voltage (PD)

IOL IOH

Output low current Output high current

Table 7.
Symbol VOL VOH IIL IDDPD IDD

DC electrical characteristics (Note 3)
Parameter

Output low voltage (SDA, INT) Output high voltage (INT) Input leakage current

bs O
fOSC

Table 8.

let o

Supply current, power-down Supply current, active

ro P e

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(s) ct

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0 0 2 .0

od

uc
70 3.6 0.8 VDD 4 4

s) t(
V V V V V

Unit C

0.3 VDD

0.7 VDD

mA mA

Conditions

Min

Max 0.4

Unit V V

IOL = max, VDD = min 2 .4 -1

IOH = max, VDD = min All I/O pins PD low (Note 4) PD high (Note 4)

+1 1.0 1.1

A A mA

AC electrical characteristics (Note 3)
Parameter Conditions Min Typ 3.6 Max Unit MHz

Symbol

Internal oscillator frequency

13/17

Electrical characteristics Table 9.
Symbol fSCL tLOW tHIGH tSU;STA tHD;STA tSU;DAT tHD;DAT tSU;STO tBUF tR tF Cb SCL clock frequency SCL clock low period SCL clock high period (Repeated) START condition setup time (Repeated) START condition hold time Data setup time Data hold time STOP condition setup time Bus free condition between START and STOP conditions Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Capacitive load for each bus line

VM6101

Serial interface timing (Note 3)
Parameter Min 0 4.7 4 .0 4.7 4.0 250 300 4.0 4 .7 300 300 Max 100 Unit kHz s s s s ns ns ns s ns

Figure 9.

Serial interface timing waveforms

Stop
SDA

Star t

tBUF S CL

tLOW

tR

tHD;STA

Note:

1

O

bs

let o
2 3 4

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Unless otherwise specified, all voltages are referenced to ground. Over recommended operating conditions, unless otherwise specified. Using typical operating conditions: TA = 25 C, VDD = 3.3 V

od Pr e

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tHD;DAT

(s)

tHIGH

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Star t

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400

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ns

pF

Stop

tHD;STA

tSU;DAT

tSU;STA

tSU;STO

14/17

VM6101

Mechanical information

7

Mechanical information
Figure 10. 8-lead MLPD package outline
Symbol A A3 b D D2 E E2 e L 0.55 0.25 2.90 2.20 2.90 1.00 Min 0.65 Typ 0 .7 0.20 0.30 3.00 0.35 3.10 Max 0.75

2.350.652.45 0.7 3.00 1.15 3.10 1.25

2.20
0.65

1 0.60 .00 0.65 1.15

All dimensions in millimeters 0.55

Figure 11. Recommended PCB layout

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0.60

2.35

15/17

Ordering information

VM6101

8

Ordering information
Table 10. Ordering information
Order code VM6101V008 VM6101V008/TR STV-6101-R01 Description 8-lead MLPD 3 x 3 x 0.7 mm, RoHS compliant, tray packing. 8-lead MLPD 3 x 3 x 0.7 mm, RoHS compliant, 13" tape and reel, 5000 parts/reel. VM6101 evaluation board

9

Revision history
Table 11.
Date 05-Jun-2006 14-Dec-2006 27-Apr-2007

Document revision history
Revision 1 2 3 Initial release Global update Changes

Updated Chapter 6: Electrical characteristics Chapter 4: Register description

06-Jun-2008

4

Updated the datasheet status to `New for New Design'.

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VM6101

Please Read Carefully:

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