L6727
Single phase PWM controller
Feature
Flexible power supply from 5V to 12V Power conversion input as low as 1.5V 1% output voltage accuracy High-current integrated drivers Adjustable output voltage 0.8V internal reference Simple voltage mode control loop Sensorless and programmable OCP across Low-Side RdsON Oscillator internally fixed at 300kHz Internal Soft-Start LS-LESS to manage pre-bias start-up Disable function OV / UV protection FB disconnection protection SO-8 package SO-8
Description
L6727 is a single-phase step-down controller with integrated high-current drivers that provides complete control logic, protections and reference voltage to realize in an easy and simple way general DC-DC converters by using a compact SO-8 package. Device flexibility allows managing conversions with power input VIN as low as 1.5V and device supply voltage in the range of 5V to 12V. L6727 provides simple control loop with voltagemode error-amplifier. The integrated 0.8V reference allows regulating output voltages with 1% accuracy over line and temperature variations. Oscillator is internally fixed to 300kHz. L6727 provides programmable over current protection as well as over and under voltage protection. Current information is monitored across the Low-Side mosfet RdsON saving the use of expensive and space-consuming sense resistors while output voltage is monitored through FB pin. FB disconnection protection prevents excessive and dangerous output voltages in case of floating FB pin.
Applications
Subsystem power supply (MCH, IOCH, PCI...) Memory and termination supply CPU & DSP power supply Distributed power supply General DC / DC converters
Table 1.
Device summary
Part Number L6727 L6727TR Package SO-8 SO-8 Rev 3 Packaging Tube Tape & Reel 1/22
www.st.com 1
June 2007
Contents
L6727
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
1.1 1.2 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 5
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Soft Start and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.1 6.2 Low-Side-Less Start up (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Enable / Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 Over current threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8
Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 14
8.1 8.2 8.3 8.4 Under voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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L6727
Contents
9
Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9.1 9.2 9.3 9.4 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Embedding L6727-based VRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10 11
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
Typical application circuit and block diagram
L6727
1
1.1
Typical application circuit and block diagram
Application circuit
Figure 1. Typical application circuit
VIN = 1.5V to 19V (**)
D RD CBOOT 2 RgHS
VCC = 5V to 12V
CDEC
ROCSET
(*)
5 VCC
7
BOOT
COMP / DIS / OC
1
C HF HS L
C BULK
CF CP RF
L6727
UGATE
6
PHASE
8
Vout
FB LGATE
4
RgLS
LS
RSN
COUT
ROS
RFB
GND 3
CSN
LOAD
L6727 Reference Schematic (*) ROCSET not to be connected when VCC > 5V (**) Up to 12V with Vcc > 5V
1.2
Block diagram
Figure 2. Block diagram
VCC
CONTROL LOGIC & PROTECTIONS
CURRENT READ & OCP
Vout Monitor
BOOT
ADAPTIVE ANTI CROSS CONDUCTION
HS
IOCSET
UGATE PHASE
DISABLE PWM
VCC
300 kHz OSCILLATOR + 0.8V
LS
LGATE GND
L6727
COMP / DIS / OC
ERROR AMPLIFIER
4/22
FB
L6727
Pins description and connection diagrams
2
Pins description and connection diagrams
Figure 3. Pins connection (top view)
BOOT UGATE GND LGATE
1 2 3 4
8 7
L6727
6 5
PHASE COMP / DIS / OC FB VCC
2.1
Pin descriptions
Table 2.
Pin #
Pins descriptions
Name Function HS Driver Supply. Connect through a capacitor (100nF) to the floating node (LS-Drain) pin and provide necessary bootstrap diode from VCC. HS Driver Output. Connect to HS mosfet gate. All internal references, logic and drivers are connected to this pin. Connect to the PCB ground plane. LS Driver Output. Connect to LS mosfet gate. Device and LS Driver power supply. Operative range from 4.1V to 13.2V. Filter with at least 1F MLCC to GND. Error Amplifier Inverting Input. Connect with a resistor RFB to the output regulated voltage. Additional resistor ROS to GND may be used to regulate voltages higher than the reference.
1 2 3 4 5
BOOT UGATE GND LGATE VCC
6
FB
7
COMP. Error Amplifier Output. Connect with an RF - CF // CP to FB to compensate the control-loop. DIS. The device can be disabled by forcing this pin lower than 0.5V(typ). To disable the device, the external pull-down need to overcome 10mA of COMP / DIS COMP output current for about 15s. Once disabled, COMP output current / OC drops to 20A. OC. Over current threshold set. Connect with an ROCSET resistor to VCC (ONLY IF VCC is supplied by 5V bus) to program OC threshold. When VCC > 5V, ROCSET need to be not-connected. HS Driver return path, current-reading and adaptive-dead-time monitor. Connect to the LS drain to sense RdsON drop to measure the output current. This pin is also used by the adaptive-dead-time control circuitry to monitor when HS mosfet is OFF.
8
PHASE
5/22
Electrical specifications
L6727
2.2
Thermal data
Table 3.
Symbol RthJA TMAX TSTG TJ
Thermal data
Parameter Thermal Resistance Junction to Ambient(1) Maximum Junction Temperature Storage Temperature Range Junction Temperature Range Value 85 150 -40 to 150 -20 to 150 Unit C/W C C C
1. Measured with the component mounted on a 2S2P board in free air (6.7cm x 6.7cm, 35m (P) and 17.5m (S) copper thickness).
3
3.1
Electrical specifications
Absolute maximum ratings
Table 4.
Symbol VCC VBOOT to GND to PHASE to GND to PHASE to PHASE; t < 50ns to GND to GND to GND to GND; t < 50ns COMP to GND FB to GND
1. ESD immunity for FB pin is guaranteed up to 1000V (Human Body Model).
Absolute maximum ratings
Parameter (1) Value -0.3 to 15 15 45 -0.3 to (VBOOT - VPHASE) + 0.3 -1 VBOOT + 0.3 -8 to 30 -0.3 to VCC + 0.3 -1 -0.3 to 7 -0.3 to 3.6 Unit V V
VUGATE VPHASE VLGATE
V V V V V
6/22
L6727
Electrical specifications
3.2
Table 5.
Symbol
Electrical characteristics
Electrical characteristics (VCC = 12V; TA = -20C to +85C, unless otherwise specified).
Parameter Test conditions Min. Typ. Max. Unit
Recommended operating conditions VCC VIN Device supply voltage See Figure 1 13.2 Conversion input voltage VCC < 7.0V 19.0 V V 4.1 13.2 V
Supply current and power-ON ICC IBOOT UVLO Hysteresis Oscillator 0C to +70C FSW VOSC dMAX Reference Output voltage accuracy Error amplifier A0 GBWP SR IFB DIS DC gain(1) Gain-bandwidth product Slew-rate(1) Input bias current Disable threshold Sourced from FB COMP Falling 0.43
(1)
VCC supply current BOOT supply current VCC turn-ON
UGATE and LGATE = OPEN UGATE = OPEN; PHASE to GND VCC Rising
6 0.5 4.1 0.2
mA mA V V
270 250
300 300 1.5
330 350
kHz kHz V %
Main oscillator accuracy PWM ramp amplitude Maximum duty cycle 80
VOUT = 0.8V, TA = 0C to 70C VOUT = 0.8V
-1 -1.5
-
1 1.5
% %
120 15 8 100 0.5
dB MHz V/s nA V
7/22
Electrical specifications Table 5.
Symbol Gate drivers IUGATE RUGATE ILGATE RLGATE HS source current HS sink resistance LS source current LS sink resistance BOOT - PHASE = 5V to 12V BOOT - PHASE = 5V to 12V VCC = 5V to 12V VCC = 5V to 12V 1.5 1.1 1.5 0.65
L6727
Electrical characteristics (continued) (VCC = 12V; TA = -20C to +85C, unless otherwise specified).
Parameter Test conditions Min. Typ. Max. Unit
A A
Over-current protection IOCSET VCC_OC VOCTH OCSET current source OC Switch-over threshold Fixed OC threshold Sunk from COMP pin, before SS VCC Rising VPHASE to GND, VCC > VCC_OC 55 60 8 -400 65 A V mV
Over & under-voltage protections OVP UVP OVP threshold UVP threshold FB rising FB falling 1 0.6 V V
1. Guaranteed by design, not subject to test.
8/22
L6727
Device description
4
Device description
L6727 is a single-phase PWM controller with embedded high-current drivers that provides complete control logic and protections to realize in an easy and simple way a general DCDC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, with its high level of integration this 8-pin device allows reducing cost and size of the power supply solution. L6727 is designed to operate from a 5V or 12V supply bus. Thanks to the high precision 0.8V internal reference, the output voltage can be precisely regulated to as low as 0.8V with 1% accuracy over line and temperature variations (between 0C and +70C). The switching frequency is internally set to 300kHz. This device provides a simple control loop with a voltage-mode error-amplifier. The erroramplifier features a 15MHz gain-bandwidth product and 8V/s slew rate, allowing high regulator bandwidth for fast transient response. To avoid load damages, L6727 provides over current protection as well as over voltage, under voltage and feedback disconnection protection. When the device is supplied from 5V, over current trip threshold is programmable by a simple resistor. Output current is monitored across Low-Side MOSFET RdsON, saving the use of expensive and space-consuming sense resistor. Output voltage and feedback disconnection are monitored through FB pin. L6727 implements soft-start increasing the internal reference from 0V to 0.8V in 5.1ms (typ) in closed loop regulation. Low-Side-Less feature allows the device to perform soft-start over pre-biased output avoiding high current return through the output inductor and dangerous negative spike at the load side.
9/22
Driver section
L6727
5
Driver section
The integrated high-current drivers allow using different types of power MOSFET (also multiple MOSFETs to reduce the equivalent RdsON), maintaining fast switching transition. The driver for the high-side MOSFET uses BOOT pin for supply and PHASE pin for return. The driver for low-side MOSFET uses the VCC pin for supply and GND pin for return. The controller embodies an anti-shoot-through and adaptive dead-time control to minimize low side body diode conduction time, maintaining good efficiency while saving the use of Schottky diode:
to check high-side MOSFET turn off, PHASE pin is sensed. When the voltage at PHASE pin drops down, the low-side MOSFET gate drive is suddenly applied; to check low-side MOSFET turn off, LGATE pin is sensed. When the voltage at LGATE has fallen, the high-side MOSFET gate drive is suddenly applied.
If the current flowing in the inductor is negative, voltage on PHASE pin will never drop. To allow the low-side MOSFET to turn-on even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. Power conversion input is flexible: 5V, 12V bus or any bus that allows the conversion (See maximum duty cycle limitation and recommended operating conditions, in Table 5) can be chosen freely.
5.1
Power dissipation
L6727 embeds high current MOSFET drivers for both high side and low side MOSFETs: it is then important to consider the power that the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. Two main terms contribute in the device power dissipation: bias power and drivers' power.
Device Bias Power (PDC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same VCC of the device):
PDC = VCC ( ICC + IBOOT )
Drivers power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power PSW dissipated to switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs results:
PS W = FSW [ Qg H S ( VB O O T VP H A SE ) + Qg L S VC C ]
where VBOOT - VPHASE is the voltage across the bootstrap capacitor. External gate resistors helps the device to dissipate the switching power since the same power PSW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device.
10/22
L6727
Soft Start and Disable
6
Soft Start and Disable
L6727 implements a soft start to smoothly charge the output filter avoiding high in-rush currents to be required from the input power supply. The device progressively increases the internal reference from 0V to 0.8V in about 5.1ms, in closed loop regulation, gradually charging the output capacitors to the final regulation voltage. In the event of an over current triggering during soft start, the over current logic will override the soft start sequence and will shut down both the high side and low side gates for the internal soft start residual time (up to 2048 clock cycles) plus 2048 clock cycles, then it will begin a new soft start. The device begins soft start phase only when VCC power supply is above UVLO threshold and over current threshold setting phase has been completed.
6.1
Low-Side-Less Start up (LSLess)
In order to manage start up over pre-biased output, L6727 performs a special sequence in enabling LS driver to switch: during the soft-start phase, LS driver results disabled (LS = OFF) until HS starts to switch. This avoids the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output. If the output voltage is pre-biased to a voltage lower than the programmed one, neither HS nor LS will turn on until the soft start ramp exceeds the output pre-bias voltage; then VOUT will ramp up from there, without any drop or current return. If the output voltage is pre-biased to a voltage higher than the programmed one, HS would never start to switch. In this case, at the end of soft start time, LS is enabled and discharges the output to the final regulation value. This particular feature of the device masks the LS turn-on only from the control loop point of view: protections by-pass LSLESS, turning ON the LS mosfet in case of need. Figure 4. LSLess Startup (left) vs. Non-LSLess Startup (right)
11/22
Soft Start and Disable
L6727
6.2
Enable / Disable
The device can be disabled by externally pushing COMP / DIS pin under 0.5V (typ). In disable condition HS and LS MOSFETs are turned off, and a 20A current is sourced from COMP / DIS pin. Setting free the pin, this current pulls it over the threshold and the device enables again performing a new SS. To disable the device, the external pull-down needs to overcome 10mA of COMP output current for about 15s. Once disabled, COMP output current drops to 20A. Figure 5. Start Up sequence; VCC = 5V (Left). Over Current Hiccup (Right)
12/22
L6727
Over current protection
7
Over current protection
The over current feature protects the converter from a shorted output or overload, by sensing the output current information across the Low Side MOSFET drain-source onresistance, RdsON. This method reduces cost and enhances converter efficiency by avoiding the use of expensive and space-consuming sense resistors. The low side RdsON current sense is implemented by comparing the voltage at the PHASE node when LS MOSFET is turned on with the programmed OCP threshold voltage, internally held. If the monitored voltage drop (GND to PHASE) exceeds this threshold, an Over Current Event is detected. If two Over Current Events are detected in two consecutive switching cycles, the protection will be triggered and the device will turn off both LS and HS MOSFETs for 2048 clock cycles (plus internal SS remaining time, if triggered during a SS phase); then it will begin a new Soft Start. If the over current condition is not removed, the continuous fault will cause L6727 to go into a hiccup mode with a typical period of 13.6ms (Figure 5), guaranteeing safe load protection and very low power dissipation.
7.1
Over current threshold setting
When supplied with VCC = 5V, L6727 allows to easily program an Over Current Threshold ranging from 50mV to 500mV, simply by adding a resistor (ROCSET) between COMP and VCC. During a short period of time (5.5ms - 6.5ms) following the first enable (given VCC over UVLO threshold), an internal 60A current (IOCSET) is sunk from COMP pin, determining a voltage drop across ROCSET. This voltage drop, differentially sensed between VCC and COMP, divided by a factor 3, will be sampled and internally held by the device as Over Current Threshold until next VCC cycling. Differential sensing versus VCC allows OCSET procedure to be fully independent from VIN rail. The OC setting procedure overall time length ranges from 5.5ms to 6.5ms, proportionally to the threshold being set. Connecting an ROCSET resistor between COMP and VCC, the programmed threshold will be:
1 IOCSET ROCSET I O C t h = -- ------------------------------------------3 RdsON
ROCSET values range from 2.5k to 25k. If the voltage drop across ROCSET is too low, the system will be very sensitive to start-up inrush current and noise. This can result in a continuous OCP triggering and hiccup mode. In this case, consider to increase ROCSET value. In case ROCSET is not connected (and VCC = 5V), the device will set the maximum threshold. If the device is supplied with a VCC higher than 7V, ROCSET must be not connected. In this case, as soon as VCC rises over VCC_OC (8V typ.), L6727 switches OC threshold to 400mV (internally fixed value). See Figure 5 for OC threshold setting and soft start oscilloscope sample waveforms.
13/22
Output voltage monitor and protections
L6727
8
Output voltage monitor and protections
L6727 monitors the voltage at FB pin and compares it to internal reference voltage in order to provide Under Voltage and Over Voltage protections.
8.1
Under voltage protection
If the voltage at FB pin drops below UV threshold (0.6V typ), the device turns off both HS and LS MOSFETs, waits for 2048 clock cycles and then performs a new Soft Start. If under voltage condition is not removed, the device enters a hiccup mode with a typical period of 13.6ms. UVP is active from the end of soft start.
8.2
Over voltage protection
If the voltage at FB pin rises over OV threshold (1V typ), over voltage protection turns off HS MOSFET and turns on LS MOSFET overriding PWM logic as long as over voltage is detected. OVP is always active with top priority as soon as over current threshold setting phase has been completed.
8.3
Feedback disconnection protection
In order to provide load protection even if FB pin is not connected, a 100nA bias current is always sourced from this pin. If FB pin is not connected, this current will permanently pull up FB over OVP threshold: thus LS will be latched on preventing output voltage from rising out of control.
8.4
Under voltage lock out
In order to avoid anomalous behaviors of the device when the supply voltage is too low to support its internal rails, UVLO is provided: the device will start up when VCC reaches UVLO upper threshold and will shutdown when VCC drops below UVLO lower threshold. The 4.1V maximum UVLO upper threshold allows L6727 to be supplied from 5V and 12V busses in or-ing diode configuration.
14/22
L6727
Application details
9
9.1
Application details
Output voltage selection
L6727 is capable to precisely regulate an output voltage as low as 0.8V. In fact, the device comes with a fixed 0.8V internal reference that guarantees the output regulated voltage to be within 1% tolerance over line and temperature variations between 0C and +70C (excluding output resistor divider tolerance, when present). Output voltage higher than 0.8V can be easily achieved by adding a resistor ROS between FB pin and ground. Referring to Figure 1, the steady state DC output voltage will be:
R V O U T = V R E F 1 + -----F-B --- R O S
where VREF is 0.8V.
9.2
Compensation network
The control loop showed in Figure 6 is a voltage mode control loop. The error amplifier is a voltage mode type. The output voltage is regulated to the internal reference (when present, offset resistor between FB node and GND can be neglected in control loop calculation). Error Amplifier output is compared to oscillator saw-tooth waveform to provide PWM signal to the driver section. PWM signal is then transferred to the switching node with VIN amplitude. This waveform is filtered by the output filter. The converter transfer function is the small signal transfer function between the output of the EA and VOUT. This function has a double pole at frequency FLC depending on the L-COUT resonance and a zero at FESR depending on the output capacitor ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage VOSC. The compensation network closes the loop joining VOUT and EA output with transfer function ideally equal to -ZF/ZFB. Figure 6. PWM control loop
VIN OS C V OSC
_ + PWM CO MP ARATO R E RRO R AMP LIF IE R + _
L
R COUT ESR
V OUT
VREF R FB
CF CP
RF
CS ZF
RS Z FB
15/22
Application details
L6727
Compensation goal is to close the control loop assuring high DC regulation accuracy, good dynamic performances and stability. To achieve this, the overall loop needs high DC gain, high bandwidth and good phase margin. High DC gain is achieved giving an integrator shape to compensation network transfer function. Loop bandwidth (F0dB) can be fixed choosing the right RF/RFB ratio, however, for stability, it should not exceed FSW/2. To achieve a good phase margin, the control loop gain has to cross 0dB axis with -20dB/decade slope. As an example, Figure 7 shows an asymptotic bode plot of a type III compensation. Figure 7. Example of type III compensation.
Gain [dB] open loop EA gain FZ1 FZ 2 closed loop gain compensation gain open loop converter gain 0dB F0d B FLC FESR 20log (RF/RFB) 20log (VIN/VOSC ) Log (Freq) FP1 FP2
Open loop converter singularities: a) b)
1 F L C = --------------------------------2 L CO U T 1 F E S R = ------------------------------------------2 CO U T E S R
Compensation Network singularities frequencies: a) b) c)
1 F Z 1 = -----------------------------2 RF CF 1 F Z 2 = ---------------------------------------------------2 ( RF B + RS ) CS 1 F P 1 = ------------------------------------------------CF CP 2 R F -------------------- C F + C P 1 F P 2 = -----------------------------2 RS CS
d)
16/22
L6727
Application details To place the poles and zeroes of the compensation network, the following suggestions may be followed: a) Set the gain RF/RFB in order to obtain the desired closed loop regulator bandwidth according to the approximated formula (suggested values for RFB range from 2k to 5k):
F0 d B VO S C RF ---------- = ------------ -----------------FL C VI N RF B
b)
Place FZ1 below FLC (typically 0.5*FLC):
1 C F = ---------------------------- RF FL C
c)
Place FP1 at FESR:
CF C P = ---------------------------------------------------------2 RF CF FE S R 1
d)
Place FZ2 at FLC and FP2 at half of the switching frequency:
RB -R S = -------------F----------FS W ----------------- 1 2 FL C 1 C S = ----------------------------- RS FS W
e) f)
Check that compensation network gain is lower than open loop EA gain; Estimate phase margin obtained (it should be greater than 45) and repeat, modifying parameters, if necessary.
9.3
Layout guidelines
L6727 provides control functions and high current integrated drivers to implement highcurrent step-down DC-DC converters. In this kind of application, a good layout is very important. The first priority when placing components for these applications has to be reserved to the power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) power connections (highlighted in Figure 8) must be part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs, must be close one to the other. The use of multi-layer printed circuit board is recommended. The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS drain. Use proper VIAs number when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
17/22
Application details
L6727
same high-current trace on more than one PCB layer will reduce the parasitic resistance associated to that connection. Connect output bulk capacitors (COUT) as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace, also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitors bank. Figure 8. Power connections (heavy lines)
VIN
UGATE PHASE
CIN L
L6727
LGATE GND COUT LOAD
Gate traces and phase trace must be sized according to the driver RMS current delivered to the power MOSFET. The device robustness allows managing applications with the power section far from the controller without losing performances. Anyway, when possible, it is recommended to minimize the distance between controller and power section. See Figure 9 for drivers current paths. Small signal components and connections to critical nodes of the application, as well as bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC and Bootstrap capacitor) and loop compensation components as close to the device as practical. For over current programmability, place ROCSET close to the device and avoid leakage current paths on COMP / OC pin, since the internal current source is only 60A. Systems that do not use Schottky diode in parallel to the Low-Side MOSFET might show big negative spikes on the phase pin. This spike must be limited within the absolute maximum ratings (for example, adding a gate resistor in series to HS MOSFET gate, or a phase resistor in series to PHASE pin), as well as the positive spike, but has an additional consequence: it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the absolute maximum ratings also causing device failures. It is then suggested in this cases to limit this extra-charge by adding a small resistor in series to the bootstrap diode (RD in Figure 1). Figure 9.
LS DRIVER VCC CGD RGATE LGATE CGS CDS RINT UGATE RPHASE PHASE CGS CDS RGATE RINT
Drivers turn-on and turn-off paths
LS MOSFET HS DRIVER BOOT CGD HS MOSFET
GND
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L6727
Application details
9.4
Embedding L6727-based VRs
When embedding the VR into the application, additional care must be taken since the whole VR is a switching DC/DC regulator and the most common system in which it has to work is a digital system such as MB or similar. In fact, latest MBs have become faster and more powerful: high speed data busses are more and more common and switching-induced noise produced by the VR can affect data integrity if additional layout guidelines are not followed. Few easy points must be considered mainly when routing traces in which switching high currents flow (switching high currents cause voltage spikes across the stray inductance of the traces causing noise that can affect the near traces): When reproducing high current path on internal layers, keep all layers the same size in order to avoid "surrounding" effects that increase noise coupling. Keep safe guard distance between high current switching VR traces and data busses, especially if high-speed data busses, to minimize noise coupling. Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that must walk near the VR. Possible causes of noise can be located in the PHASE connections, MOSFETs gate drive and Input voltage path (from input bulk capacitors and HS drain). Also GND connection must be considered if not insisting on a power ground plane. These connections must be carefully kept far away from noise-sensitive data busses. Since the generated noise is mainly due to the switching activity of the VR, noise emissions depend on how fast the current switches. To reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope and thus to increase the switching times: this will cause, as a consequence of the higher switching time, an increase in switching losses that must be considered in the thermal design of the system.
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Package mechanical data
L6727
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com Table 6.
Dim. Min A A1 A2 B C
D (1)
SO-8 Mechanical data
mm. Typ Max 1.75 0.25 1.65 0.51 0.25 5.00 4.00 1.27 5.80 0.25 0.40 6.20 0.50 1.27 0.10 0.228 0.010 0.016 Mi n 0.053 0.004 0.043 0.013 0.007 0.189 0.15 0.050 0.244 0.020 0.050 0.004 inch Typ Ma x 0.069 0.010 0.065 0.020 0.010 0.197 0.157
1.35 0.10 1.10 0.33 0.19 4.80 3.80
E e H h L k ddd
0 (min.), 8 (max.)
1. D and F does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side.
Figure 10. Package dimensions
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L6727
Revision history
11
Revision history
Table 7.
Date 04-Dec-2006 28-Feb-2007 06-Jun-2007
Revision history
Revision 1 2 3 Initial release. Updated VOCTH values in Table 5 on page 7 Updated Figure 1: Typical application circuit on page 4, Table 3 and Table 4 on page 6 Changes
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L6727
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