STM32F101x8 STM32F101xB
Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces
Features
Core: ARM 32-bit CortexTM-M3 CPU 36 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access Single-cycle multiplication and hardware division Memories 64 to 128 Kbytes of Flash memory 10 to 16 Kbytes of SRAM Clock, reset and supply management 2.0 to 3.6 V application supply and I/Os POR, PDR and programmable voltage detector (PVD) 4-to-16 MHz crystal oscillator Internal 8 MHz factory-trimmed RC Internal 40 kHz RC PLL for CPU clock 32 kHz oscillator for RTC with calibration Low power Sleep, Stop and Standby modes VBAT supply for RTC and backup registers Debug mode Serial wire debug (SWD) and JTAG interfaces DMA 7-channel DMA controller Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs 1 × 12-bit, 1 s A/D converter (up to 16 channels) Conversion range: 0 to 3.6 V Temperature sensor Up to 80 fast I/O ports 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors, all 5 V-tolerant except for analog inputs
VFQFPN36 6 × 6 mm
LQFP48 7 x 7 mm
LQFP64 10 x 10 mm
LQFP100 14 x 14 mm
Six timers Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter 2 watchdog timers (Independent and Window) SysTick timer: 24-bit downcounter Up to 7 communication interfaces Up to 2 x I2C interfaces (SMBus/PMBus) Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) Up to 2 SPIs (18 Mbit/s) CRC calculation unit, 96-bit unique ID ECOPACK packages Device summary
Part number STM32F101C8, STM32F101R8 STM32F101V8, STM32F101T8 STM32F101RB, STM32F101VB, STM32F101CB
Table 1.
Reference STM32F101x8 STM32F101xB
September 2008
Rev 10
1/77
www.st.com 1
Contents
STM32F101x8, STM32F101xB
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 4 5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 29 Embedded reset and power control block characteristics . . . . . . . . . . . 29 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 48 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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STM32F101x8, STM32F101xB 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17
Contents
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1 6.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.2.1 6.2.2 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Evaluating the maximum junction temperature for an application . . . . . 70
7 8
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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List of tables
STM32F101x8, STM32F101xB
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Device features and peripheral counts (STM32F101xx medium-density access line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Medium-density STM32F101xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 30 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Maximum current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 34 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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STM32F101x8, STM32F101xB Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52.
List of tables
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 65 LQPF100 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 66 LQFP64 64-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 67 LQFP48 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 68 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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List of figures
STM32F101x8, STM32F101xB
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. STM32F101xx medium-density access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STM32F101xx medium-density access line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . 17 STM32F101xx medium-density access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . 18 STM32F101xx medium-density access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . 18 STM32F101xx medium-density access line VFQPFN36 pinout . . . . . . . . . . . . . . . . . . . . . 19 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 33 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 33 Current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V . . . 36 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 62 Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . . 63 VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Recommended footprint (dimensions in mm)(1)(2)(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 LQFP64 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 LQFP48 48-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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STM32F101x8, STM32F101xB
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of the STM32F101x8 and STM32F101xB medium-density access line microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family, please refer to Section 2.2: Full compatibility throughout the family. The medium-density STM32F101xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
2
Description
The STM32F101xB and STM32F101x8 medium-density access line family incorporates the high-performance ARM CortexTM-M3 32-bit RISC core operating at a 36 MHz frequency, high-speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 16 Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces (two I2Cs, two SPIs, and up to three USARTs), one 12-bit ADC and three general-purpose 16-bit timers. The STM32F101xx medium-density access line family operates in the 40 to +85 C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F101xx medium-density access line family includes devices in four different packages ranging from 36 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F101xx medium-density access line microcontroller family suitable for a wide range of applications:
Application control and user interface Medical and handheld equipment PC peripherals, gaming and GPS platforms Industrial applications: PLC, inverters, printers, and scanners Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
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Description
STM32F101x8, STM32F101xB
2.1
Device overview
Table 2. Device features and peripheral counts (STM32F101xx medium-density access line) Peripheral
Flash - Kbytes SRAM - Kbytes Communication Timers General -purpose SPI I
2C
STM32F101Tx STM32F101Cx 64 10 3 1 1 2 1 10 channels 26 64 10 3 2 2 3 128 16 3 2 2 3
STM32F101Rx 64 10 3 2 2 3 1 16 channels 51 128 16
STM32F101Vx 64 10 3 2 2 3 1 16 channels 80 128 16
USART
12-bit synchronized ADC number of channels GPIOs CPU frequency Operating voltage Operating temperatures Packages
1 10 channels 37
36 MHz 2.0 to 3.6 V Ambient temperature: 40 to +85 C (see Table 8) Junction temperature: 40 to +105 C (see Table 8) VFQFPN36 LQFP48 LQFP64 LQFP100
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STM32F101x8, STM32F101xB
Description
2.2
Full compatibility throughout the family
The STM32F101xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are referred to as low-density devices, the STM32F101x8 and STM32F101xB are referred to as medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are referred to as high-density devices. Low- and high-density devices are an extension of the STM32F101x8/B devices, they are specified in the STM32F101x4/6 and STM32F101xC/D/E datasheets, respectively. Lowdensity devices feature lower Flash memory and RAM capacities and a timer less. Highdensity devices have higher Flash memory and RAM capacities, and additional peripherals like FSMC and DAC, while remaining fully compatible with the other members of the STM32F101xx family. The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD and STM32F101xE are a drop-in replacement for the STM32F101x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F101xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices. Table 3. STM32F101xx family
Memory size Low-density devices Pinout 16 KB Flash 32 KB Flash(1) Medium-density devices 64 KB Flash 128 KB Flash High-density devices 256 KB Flash 32 KB RAM 384 KB Flash 48 KB RAM 512 KB Flash 48 KB RAM
4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM 144 100 64 48 36 2 × USARTs 2 × 16-bit timers 1 × SPI, 1 × I2C 1 × ADC 3 × USARTs 3 × 16-bit timers 2 × SPIs, 2 × I2Cs, 1 × ADC
5 × USARTs 4 × 16-bit timers, 2 × basic timers 3 × SPIs, 2 × I2Cs, 1 × ADC, 1 × DAC FSMC (100 and 144 pins)
1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices.
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Description
STM32F101x8, STM32F101xB
2.3
Overview
ARM CortexTM-M3 core with embedded Flash and SRAM
The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F101xx medium-density access line family having an embedded ARM core, is therefore compatible with all ARM tools and software.
Embedded Flash memory
64 or 128 Kbytes of embedded Flash is available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
Embedded SRAM
Up to 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
Nested vectored interrupt controller (NVIC)
The STM32F101xx medium-density access line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels.
Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Suppor t for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt latency.
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STM32F101x8, STM32F101xB
Description
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 36 MHz. See Figure 2 for details on the clock tree.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from User Flash Boot from System Memory Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606.
Power supply schemes
VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 10: Power supply scheme.
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher
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Description
STM32F101x8, STM32F101xB than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 10: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD.
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
MR is used in the nominal regulation mode (Run) LPR is used in the Stop mode Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output.
Low-power modes
The STM32F101xx medium-density access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm.
Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer.
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STM32F101x8, STM32F101xB
Description
Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers TIMx and ADC.
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It features:
A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source
General-purpose timers (TIMx)
There are three synchronizable general-purpose timers embedded in the STM32F101xx medium-density access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture, output compare, PWM or one pulse mode output. This gives up to 12 input captures / output compares / PWMs on the largest packages.
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Description
STM32F101x8, STM32F101xB The general-purpose timers can work together via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus.
Universal synchronous/asynchronous receiver transmitter (USART)
The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller.
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.
ADC (analog to digital converter)
The 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
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STM32F101x8, STM32F101xB
Description
Temperature sensor
The temperature sensor has to generate a linear voltage with any variation in temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Figure 1. STM32F101xx medium-density access line block diagram
TRACECLK TRACED[0:3] as AS
TPIU SW/JTAG TrWD /trig S ace
Co rtex M3 CPU
Fmax : 36 MHz NVIC NVIC Db us
Ibus
Flash obl Inte rfac e
JN TRST JT DI JT CK/ SWCL K J TMS/SWDIO JT DO as AF
p bus
Tr ac e Cont rol l er
POWER VOLT. REG. 3.3V TO 1.8V @VDD
VDD = 2 to 3.6V
VSS
Flash 128 KB 64 bit
BusM atrix
Sy st em
SRAM 16 KB
PCLK1 PCLK 2 HCL K FCL K RC 8 MHz RC 42 kHz @VDDA @VBAT PLL & CLO CK MANAGT
@VDD XTAL OSC 4-16 MHz OSC_IN OSC_OUT
GP DMA
7 channels
AH B: Fma x =36 MHz
IWDG Stand b y in t er f ac e
@VDDA SUPPL Y SUPERVISION POR / PDR PVD Rs t Int
VBAT OSC32_IN OSC32_OUT TAMPER-RTC
NRST VDDA VSSA
XTAL 32 kHz AH B2 AP B2 AH B2 APB 1 RTC AW U Back up re g
80AF PA[ 15: 0] PB[ 15: 0] PC[ 15: 0] PD[ 15: 0] PE[1 5:0 ]
EXTI WA KE UP GPIOA
Ba cku p i n t erf ac e TIM2 TIM3 4 Chann el s 4 Chann el s 4 Channels RX,TX, CTS, RTS, CK, SmartCard as AF RX,TX, CTS, RTS, CK, SmartCard as AF MOSI,MISO,SCK ,NSS as AF SCL ,SDA ,SMBA L as AF SCL ,SDA as AF
GPIOB
APB 1 : Fma x =24 / 36 MHz
TIM4 USAR T2 USAR T3 S 2x(8x16bit) PI2 I2C1 I2C2
GPIOC GPIOD GPIOE
MOSI,MISO, SCK ,NSS as AF RX,TX, CTS, RTS, Smart Card as AF 16AF VREF+ VREF-
SPI1 USA RT1 @VDDA 12b i t A DC1 IF
AP B2 : Fma x = 36 MHz
WWDG
Tem p sen so r
ai14385B
1. AF = alternate function on I/O port pin. 2. TA = 40 C to +85 C (junction temperature up to 105 C).
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Description Figure 2. Clock tree
8 MHz HSI RC
HSI
STM32F101x8, STM32F101xB
/2
36 MHz max Clock Enable (3 bits)
HCLK to AHB bus, core, memory and DMA to Cortex System timer FCLK Cortex free running clock PCLK1 to APB1 peripherals Peripheral Clock
Enable (13 bits)
PLLSRC
PLLMUL ..., x16 x2, x3, x4 PLL
HSI PLLCLK HSE
SW
SYSCLK
/8
36 MHz /1, 2..512 max
AHB Prescaler
APB1 Prescaler /1, 2, 4, 8, 16
36 MHz max
CSS
to TIM2, 3 TIM2,3, 4 and 4 If (APB1 prescaler =1) x1 TIMXCLK else x2 Peripheral Clock
En able (3 bits)
PLLXTPRE OSC_OUT OSC_IN 4-16 MHz HSE OSC /2
APB2 Prescaler /1, 2, 4, 8, 16
36 MHz max Peripheral Clock Enable (11 bits)
PCLK2 to APB2 peripherals
/128 OSC32_IN OSC32_OUT LSE OSC 32.768 kHz
LSE to RTC
ADC Prescaler /2, 4, 6, 8 RTCCLK
to ADC
ADCCLK
RTCSEL[1:0] LSI RC 40 kHz
LSI to Independent Watchdog (IWDG)
IWDGCLK
Legend:
Main Clock Output
/2
PLLCLK HSI HSE SYSCLK
MCO
HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal
MCO
ai15104
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 36 MHz. 2. To have an ADC conversion time of 1 s, APB2 must be at 14 MHz or 28 MHz.
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STM32F101x8, STM32F101xB
Pin descriptions
3
Pin descriptions
Figure 3. STM32F101xx medium-density access line LQFP100 pinout
VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LQFP100
VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1
ai14386b
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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Pin descriptions Figure 4.
STM32F101x8, STM32F101xB STM32F101xx medium-density access line LQFP64 pinout
VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14
VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1
ai14387b
Figure 5.
STM32F101xx medium-density access line LQFP48 pinout
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2
48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12
PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1
ai14378d
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STM32F101x8, STM32F101xB Figure 6.
Pin descriptions
STM32F101xx medium-density access line VFQPFN36 pinout
BOOT0
VSS_3
PA15
36 VDD_3 OSC_IN/PD0 OSC_OUT/PD1 NRST VSSA VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10
35
34
33
32
31
30
29
28 27 26 25 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 VDD_1
QFN36
11
12
13
14
15
16
17
19 18
PB0
PB1
PB2
PA3
PA4
PA5
PA6
PA7
VSS_1
PA14
PB7
PB6
PB5
PB4
PB3
23 22 21 20
ai14654
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Pin descriptions Table 4.
Pins VFQFPN36 LQFP100 LQFP48 LQFP64 Pin name Type(1)
STM32F101x8, STM32F101xB
Medium-density STM32F101xx pin definitions
I / O level(2) Alternate functions(3) Main function(3) (after reset)
Default
Remap
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
2 3 4 5 6 7
PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPERRTC(4) PC14-OSC32_IN(4) PC15OSC32_OUT(4) VSS_5 VDD_5 O SC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP
I/O I/O I/O I/O I/O S I/O I/O I/O S S I O I/O I/O I/O I/O I/O S S S S I/O
FT FT FT FT FT
PE2 PE3 PE4 PE5 PE6 VBAT PC13(5) PC14(5) PC15(5) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0
TRACECLK TRACED0 TRACED1 TRACED2 TRACED3
TAMPER-RTC OSC32_IN OSC32_OUT
ADC_IN10 ADC_IN11 ADC_IN12 ADC_IN13
WKUP/USART2_CTS(7)/ ADC_IN0/ TIM2_CH1_ETR(7) USART2_RTS(7)/ ADC_IN1/TIM2_CH2(7) USART2_TX(7)/ ADC_IN2/TIM2_CH3(7) USART2_RX(7)/ ADC_IN3/TIM2_CH4(7)
11 12 13 -
15 16 17 18
24 25 26 27
8 9 10 -
PA1 PA2 PA3 VSS_4
I/O I/O I/O S
PA1 PA2 PA3 VSS_4
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STM32F101x8, STM32F101xB Table 4.
Pins VFQFPN36 LQFP100 LQFP48 LQFP64 Pin name Type(1)
Pin descriptions
Medium-density STM32F101xx pin definitions (continued)
I / O level(2) Alternate functions(3) Main function(3) (after reset)
Default
Remap
14 15 16 17 18 19 20 21 22 23 24 25
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
11 12 13 14
VDD_4 PA4 PA5 PA6 PA7 PC4 PC5
S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S I/O FT FT FT FT FT FT FT FT FT FT FT FT FT
VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2/BOOT1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PB12 SPI2_NSS / I2C2_SMBAl/ USART3_CK (7) SPI2_SCK/ USART3_CTS(7) SPI2_MISO/ USART3_RTS(7) I2C2_SCL/ USART3_TX (7) I2C2_SDA/ USART3_RX (7) TIM2_CH3 TIM2_CH4 SPI1_NSS(7)/ADC_IN4 USART2_CK(7)/ SPI1_SCK(7)/ADC_IN5 SPI1_MISO(7)/ADC_IN6 TIM3_CH1(7) SPI1_MOSI(7)/ADC_IN7 TIM3_CH2(7) ADC_IN14 ADC_IN15 ADC_IN8/TIM3_CH3(7) ADC_IN9/TIM3_CH4(7)
15 16 17 18 19 -
PB0 PB1 PB2/BOOT1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PB12
26 27
34 35
52 53
-
PB13 PB14
I/O I/O
FT FT
PB13 PB14
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Pin descriptions Table 4.
Pins VFQFPN36 LQFP100 LQFP48 LQFP64 Pin name Type(1)
STM32F101x8, STM32F101xB
Medium-density STM32F101xx pin definitions (continued)
I / O level(2) Alternate functions(3) Main function(3) (after reset)
Default
Remap
28 -
36 37 38 39
54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
20 21 22 23 24
PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT
PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 JTMS-SWDIO
SPI2_MOSI USART3_TX USART3_RX USART3_CK USART3_CTS TIM4_CH1 / USART3_RTS TIM4_CH2 TIM4_CH3 TIM4_CH4 TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 USART1_CK/MCO USART1_TX(7) USART1_RX(7) USART1_CTS USART1_RTS PA13
29 30 31 32 33 34 35 36 37 38 5 6
40 41 42 43 44 45 46 47 48 49 50 51 52 53 5 6 54
25 PA13/JTMS/SWDIO 26 27 VSS_2 VDD_2
Not connected S S I/O I/O I/O I/O I/O I/O I/O I/O I/O FT FT FT FT FT FT FT FT FT VSS_2 VDD_2 JTCK/SWCLK JTDI PC10 PC11 PC12 OSC_IN
(6)
28 PA14/JTCK/SWCLK 29 PA15/JTDI PC10 PC11 PC12 2 3 PD0 PD1 PD2 PD3
PA14 PA15 TIM2_CH1_ETR/ SPI1_NSS USART3_TX USART3_RX USART3_CK
OSC_OUT(6) PD2 PD3 TIM3_ETR USART2_CTS
-
-
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STM32F101x8, STM32F101xB Table 4.
Pins VFQFPN36 LQFP100 LQFP48 LQFP64 Pin name Type(1)
Pin descriptions
Medium-density STM32F101xx pin definitions (continued)
I / O level(2) Alternate functions(3) Main function(3) (after reset)
Default
Remap
39 40 41 42 43 44 45 46 47 48
55 56 57 58 59 60 61 62 63 64
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
30 31 32 33 34 35 36 1
PD4 PD5 PD6 PD7 PB3/JTDO PB4/JNTRST PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3
I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O S S
FT FT FT FT FT FT
PD4 PD5 PD6 PD7 JTDO JNTRST PB5 PB3/TRACESWO PB4 I2C1_SMBAl I2C1_SCL(7)/ TIM4_CH1 (7) I2C1_SDA(7)/ TIM4_CH2 (7)
USART2_RTS USART2_TX USART2_RX USART2_CK TIM2_CH2 / SPI1_SCK TIM3_CH1 / SPI1_MISO TIM3_CH2 / SPI1_MOSI USART1_TX USART1_RX
FT FT
PB6 PB7 BOOT0
FT FT FT FT
PB8 PB9 PE0 PE1 VSS_3 VDD_3
TIM4_CH3 (7) TIM4_CH4
(7)
I2C1_SCL I2C1_SDA
TIM4_ETR
1. I = input, O = output, S = supply, HiZ= high impedance. 2. FT= 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 8. 4. PC13, PC14 and PC15 are supplied through the power switch and since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 is restricted: only one I/O at a time can be used as an output, the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). 5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 6. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode. 7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
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Memory mapping
STM32F101x8, STM32F101xB
4
Memory mapping
The memory map is shown in Figure 7. Figure 7. Memory map
0xFFFF FFFF 0xE010 0000 0x6000 0000 0x4002 3400 0xFFFF FFFF 0x4002 3000 0x4002 2400 0x4002 2000
APB memory space
reserved reserved reserved CRC reserved Flash interface reserved RCC reserved DMA reserved
4K 1K 3K 1K 3K 1K 3K 1K 1K 1K 1K 1K 1K 1K 1K 2K 1K 1K 1K 1K 1K 1K 1K 35K 1K 1K 1K 1K 1K 1K 1K 1K 2K 1K 1K 2K 1K 1K 1K 1K 1K 7K 1K 1K 1K
7
0xE010 0000 0xE000 0000 Cortex-M3 internal peripherals
0x4002 1400 0x4002 1000 0x4002 0400 0x4002 0000
6
0xC000 0000
0x4001 3C00 0x4001 3800 0x4001 3400 0x4001 3000 USART1 reserved SPI1 reserved reserved ADC1 reserved 0x4001 1C00
5
0xA000 0000
0x4001 2C00 0x4001 2800 0x4001 2400
4
0x8000 0000
0x1FFF FFFF 0x1FFF F80F
0x4001 1800
reserved
Port E Port D Port C Port B Port A EXTI AFIO reserved
0x4001 1400 0x4001 1000 0x4001 0C00 0x4001 0800
Option Bytes 0x1FFF F800
3
0x1FFF F000 0x6000 0000
System memory
0x4001 0400 0x4001 0000
0x4000 7400
2
0x4000 0000 Peripherals reserved
0x4000 7000 0x4000 6C00 0x4000 6800 0x4000 6400 0x4000 6000
PWR BKP reserved reserved reserved reserved I2C2 I2C1 reserved
1
0x2000 0000 SRAM 0x0801 FFFF
0x4000 5C00 0x4000 5800 0x4000 5400
0x4000 4C00
0
0x0800 0000 0x0000 0000
Flash memory
0x4000 4800 0x4000 4400
USART3 USART2 reserved
Aliased to Flash, system memory or SRAM depending on 0x0000 0000 BOOT pins
Res erved
0x4000 3C00 0x4000 3800 0x4000 3400 0x4000 3000 0x4000 2C00 0x4000 2800
SPI2 reserved IWDG WWDG RTC reserved
0x4000 0C00 0x4000 0800 0x4000 0400 0x4000 0000 TIM4 TIM3 TIM2
ai14379c
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STM32F101x8, STM32F101xB
Electrical characteristics
5
5.1
Electrical characteristics
Test conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
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Electrical characteristics
STM32F101x8, STM32F101xB
Figure 8.
Pin loading conditions
Figure 9.
Pin input voltage
STM32F10xxx pin C = 50 pF
VIN
STM32F10xxx pin
ai14123b
ai14124b
5.1.6
Power supply scheme
Figure 10. Power supply scheme
VBAT
1. 8-3. 6V
Po wer swi tch
Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers)
O UT
Level shifter
GP I/Os
IN
IO Logic Kernel logic (CPU, Digital & Memories)
VDD
VDD 1/2/3/4/5 VSS
Regulator
5 × 100 nF + 1 × 4.7 F
VDD VREF
1/2/3/4/5
VDDA VREF+ VREFVSSA
ai14125d
10 nF + 1 F
10 nF + 1 F
ADC
An alo g: RCs, PLL, ...
Caution:
In Figure 10, the 4.7 F capacitor must be connected to VDD3.
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STM32F101x8, STM32F101xB
Electrical characteristics
5.1.7
Current consumption measurement
Figure 11. Current consumption measurement scheme
IDD_VBAT VBAT
IDD VDD
VDDA
ai14126
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics, Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 5.
Symbol VDD -VSS VIN |VDDx| |VSSX - VSS|
Voltage characteristics
Ratings External main supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different VDD power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min 0.3 VSS -0.3 VSS - 0.3 Max 4.0 +5.5 VDD+0.3 50 mV 50 see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) V Unit
VESD(HBM)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded (see Table 6: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is induced by VIN
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Electrical characteristics Table 6.
Symbol IVDD IVSS IIO
STM32F101x8, STM32F101xB
Current characteristics
Ratings Total current into VDD/VDDA power lines (source)(1) Total current out of VSS ground lines (sink)
(1)
Max. 150 150 25 -25 5 5 5 pins)(4) 25
Unit
Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRST pin IINJ(PIN) (2)(3) Injected current on High-speed external OSC_IN and Lowspeed external OSC_IN pins Injected current on any other pin(4) IINJ(PIN)
(2)
mA
Total injected current (sum of all I/O and control
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN
Table 7.
Thermal characteristics
Ratings Storage temperature range Maximum junction temperature Value 65 to +150 150 Unit C C
Symbol TSTG TJ
5.3
5.3.1
Operating conditions
General operating conditions
Table 8.
Symbol fHCLK fPCLK1 fPCLK2 VDD
General operating conditions
Parameter Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency Standard operating voltage Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Backup operating voltage Conditions Min 0 0 0 2 2 Must be the same potential as VDD(2) 2.4 1.8 Max 36 36 36 3.6 3.6 V 3.6 3.6 V V MHz Unit
VDDA(1)
VBAT
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STM32F101x8, STM32F101xB Table 8.
Symbol
Electrical characteristics
General operating conditions (continued)
Parameter Conditions LQFP100 Min Max 434 444 mW LQFP48 VFQFPN36 Maximum power dissipation 40 40 40 363 1110 85 105 105 C C C Unit
PD
Power dissipation at TA = 85 C(3)
LQFP64
TA TJ
Ambient temperature Junction temperature range
Low power dissipation(4)
1. When the ADC is used, refer to Table 41: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 69). 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.2: Thermal characteristics on page 69).
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for TA. Table 9.
Symbol tVDD
Operating conditions at power-up / power-down
Parameter VDD rise time rate VDD fall time rate Conditions Mi n 0 20 Max Unit s/V
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 10 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8.
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Electrical characteristics Table 10.
Symbol
.
STM32F101x8, STM32F101xB
Embedded reset and power control block characteristics
Parameter Conditions PLS[2:0]=000 (rising edge) PLS[2:0]=000 (falling edge) PLS[2:0]=001 (rising edge) PLS[2:0]=001 (falling edge) PLS[2:0]=010 (rising edge) PLS[2:0]=010 (falling edge) PLS[2:0]=011 (rising edge) Mi n 2.1 2 2.19 2.09 2.28 2.18 2.38 2.28 2.47 2.37 2.57 2.47 2.66 2.56 2.76 2.66 Typ 2.18 2.08 2.28 2.18 2.38 2.28 2.48 2.38 2.58 2.48 2.68 2.58 2.78 2.68 2.88 2.78 100 Falling edge Rising edge 1.8(1) 1.84 1.88 1.92 40 1.5 2.5 4.5 1.96 2.0 Max 2.26 2.16 2.37 2.27 2.48 2.38 2.58 2.48 2.69 2.59 2.79 2.69 2.9 2.8 3 2.9 Unit V V V V V V V V V V V V V V V V mV V V mV ms
VPVD
Programmable voltage detector level selection
PLS[2:0]=011 (falling edge) PLS[2:0]=100 (rising edge) PLS[2:0]=100 (falling edge) PLS[2:0]=101 (rising edge) PLS[2:0]=101 (falling edge) PLS[2:0]=110 (rising edge) PLS[2:0]=110 (falling edge) PLS[2:0]=111 (rising edge) PLS[2:0]=111 (falling edge)
VPVDhyst
(2)
PVD hysteresis Power on/power down reset threshold PDR hysteresis
VPOR/PDR VPDRhyst
(2)
tRSTTEMPO(2) Reset temporization
2. Guaranteed by design, not tested in production.
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
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STM32F101x8, STM32F101xB
Electrical characteristics
5.3.4
Embedded reference voltage
The parameters given in Table 11 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 11.
Symbol VREFINT TS_vrefint(1)
Embedded internal reference voltage
Parameter Internal reference voltage ADC sampling time when reading the internal reference voltage Conditions 40 C < TA < +85 C Min 1.16 Typ 1.20 5.1 Max 1.24 17.1(2) Unit V s
1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 11: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 36 MHz) Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 12 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8.
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Electrical characteristics Table 12.
STM32F101x8, STM32F101xB
Maximum current consumption in Run mode, code with data processing running from Flash
Max(1) Parameter Conditions fHCLK TA = 85 C 36 MHz External clock (2), all peripherals enabled 24 MHz 16 MHz 8 MHz 36 MHz External clock (3), all peripherals Disabled 24 MHz 16 MHz 8 MHz 28.6 19.9 14.7 8.6 mA 19.8 13.9 10.7 6.8 Unit
Symbol
IDD
Supply current in Run mode
1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 13.
Maximum current consumption in Run mode, code with data processing running from RAM
Max(1) Parameter Conditions fHCLK TA = 85 C 36 MHz External clock (2), all peripherals enabled 24 MHz 16 MHz 8 MHz 36 MHz External clock(2) all peripherals disabled 24 MHz 16 MHz 8 MHz 24 17.5 12.5 7.5 16 11.5 8.5 5.5 mA Unit
Symbol
IDD
Supply current in Run mode
1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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STM32F101x8, STM32F101xB
Electrical characteristics
Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled
25
20 Cons umption (mA)
15
10
36MHz 16MHz 8MHz
5
0 - 40 0 25 Temper atur e (C) 70 85
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled
16 14 12 Cons umption (mA) 10 8 6 4 2 0 - 40 0 25 T emperature (C) 70 85 36MHz 16MHz 8MHz
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Electrical characteristics Table 14.
STM32F101x8, STM32F101xB
Maximum current consumption in Sleep mode, code running from Flash or RAM
Max(1) Parameter Conditions fHCLK TA = 85 C 36 MHz External clock(2) all peripherals enabled 24 MHz 16 MHz 8 MHz 36 MHz External clock(2), all peripherals disabled 24 MHz 16 MHz 8 MHz 15.5 11.5 8.5 5.5 mA 5 4.5 4 3 Unit
Symbol
IDD
Supply current in Sleep mode
1. Data based on characterization results, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 15.
Symbol
Typical and maximum current consumptions in Stop and Standby modes
Typ(1) Parameter Conditions VDD/ VBAT = 2.4 V VDD/VBAT = 3.3 V Max TA = 85 C(2) Unit
Supply current in Stop mode
Regulator in Run mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Regulator in Low-Power mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON
23.5
24
200
13.5
14
180
IDD
2.6 2.4
3.4 3.2
-
A
Supply current in Standby mode
Low-speed internal RC oscillator ON, independent watchdog OFF Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF
1.7
2
4
IDD_VBAT
Backup domain supply current
Low-speed oscillator and RTC ON
1.1
1.4
1.9
1. Typical values are measured at TA = 25 C. 2. Based on characterization, not rested in production.
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STM32F101x8, STM32F101xB
Electrical characteristics
Figure 14. Current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3.3 V and 3.6 V
140 120 Cons umpt ion (A) 100 80 60 40 20 0 -45 25 70 90 Temperat ure (C) 3. 3 V 3. 6 V
Figure 15. Current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V
100 90 80 Cons umption (A) 70 60 50 40 30 20 10 0 45 C 25 C Temperat ure (C) 85 C 3.3 V 3.6 V
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Electrical characteristics
STM32F101x8, STM32F101xB
Figure 16. Current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V
3 2. 5 Cons umpt ion (A) 2 1. 5 1 0. 5 0 -45 25 70 90 Temperat ure (C) 3. 3 V 3. 6 V
Typical current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 36 MHz) Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4
The parameters given in Table 16 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8.
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STM32F101x8, STM32F101xB Table 16.
Electrical characteristics
Typical current consumption in Run mode, code with data processing running from Flash
Typ(1) Typ(1) All peripherals disabled 14.8 10.1 7.4 4.6 2.8 1.9 1.45 1.25 1.06 mA 36 MHz 24 MHz Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz 18.3 12.2 8.5 4.9 2.7 1.6 1.02 0.73 0.5 14.1 9.5 6.8 4 2.2 1.4 0.9 0.67 0.48 Unit Parameter Conditions fHCLK
Symbol
All peripherals enabled(2) 19 12.9 9.3 5.5 3.3 2.2 1.6 1.3 1.08
36 MHz 24 MHz 16 MHz 8 MHz External clock(3) 4 MHz 2 MHz 1 MHz 500 kHz IDD Supply current in Run mode 125 kHz
1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics Table 17.
STM32F101x8, STM32F101xB
Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM
Typ(1) Typ(1) Unit Parameter Conditions fHCLK
Symbol
All peripherals All peripherals enabled(2) disabled 7.6 5.3 3.8 2.1 1.6 1.3 1.11 1.04 0.98 7 4.8 3.2 1.6 1 0.72 0.56 0.49 0.43 3.1 2.3 1.8 1.2 1.1 1 0.98 0.96 0.95
36 MHz 24 MHz 16 MHz 8 MHz External clock
(3)
4 MHz 2 MHz 1 MHz 500 kHz
IDD
Supply current in Sleep mode
125 kHz 36 MHz 24 MHz Running on High Speed Internal RC (HSI), AHB prescaler used to reduce the frequency 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz
mA 2.5 1.8 1.2 0.6 0.5 0.47 0.44 0.42 0.41
1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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STM32F101x8, STM32F101xB
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed under the following conditions:
all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption with all peripherals clocked off with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in Table 5. Peripheral current consumption
Peripheral TIM2 TIM3 TIM4 SPI2 Typical consumption at 25 C(1) 0.6 0.6 0.6 0.08 0.21 0.21 0.18 0.18 mA GPIO A GPIO B GPIO C GPIO D 0.21 0.21 0.21 0.21 0.21 1.4 0.24 0.35 Unit
Table 18.
APB1 USART2 USART3 I2C1 I2C2
APB2 GPIO E ADC1 SPI1 USART1
1.
(2)
fHCLK = 36 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
2. Specific conditions for ADC: fHCLK = 28 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit in the ADC_CR2 register is set to 1.
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 19 result from tests performed using an high-speed external clock source, and under the ambient temperature and supply voltage conditions summarized in Table 8.
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Electrical characteristics Table 19.
Symbol fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) t r(HSE) tf(HSE) IL
STM32F101x8, STM32F101xB
High-speed external user clock characteristics
Parameter User external clock source frequency(1) OSC_IN input pin high level voltage OSC_IN input pin low level voltage OSC_IN high or low time(1) OSC_IN rise or fall time
(1)
Conditions
M in 0 0.7VDD VSS 16
Typ 8
M ax 25 VDD 0.3VDD
Unit MHz
V
ns 5 VSS VIN VDD 1 A
OSC_IN Input leakage current
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an low-speed external clock source, and under the ambient temperature and supply voltage conditions summarized in Table 8. Table 20.
Symbol fLSE_ext VLSEH VLSEL tw(LSE) tw(LSE) tr(LSE) tf(LSE) IL
Low-speed external user clock characteristics
Parameter User external clock source frequency(1) OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) OSC32_IN Input leakage current VSS VIN VDD 0.7VDD VSS 450 ns 5 1 A Conditions Min Typ 32.768 Max 1000 VDD V 0.3VDD Unit kHz
1. Guaranteed by design, not tested in production.
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STM32F101x8, STM32F101xB
Electrical characteristics
Figure 17. High-speed external clock source AC timing diagram
VHSEH 90% VHSEL 10% tr(HSE) THSE tf(HSE) tW(HSE) tW(HSE) t
External clock source
fHSE_ext OSC _I N
IL STM32F10xxx ai14127b
Figure 18. Low-speed external clock source AC timing diagram
VLSEH 90% VLSEL 10% tr(LSE) TLSE tf(LSE) tW(LSE) tW(LSE) t
External clock source
fLSE_ext
OSC32_I N
IL STM32F10xxx ai14140c
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 21. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
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Electrical characteristics Table 21.
Symbol fOSC_IN RF CL1 CL2(3) i2 gm tSU(HSE)
(5)
STM32F101x8, STM32F101xB
HSE 4-16 MHz oscillator characteristics(1)(2)
Parameter Oscillator frequency Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(4) HSE driving current Oscillator transconductance Star tup time RS = 30 VDD = 3.3 V VIN = VSS with 30 pF load Star tup VDD is stabilized 25 2 Conditions Min 4 Typ 8 200 30 Max 16 Unit MHz k pF
1
mA mA/V ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. 4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
Figure 19. Typical application with an 8 MHz crystal
Resonator with integrated capacitors CL1 OSC_IN 8 MH z resonator CL2 REXT(1) OSC_OU T RF Bias controlled gain STM32F10xxx ai14128b fH S E
1. REXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
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Electrical characteristics
For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Table 22.
Symbol RF CL1 CL2(2) I2 gm tSU(LSE)
(4)
Caution:
LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) LSE driving current Oscillator transconductance Star tup time VDD is stabilized RS = 30 K VDD = 3.3 V VIN = VSS 5 3 Conditions Min Typ 5 15 Max Unit M pF
1.4
A A/V s
1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs above the table. 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
Figure 20. Typical application with a 32.768 kHz crystal
Resonator with integrated capacitors CL1 OSC32_IN 32.768 KH z resonator CL2 RF OSC32_OU T Bias controlled gain STM32F10xxx fLSE
ai14129b
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Electrical characteristics
STM32F101x8, STM32F101xB
5.3.7
Internal clock source characteristics
The parameters given in Table 23 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8.
High-speed internal (HSI) RC oscillator
Table 23.
Symbol fHSI Frequency TA = 40 to 85 C ACCHSI Accuracy of HSI oscillator TA = 10 to 85 C TA = 0 to 70 C TA = 25 C tsu(HSI) IDD(HSI) HSI oscillator startup time HSI oscillator power consumption 1 80
HSI oscillator characteristics(1)(2)
Parameter Conditions Min Typ 8 1 1 1 1 3 2.5 2.2 2 2 100 Ma x Unit MHz % % % % s A
1. Guaranteed by design, not tested in production. 2. VDD = 3.3 V, TA = 40 to 85 C unless otherwise specified.
Low-speed internal (LSI) RC oscillator
Table 24.
Symbol fLSI(2) tsu(LSI)(3) IDD(LSI)(3) Frequency LSI oscillator startup time LSI oscillator power consumption 0.65
LSI oscillator characteristics (1)
Parameter Min 30 Typ 40 Max 60 85 1.2 Unit kHz s A
1. VDD = 3 V, TA = 40 to 85 C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 25 are measured on a wakeup phase with an 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:
Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8.
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STM32F101x8, STM32F101xB Table 25.
Symbol
Electrical characteristics
Low-power mode wakeup timings
Parameter Conditions Wakeup on HSI RC clock HSI RC wakeup time = 2 s HSI RC wakeup time = 2 s, Regulator wakeup from LP mode time = 5 s HSI RC wakeup time = 2 s, Regulator wakeup from power down time = 38 s Typ 1.8 3.6 s 5.4 Unit s
tWUSLEEP(1) Wakeup from Sleep mode Wakeup from Stop mode (regulator in run mode) tWUSTOP(1) Wakeup from Stop mode (regulator in low-power mode)
tWUSTDBY(1) Wakeup from Standby mode
50
s
1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction.
5.3.8
PLL characteristics
The parameters given in Table 26 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 26.
Symbol
PLL characteristics
Parameter PLL input clock(2) Test conditions Value Min(1) 1 40 16 Typ 8.0 Max(1) 25 60 36 200 Unit MHz % MHz s
fPLL_IN fPLL_OUT tLOCK
PLL input clock duty cycle PLL multiplier output clock PLL lock time
1. Based on device characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT.
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5.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = 40 to 85 C unless otherwise specified. Table 27.
Symbol tprog tERASE t ME
Flash memory characteristics
Parameter 16-bit programming time Page (1 KB) erase time Mass erase time Conditions TA = 40 to +85 C TA = 40 to +85 C TA = 40 to +85 C Read mode fHCLK = 36 MHz with 2 wait states, VDD = 3.3 V Min(1) 40 20 20 Typ 52.5 Max(1) 70 40 40 20 Unit s ms ms mA
IDD
Supply current
Write / Erase modes fHCLK = 36 MHz, VDD = 3.3 V Power-down mode / Halt, VDD = 3.0 to 3.6 V
5 50 2 3.6
mA A V
Vprog
Programming voltage
1. Guaranteed by design, not tested in production.
Table 28.
Symbol N END tRET
Flash memory endurance and data retention
Value Parameter Endurance Data retention Conditions TA = 40 C to 85 C TA = 85 C, 1 kcycle(2) TA = 55 C, 10 kcycle(2) Min
(1)
Unit Typ Max kcycles Years
10 30 20
1. Based on characterization not tested in production. 2. Cycling performed over the whole temperature range.
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Electrical characteristics
5.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (Electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in Table 29. They are based on the EMS levels and classes defined in application note AN1709. Table 29.
Symbol VFESD
EMS characteristics
Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance Conditions VDD = 3.3 V, TA = +25 C, fHCLK= 36 MHz conforms to IEC 1000-4-2 Level/Class 2B
VEFTB
VDD = 3.3 V, TA = +25 C, Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins fHCLK = 36 MHz to induce a functional disturbance conforms to IEC 1000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:
Corrupted program counter Unexpected reset Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J 1752/3 standard which specifies the test board and the pin loading. Table 30. EMI characteristics
Conditions Monitored frequency band Max vs. [fHSE/fHCLK] Unit 8/36 MHz 7 8 13 3 .5 dBV
Symbol Parameter
SEMI
Peak level
0.1 MHz to 30 MHz VDD = 3.3 V, TA = 25 C, 30 MHz to 130 MHz LQFP100 package compliant with 130 MHz to 1GHz SAE J 1752/3 SAE EMI Level
5.3.11
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 31.
Symbol VESD(HBM)
ESD absolute maximum ratings
Ratings Electrostatic discharge voltage (human body model) Conditions TA = +25 C conforming to JESD22-A114 Class Maximum value(1) 2 2000 V II 500 Unit
TA = +25 C Electrostatic discharge conforming to VESD(CDM) voltage (charge device model) JESD22-C101
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up performance:
A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78 IC latch-up standard. Table 32.
Symbol LU
Electrical sensitivities
Parameter Static latch-up class Conditions TA = +85 C conforming to JESD78A Class II level A
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5.3.12
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 33 are derived from tests performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL compliant. Table 33.
Symbol VIL VIH VIL VIH
I/O static characteristics
Parameter Conditions Min 0.5 TTL ports 2 2 0.5 CMOS ports 0.65 VDD 200 5% VDD(3) VSS VIN VDD Standard I/Os VIN = 5 V I/O FT 1 A 3 30 30 40 40 5 50 50 k k pF Typ Max 0.8 V VDD+0.5 5.5V 0.35 VDD VDD+0.5 mV mV V Unit
Input low level voltage Standard IO input high level voltage IO FT(1) input high level voltage Input low level voltage Input high level voltage Standard IO Schmitt trigger voltage hysteresis(2)
Vhys
IO FT Schmitt trigger voltage hysteresis(2)
I lkg
Input leakage current (3)
RPU RPD CIO
Weak pull-up equivalent resistor(4) Weak pull-down equivalent resistor(5) I/O pin capacitance
VIN = VSS VIN = VDD
1. FT = Five-volt tolerant. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required), their characteristics consider the most strict CMOS-technology or TTL parameters:
For VIH: if VDD is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included if VDD is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included if VDD is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included if VDD is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included
For VIL:
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed VOL). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 6). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 6).
Output voltage levels
Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. All I/Os are CMOS and TTL compliant. Table 34.
Symbol VOL(1) VOH(2) VOL(1) VOH(2) VOL(1) VOH (2) VOL(1) VOH(2)
Output voltage characteristics
Parameter Output Low level voltage for an I/O pin when 8 pins are sunk at the same time Output High level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Conditions TTL port, IIO = +8 mA, 2.7 V < VDD < 3.6 V CMOS port IIO = +8 mA 2.7 V < VDD < 3.6 V Min Max 0.4 V VDD0.4 0.4 V 2.4 1.3 V VDD1.3 0.4 V VDD0.4 Unit
IIO = +20 mA(3) 2.7 V < VDD < 3.6 V
IIO = +6 mA(3) 2 V < VDD < 2.7 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Based on characterization data, not tested in production.
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Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 21 and Table 35, respectively. Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 35.
MODEx [1:0] bit value(1)
I/O AC characteristics(1)
Symbol Parameter Conditions CL = 50 pF, VDD = 2 V to 3.6 V Ma x 2 125(3) CL = 50 pF, VDD = 2 V to 3.6 V 125 CL= 50 pF, VDD = 2 V to 3.6 V
(3)
Unit MHz
fmax(IO)out Maximum frequency(2) 10 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time
ns
fmax(IO)out Maximum frequency(2) 01 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time
10 25(3)
MHz
CL= 50 pF, VDD = 2 V to 3.6 V 25(3) CL= 30 pF, VDD = 2.7 V to 3.6 V 50 30 20 5 (3) 8 (3) 12(3) 5(3) 8 (3) 12(3) 10
ns
MHz MHz MHz
Fmax(IO)out Maximum
Frequency(2)
CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V
11
tf(IO)out
Output high to low level fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V
ns
tr(IO)out
Output low to high level rise time Pulse width of external signals detected by the EXTI controller
CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V
-
tEXTIpw
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 21. 3. Guaranteed by design, not tested in production.
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Electrical characteristics Figure 21. I/O AC characteristics definition
90% 5 0% 1 0% E XT ERNA L O UTP UT O N 50pF tr ( I O ) o u t T 10%
STM32F101x8, STM32F101xB
50% 90% tr ( I O) o u t
Maxi mum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF
ai14131
5.3.13
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 33). Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 36.
Symbol VIL(NRST)(1) VIH(NRST)
(1)
NRST pin characteristics
Parameter NRST Input low level voltage NRST Input high level voltage NRST Schmitt trigger voltage hysteresis Weak pull-up equivalent resistor(2)
(1)
Conditions
Min 0.5 2
Typ
Max 0.8
Unit V
VDD+0.5 200 mV 50 100 k ns ns
Vhys(NRST) RPU VF(NRST)
VIN = VSS
30
40
NRST Input filtered pulse 300
VNF(NRST)(1) NRST Input not filtered pulse
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order).
Figure 22. Recommended NRST pin protection
VDD NRST(2) RPU FILTER 0.1 F Internal Reset
External reset circuit(1)
STM32F10xxx
ai14132b
1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 36. Otherwise the reset will not be taken into account by the device.
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Electrical characteristics
5.3.14
TIM timer characteristics
The parameters given in Table 37 are guaranteed by design. Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 37.
Symbol tres(TIM)
TIMx(1) characteristics
Parameter Timer resolution time fTIMxCLK = 36 MHz Timer external clock frequency on CH1 to CH4 Timer resolution 16-bit counter clock period when internal clock is selected 1 fTIMxCLK = 36 MHz 0.0278 27.8 0 fTIMxCLK = 36 MHz 0 fTIMxCLK/2 18 16 65536 1820 65536 × 65536 Conditions Min 1 Max Unit tTIMxCLK ns MHz MHz bit tTIMxCLK s tTIMxCLK s
fEXT ResTIM tCOUNTER
tMAX_COUNT Maximum possible count
fTIMxCLK = 36 MHz
119.2
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
5.3.15
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 8. The STM32F101xx medium-density access line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 38. Refer also to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL).
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Electrical characteristics Table 38.
Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb
STM32F101x8, STM32F101xB
I2C characteristics
Standard mode I2C(1) Fast mode I2C(1)(2) Parameter Min SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Star t condition hold time Repeated Start condition setup time Stop condition setup time Stop to Start condition time (bus free) Capacitive load for each bus line 4.0 4.7 4.0 4.7 400 4.7 4.0 250 0
(3)
Unit Max Min 1.3 s 0.6 100 0(4) 1000 300 0.6 s 0.6 0.6 1.3 400 s s pF 20+0.1Cb 900(3) 300 300 ns Max
1. Guaranteed by design, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 4 MHz to achieve the maximum fast mode I2C frequency. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
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Electrical characteristics
Figure 23. I2C bus AC waveforms and measurement circuit(1)
VDD 4 .7 k I²C bus VDD 4 .7 k
100 100
STM32F10xxx
SDA SCL
S TAR T REPEATED S TAR T tsu(STA) SD A tf(SDA) th(STA) SCL tw(SCKH) S TAR T
tr(SDA) tw(SCKL)
tsu(SDA) th(SDA) S TOP
tsu(STA:STO)
tr(SCK)
tf(SCK)
tsu(STO)
ai14127c
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 39.
SCL frequency (fPCLK1= 36 MHz, VDD = 3.3 V)(1)(2)
I2C_CCR value fSCL (kHz) RP = 4.7 k 400 300 200 100 50 20 0x801E 0x8028 0x803C 0x00B4 0x0168 0x0384
1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application.
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SPI interface characteristics
Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 8. Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 40.
Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(NSS)(2) th(NSS)(2) tw(SCKH)(2) tw(SCKL)(2) tsu(MI) (2) tsu(SI)(2) th(MI) (2) th(SI)(2)
SPI characteristics(1)
Parameter SPI clock frequency Slave mode SPI clock rise and fall time NSS setup time NSS hold time SCK high and low time Data input setup time Master mode Data input setup time Slave mode Data input hold time Master mode Data input hold time Slave mode Slave mode, fPCLK = 36 MHz, Data output access time presc = 4 Slave mode, fPCLK = 24 MHz SPI1 SPI2 Capacitive load: C = 30 pF Slave mode Slave mode Master mode, fPCLK = 36 MHz, presc = 4 SPI1 SPI2 4 tPCLK 73 50 1 5 1 1 |
