L4970A
10A SWITCHING REGULATOR
10A OUTPUT CURRENT 5.1V TO 40V OUTPUT VOLTAGE RANGE 0 TO 90% DUTY CYCLE RANGE INTERNAL FEED-FORWARD LINE REGULATION INTERNAL CURRENT LIMITING PRECISE 5.1V 2% ON CHIP REFERENCE RESET AND POWER FAIL FUNCTIONS SOFT START INPUT/OUTPUT SYNC PIN UNDER VOLTAGE LOCK OUT WITH HYSTERETIC TURN-ON PWM LATCH FOR SINGLE PULSE PER PERIOD VERY HIGH EFFICIENCY SWITCHING FREQUENCY UP TO 500KHz THERMAL SHUTDOWN CONTINUOUS MODE OPERATION DESCRIPTION The L4970A is a stepdown monolithic power switching regulator delivering 10A at a voltage variable from 5.1 to 40V. BLOCK DIAGRAM
MULTIPOWER BCD TECHNOLOGY
Multiwatt15V ORDERING NUMBER: L4970A
Realized with BCD mixed technology, the device uses a DMOS output transistor to obtain very high efficiency and very fast switching times. Features of the L4970A include reset and power fail for microprocessors, feed forward line regulation, soft start, limiting current and thermal protection. The device is mounted in a 15-lead multiwatt plastic power package and requires few external components. Efficient operation at switching frequencies up to 500KHz allows reduction in the size and cost of external filter components.
June 2000
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L4970A
ABSOLUTE MAXIMUM RATINGS
Symbol V9 V9 V7 I7 V6 V3, V12 V4 I4 V5, V10, V11, V13 I5 I10 I12 Ptot Tj, Tstg Input Voltage Input Operating Voltage Output DC Voltage Output Peak Voltage at t = 0.1s f = 200KHz Maximum Output Current Bootstrap Voltage Bootstrap Operating Voltage Input Voltage at Pins 3, 12 Reset Output Voltage Reset Output Sink Current Input Voltage at Pin 5, 10, 11, 13 Reset Delay Sink Current Error Amplifier Output Sink Current Soft Start Sink Current Total Power Dissipation at Tcase < 120C Junction and Storage Temperature Parameter Value 55 50 -1 -7 Internally Limited 65 V9 + 15 12 50 50 7 30 1 30 30 -40 to 150 V V V V mA V mA A mA W C Unit V V V V
PIN CONNECTION (Top view)
THERMAL DATA
Symbol Rth j-case Rth j-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient max max Value 1 35 Unit C/W C/W
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PIN FUNCTIONS
No 1 2 3 Name OSCILLATOR OSCILLATOR RESET INPUT Function Rosc. External resistor connected to ground determines the constant charging current of Cosc. Cosc. External capacitor connected to ground determines (with Rosc) the switching frequency. Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider to the input for power fail function. It must be connected to the pin 14 an external 30K resistor when power fail signal not required. Open Collector Reset/power Fail Signal Output. This output is high when the supply and the output voltages are safe. A Cd capacitor connected between this terminal and ground determines the reset signal delay time. A Cboot capacitor connected between this terminal and the output allows to drive properly the internal D-MOS transistor. Regulator Output. Common Ground Terminal Unregulated Input Voltage. A series RC network connected between this terminal and ground determines the regulation loop gain characteristics. The Feedback Terminal of the Regulation Loop. The output is connected directly to this terminal for 5.1V operation; It is connected via a divider for higher voltages. Soft Start Time Constant. A capacitor is connected between thi sterminal and ground to define the soft start time constant. Multiple L4970A are synchronized by connecting pin 13 inputs together or via an external syncr. pulse. 5.1V Vref Device Reference Voltage. Internal Start-up Circuit to Drive the Power Stage.
4 5 6 7 8 9 10 11
RESET OUT RESET DELAY BOOTSTRAP OUTPUT GROUND SUPPLY VOLTAGE FREQUENCY COMPENSATION FEEDBACK INPUT
12 13 14 15
SOFT START SYNC INPUT Vref Vstart
CIRCUIT OPERATION (refer to the block diagram) The L4970A is a 10A monolithic stepdown switching regulator working in continuous mode realized in the new BCD Technology. This technology allows the integration of isolated vertical DMOS power transistors plus mixed CMOS/Bipolar transistors. The device can deliver 10A at an output voltage adjustable from 5.1V to 40V, and contains diagnostic and control functions that make it particularly suitable for microprocessor based systems. BLOCK DIAGRAM The block diagram shows the DMOS power transistor and the PWM control loop. Integrated functions include a reference voltage trimmed to 5.1V 2%, soft start, undervoltage lockout, oscillator with feedforward control, pulse by pulse current limit, thermal shutdown and finally the reset and power fail circuit. The reset and power fail circuit provides an output signal for a microprocessor indicating the status of the system.
Device turn on is around 11V with a typical 1V hysteresis, this threshold provides a correct voltage for the driving stage of the DMOS gate and the hysteresis prevents instabilities. An external bootstrap capacitor charged to 12V by an internal voltage reference is needed to provide correct gate drive to the power DMOS. The driving circuit is able to source and sink peak currents of around 0.5A to the gate of the DMOS transistor. A typical switching time of the current in the DMOS transistor is 50ns. Due to the fast commutation switching frequencies up to 500kHz are possible. The PWM control loop consists of a sawtooth oscillator, error amplifier, comparator, latch and the output stage. An error signal is produced by comparing the output voltage with the precise 5.1V 2% on chip reference. This error signal is then compared with the sawtooth oscillator, in order to generate a fixed frequency pulse width modulated drive for the output stage. A PWM latch is included to eliminate multiple pulsing within a period even in noisy environments. The gain and
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Figure 1: Feedforward Waveform
Figure 2: Soft Start Function
Figure 3: Limiting Current Function
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stability of the loop can be adjusted by an external RC network connected to the output of the error amplifier. A voltage feedforward control has been added to the oscillator, this maintains superior line regulation over a wide input voltage range. Closing the loop directly gives an output voltage of 5.1V, higher voltages are obtained by inserting a voltage divider. At turn on output overcurrents are prevented by the soft start function (fig. 2). The error amplifier is initially clamped by an external capacitor Css and allowed to rise linearly under the charge of an internal constant current source. Output overload protection is provided by a current limit circuit (fig. 3). The load current is sensed by an internal metal resistor connected to a comparator. When the load current exceeds a preset threshold the output of the comparator sets a flip flop which turns off the power DMOS. The next clock pulse, from an internal 40kHz oscillator will reset the flip flop and the power DMOS will again conduct. This current protection method, ensures Figure 4: Reset and Power Fail Functions. a constant current output when the system is overloaded or short circuited and limits the switching frequency, in this condition, to 40kHz. The Reset and Power fail circuitry (fig 4) generates an output signal when the supply voltage exceeds a threshold programmed by an external voltage divider. The reset signal, is generated with a delay time programmed by an external capacitor on the delay pin. When the supply voltage falls below the threshold or the output voltage goes below 5V the reset output goes low immediately. The reset output is an open collector-drain. Fig 4A shows the case when the supply voltage is higher than the threshold, but the output voltage is not yet 5V. Fig 4B shows the case when the output is 5.1V but the supply voltage is not yet higher than the fixed threshold. The thermal protection disables circuit operation when the junction temperature reaches about 150C and has an hysterysis to prevent unstable conditions.
A
B
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ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tj = 25C, Vi = 35V, R4 = 16K, C9 = 2.2nF, fSW = 200KHz typ, unless otherwise specified) DYNAMIC CHARACTERISTICS
Symbol Vi Vo Vo Vo Parameter input Voltage Range (pin 9) Output Votage Line Regulation Load Regulation Test Condition Vo = Vref to 40V Io = 10A Vi = 15V to 50V Io = 5A; Vo = Vref Vi = 15V to 50V Io = 5A; Vo = Vref Vo = Vref Io = 3A to 6A Io = 2A to 10A Io = 5A Io = 10A Vi = 15 to 50V Io = 5A Vo = Vref Vo = 12V Io = 10A Vo = Vref Vo = 12V SVR f f Supply Voltage Ripple Reject. Switching Frequency Voltage Stability of Swiching Frequency Temperature Stability of Swiching Frequency Maximum Operating Switching Frequency Vi = 15V to 45V Tj = 0 to 125C Vo = Vref; R4 = 10K Io = 10A; C9 = 1nF 500 Vi = 2VRMS; Io = 5A f = 100Hz; Vo = Vref 11 80 Min. 15 5 5.1 12 Typ. Max. 50 5.2 30 Unit V V mV Fig. 5 5 5 5 10 20 0.55 1.1 13 85 92 80 87 60 200 2 1 220 6 30 50 0.8 1.6 15 mV mV V V A % % 5 75 56 180 % % dB KHz % % KHz 5 5 5 5 5 5 5 5
Vd I7L
Dropout Voltage Between Pin 9 and 7 Max. Limiting Current Efficiency
Vi f Tj
fmax
Vref SECTION (pin 14)
Symbol V14 V14 V14 V14 T I14 short Parameter Reference Voltage Line Regulation Load Regulation Average Temperature Coefficient Reference Voltage Short Circuit Current Limit Vi = 15V to 50V I14 = 0 to 1mA Tj = 0C to 125C Test Condition Min. 5 Typ. 5.1 10 20 0.4 Max. 5.2 25 40 Unit V mV mV mV/C Fig. 7 7 7 7
V14 = 0
70
mA
7
VSTART SECTION (pin 15)
Symbol V15 V15 V15 I15 short Parameter Reference Voltage Line Regulation Load Regulation Short Circuit Current Limit Vi = 15 to 50V I15 = 0 to 1mA V15 = 0V Test Condition Min. 11.4 Typ. 12 0.6 50 80 Max. 12.6 1.4 200 Unit V V mV mA Fig. 7 7 7 7
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ELECTRICAL CHARACTERISTICS (continued) DC CHARACTERISTICS
Symbol V9on V9 Hyst I9 Q I9OQ I7L Parameter Turn-on Threshold Turn-off Hysteresys Quiescent Current Operating Supply Current Out Leak Current V12 = 0; S1 = D V12 = 0; S1 = C; S2 = B Vi = 55V; S3 = A; V12 = 0 Test Condition Min. 10 Typ. 11 1 13 16 19 23 2 Max. 12 Unit V V mA mA mA Fig. 7A 7A 7A 7A 7A
SOFT START
Symbol I12 V12 Parameter Soft Start Source Current Output Saturation Voltage Test Condition V12 = 3V; V11 = 0V I12 = 20mA; V9 = 10V I12 = 200A; V9 = 10V Min. 70 Typ. 100 Max. 130 1 0.7 Unit A V V Fig. 7B 7B 7B
ERROR AMPLIFIER
Symbol V10H V10L I10H I10L I11 GV SVR VOS Parameter High Level Out Voltage Low Level Out Voltage Source Output Current Sink Output Current Input Bias Current DC Open Loop Gain Supply Voltage Rejection Input Offset Voltage Test Condition I10 = -100A; S1 = C V11 = 4.7V I10 = +100A; S1 = C V11 = 5.3V; V10 = 1V; S1 = E V11 = 4.7V V10 = 6V; S1 = D V11 = 5.3V RS = 10K VVCM = 4V; RS = 10 15 < Vi < 50V; RS = 10 RS = 50 100 100 150 150 0.4 60 60 80 2 10 3 Min. 6 1.2 Typ. Max. Unit V V A A A dB dB mV Fig. 7C 7C 7C 7C
RAMP GENERATOR (pin 2)
Symbol V2 V2 I2 I2 Parameter Ramp Valley Ramp Peak Min. Ramp Current Max. Ramp Current Test Condition S1 = C; S2 = B S1 = C; S2 = B; Vi = 15V Vi = 45V 2.4 Min. 1.2 Typ. 1.5 2.5 5.5 270 2.7 300 Max. Unit V V V A mA Fig. 7A 7A 7A 7A 7A
S1 = A; I1 = 100A S1 = A; I1 = 1mA
SYNC FUNCTION (pin 13)
Symbol V13 V13 I13L I13H V13 tW Parameter Low Input Voltage High Input voltage Sync Input Current with Low Input Voltage Input Current with High Input Voltage Output Amplitude Output Pulse Width Vthr = 2.5V Test Condition Vi = 15V to 50V; V12 = 0; S1 = C; S2 = B; S4 = B V12 = 0; S1 = C; S2 = B; S4 = B V13 = V2 = 0.9V; S4 = A; S1 = C; S2 = B V13 = 3.5V; S4 = A; S1 = C; S2 = B 4 0.3 5 0.5 0.8 Min. 0.3 3.5 Typ. Max. 0.9 5.5 0.4 2 Unit V V mA mA V s Fig. 7A 7A 7A 7A
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ELECTRICAL CHARACTERISTICS (continued) RESET AND POWER FAIL FUNCTIONS
Symbol V11R V11F V5H V5L I5SO I5SI V4S I4 V3R V3H I3 Parameter Rising Threshold Voltage (pin 11) Falling Threshold Voltage (pin 11) Delay High Threshold Voltage Delay Low Threshold Voltage Delay Source Current Delay Sink Current Out Saturation Voltage Output Leak Current Rising Threshold Voltage Hysteresys Input Bias Current Test Condition Vi = 15 to 50V V3 = 5.3V Vi = 15 to 50V V3 = 5.3V Vi = 15 to 50V V14 = V11 V3 = 5.3V Vi = 15 to 50V V14 = V11 V3 = 5.3V V3 = 5.3V; V5 = 3V V3 = 4.7V; V5 = 3V I4 = 15mA; S1 = B V3 = 4.7V V4 = 50V; S1 = A V3 = 5.3V V11 = V14 4.95 0.4 5.1 0.5 1 Min. Vref 120 4.77 4.95 1 40 10 0.4 100 5.25 0.6 3 Typ. Vref 100 Vref 200 5.1 1.1 60 Max. Vref 80 Vref 160 5.25 1.2 80 Unit V mV V mV V V A mA V A V V A Fig. 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D 7D
Figure 5: Test and Evaluation Board Circuit
TYPICAL PERFORMANCES (using evaluation board) : n = 83% (Vi = 35V ; Vo = VREF ; Io = 10A ; fSW = 200KHz) Vo RIPPLE = 30mV (at 10A) with output filter capacitor ESR 60m Line regulation = 5mV (Vi = 15 to 50V) Load regulation = 15mV (Io = 2 to 10A) For component values, refer to test circuit part list.
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Figure 6a: P.C. Board (components side) and Components Layout of Figure 5 (1:1 scale).
PARTS LIST
R1 = 30K R2 = 10K R3 = 15K R4 = 16K R5 = 22 0,5W R6 = 4K7 R7 = 10 R8 = see tab. A R9 = OPTION R10 = 4K7 R11 = 10 L1 = 40H C9 = 2.2nF KP1830 C10 = 220nF MKT C 11 = 2.2nF MP1830 **C12, C13, C14 = 220F 40VL EKR C15 = 1F Film C1, C2 = 3300F 63VL EYF (ROE C3, C4, C5, C6 = 2.2F C7 = 390pF Film C8 = 22nF MKT 1817 (ERO)
Table A
V0 12V 15V 18V 24V R9 4.7k 4.7k 4.7k 4.7k R7 6.2kW 9.1k 12k 18k
Table B SUGGESTED BOOTSTRAP CAPACITORS
Operating Frequency f = 20KHz f = 50KHz f = 100KHz f = 200KHz f = 500KHz Bootstrap Cap.c10 680nF 470nF 330nF 220nF 100nF
D1 = MBR 1560CT (or 16A/60V or equivalent) core 58071 MAGNETICS 27 TURNS Ø 1,3mm (AWG 16) COGEMA 949178
* 2 capacitors in parallel to increase input RMS current capability ** 3 capacitors in parallel to reduce total output ESR
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Figure 6b: P.C. Board (Back side) and Components Layout of the Circuit of Fig. 5. (1:1 scale)
Figure 7: DC Test Circuits
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Figure 7A
Figure 7B
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Figure 7D
Figure 7C
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Figure 8: Quiescent Drain Current vs. Supply Voltage (0% duty cycle - see fig. 7A). Figure 9: Quiescent Drain Current vs. Junction Temperature (0% duty cycle).
Figure 10: Quiescent Drain Current vs. Duty Cycle
Figure 11: Reference Voltage (pin14) vs. Vi (see fig. 7)
Figure 12: Reference Voltage (pin 14) vs. Junction Temperature (see fig. 7)
Figure 13: Reference Voltage (pin15) vs. Vi (see fig. 7)
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Figure 14: Reference Voltage (pin 15) vs. Junction Temperature (see fig. 7) Figure 15: Reference Voltage 5.1V (pin 14) Supply Voltage Ripple Rejection vs. Frequency
Figure 16: Switching Frequency vs. Input Voltage (see fig. 5)
Figure 17: Switching Frequency vs. Junction Temperature (see fig 5)
Figure 18: Switching Frequency vs. R4 (see fig. 5)
Figure 19: Max. Duty Cycle vs. Frequency
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Figure 20: Supply Voltage Ripple Rejection vs. Frequency (see fig. 5) Figure 21: Line Transient Response (see fig. 5)
Figure 22: Load Transient Response (see fig. 5)
Figure 23: Dropout Voltage Between Pin 9 and Pin 7 vs. Current at Pin 7
Figure 24: Dropout Voltage Between Pin 9 and Pin 7 vs. Junction Temperature
Figure 25: Power Dissipation (device only) vs. Input Voltage
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Figure 26: Power Dissipation (device only) vs. Output Voltage Figure 27: Heatsink Used to Derive the Device's Power Dissipation Tcase - Tamb Rth - Heatsink = Pd
Figure 28: Efficiency vs. Output Current Figure 29: Efficiency vs. Output Voltage
Figure 30: Efficiency vs. Output Voltage
Figure 31: Open Loop Frequency and Phase Response of Error Amplifier (see fig.7C)
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Figure 32: Power Dissipation Derating Curve
Figure 33: A5.1V/12V Multiple Supply. Note the Synchronization between the L4970A and the L4974A
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Figure 34: 5.1V / 10A Low Cost Application
Figure 35: 10A Switching Regulator, Adjustable from 0V to 25V.
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Figure 36: L4970A's Sync. Example
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DIM. MIN. A B C D E F G G1 H1 H2 L L1 L2 L3 L4 L7 M M1 S S1 Dia1 21.9 21.7 17.65 17.25 10.3 2.65 4.25 4.63 1.9 1.9 3.65 0.49 0.66 1.02 17.53 19.6
mm TYP. MAX. 5 2.65 1.6 1 0.55 0.75 1.27 17.78 1.52 18.03 20.2 22.2 22.1 17.5 10.7 4.55 5.08 22.5 22.5 18.1 17.75 10.9 2.9 4.85 5.53 2.6 2.6 3.85 0.862 0.854 0.695 0.679 0.406 0.104 0.167 0.182 0.075 0.075 0.144 0.019 0.026 0.040 0.690 0.772 MIN.
inch TYP. MAX. 0.197 0.104 0.063 0.039 0.022 0.030 0.050 0.700 0.060 0.710 0.795 0.874 0.870 0.689 0.421 0.179 0.200 0.886 0.886 0.713 0.699 0.429 0.114 0.191 0.218 0.102 0.102 0.152
OUTLINE AND MECHANICAL DATA
Multiwatt15 V
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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