ST7SCR
8-BIT LOW-POWER, FULL-SPEED USB MCU WITH 16K FLASH, 768 RAM, SMARTCARD I/F, TIMER
Memories Up to 16K of ROM or High Density Flash (HDFlash) program memory with read/write protection, HDFlash In-Circuit and In-Application Programming. 100 write/erase cycles guaranteed, data retention: 40 years at 55C Up to 768 bytes of RAM including up to 128 bytes stack and 256 bytes USB buffer Clock, Reset and Supply Management Low Voltage Reset 2 power saving modes: Halt and Wait modes PLL for generating 48 MHz USB clock using a 4 MHz crystal Interrupt Management Nested Interrupt Controller USB (Universal Serial Bus) Interface 256-byte buffer for full speed bulk, control and interrupt transfer types compliant with USB specification (version 2.0) On-Chip 3.3V USB voltage regulator and transceivers with software power-down 7 USB Endpoints: One 8-byte Bidirectional Control Endpoint One 64-byte In Endpoint, One 64-byte Out Endpoint Four 8-byte In Endpoints 35 or 4 I/O ports Up to 4 LED outputs with software programmable constant current (3 or 7 mA). 2 General purpose I/Os programmable as interrupts Up to 8 line inputs programmable as interrupts Up to 20 Outputs 1 line assigned by default as static input after reset
ST7FSC R1T1 16K FLASH ST7SCR1T1 16K ROM
LQFP64 14x14
SO24
QFN24
ISO7816-3 UART Interface 4 Mhz Clock generation Synchronous/Asynchronous protocols (T=0, T=1) Automatic retry on parity error Programmable Baud rate from 372 clock pulses up to 11.625 clock pulses (D=32/F=372) Card Insertion/Removal Detection Smartcard Power Supply Selectable card VCC 1.8V, 3V, and 5V Internal Step-up converter for 5V supplied Smartcards (with a current of up to 55mA) using only two external components. Programmable Smartcard Internal Voltage Regulator (1.8V to 3.0V) with current overload protection and 4 KV ESD protection (Human Body Model) for all Smartcard Interface I/Os One 8-bit Timer Time Base Unit (TBU) for generating periodic interrupts. Development Tools Full hardware/software development package
Table 1. Device Summary
Features Program memory User RAM (stack) bytes Peripherals Operating Supply CPU Frequency Operating temperature Package LQFP64 ST7FSCR1M 1 16K FLASH 768 (128) USB Full-Speed (7 Ep), TBU, Watchdog timer, ISO7816-3 Interface 4.0 to 5.5V 4 or 8 Mhz 0C to +70C SO24 QFN24 ST7SCR1M1 16K ROM S T7SCR1U1 16K ROM
Rev. 4.0
Apr 2007 1/101
1 www.st.com
Table of Contents
ST7SCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 PROGRAM MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.4 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101. ... 38 41 42 42
12.2 TIME BASE UNIT (TBU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.3 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Table of Contents
12.4 SMARTCARD INTERFACE (CRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 13.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 13.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 14 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.3 SUPPLY AND RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 14.4 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 14.5 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 14.6 SMARTCARD SUPPLY SUPERVISOR ELECTRICAL CHARACTERISTICS . . . . . . . . . . 84 14.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 14.8 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 89 15 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 15.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 92 16.1 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . . 93 16.2 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 16.3 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 17 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 17.1 UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 17.2 FLASH DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 18 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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ST7SCR
1 INTRODUCTION
The ST7SCR and ST7FSCR devices are members of the ST7 microcontroller family designed for USB applications. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7SCR ROM devices are factory-programmed and are not reprogrammable. The ST7FSCR versions feature dual-voltage Flash memory with Flash Programming capability. They operate at a 4MHz external oscillator frequency. Under software control, all devices can be placed in WAIT or HALT mode, reducing power consumption when the application is in idle or stand-by state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unFigure 1. ST7SCR Block Diagram
OSCIN OSCOUT 4MHz OSCILLATOR PLL 48 MHz DIVIDER USB DATA BUFFER (256 bytes) USBDP USBDM USBVCC 8 MHz or 4 MHz
ADDRESS AND DATA BUS
signed multiplication and indirect addressing modes. The devices include an ST7 Core, up to 16 Kbytes of program memory, up to 512 bytes of user RAM, up to 35 I/O lines and the following on-chip peripherals: USB full speed interface with 7 endpoints, programmable in/out configuration and embedded 3.3V voltage regulator and transceivers (no external components are needed). ISO7816-3 UART interface with Programmable Baud rate from 372 clock pulses up to 11.625 clock pulses Smartcard Supply Block able to provide programmable supply voltage and I/O voltage levels to the smartcards Low voltage reset ensuring proper power-on or power-off of the device (selectable by option) Watchdog Timer 8-bit Timer (TBU)
PORT A PORT B PORT C PORT D LED ISO7816 UART SUPPLY MANAGER
PA[5:0] PB[7:0] PC[7:0] PD[7:0] LED[3:0]
USB
WATCHDOG 8-BIT TIMER PA6 VPP CONTROL 8-BIT CORE ALU LVD RAM (512 Bytes) PROGRAM MEMORY (16K Bytes)
DIODE SELF DC/DC CONVERTER CRDVCC CRDDET CRDIO CRDC4 CRDC8 3V/1.8V Vreg CRDRST CRDCLK
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ST7SCR
2 PIN DESCRIPTION
Figure 2. 64-Pin LQFP Package Pinout
NC = Not Connected
CRD RST NC CRDC LK NC C4 CRDIO C8 GN D PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CRDVC C GND GND A DIODE SELF1 SELF2 PA5 PA4 NC NC LED3 LED2 LED1 VDD VDDA USBVcc NC DP DM LE D0 P A6 VPP P C 7/W AKUP1 P C 6/W AKUP1 P C 5/W AKUP1 P C 4/W AKUP1 P C 3/W AKUP1 P C 2/W AKUP1 P C 1/W AKUP1 P C 0/W AKUP1 G ND V DD CRDDET VDD W AKUP2/ICCDATA /PA0 WAKUP2/ICCCLK/PA1 WAKUP 2 /PA2 WAKUP 2 /PA3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 OSCIN O SCOUT
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ST7SCR
PIN DESCRIPTION (Cont'd) Figure 3. 24-Pin SO Package Pinout
DIODE G NDA GND CR DVCC C RDRST C RDCLK C4 CRDIO C8 C RDDET ICC DATA/W AKUP2/PA0 IC CCLK/W AKUP2/PA1
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
SELF V DD VDDA USBVcc DP DM LED0 PA6 VP P OSCO UT OSCIN NC
Figure 4. 24-Lead QFN Package Pinout
DIODE
G NDA
24
23
22
21
20
19 18
CRDVCC CRDRS T CRDCLK C4 C RDIO C8
1
V DDA
S ELF
G ND
V DD
USBVCC DP DM LED0 PA6 GND
2
17
3
16
4
15
5
14
6 7 8 9 10 11 12
13
ICCDATA /WA KUP2/PA 0
ICCCLK/WAKUP2/PA1
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OSCOU T
CRDDE T
NC
OSCIN
ST7SCR
PIN DESCRIPTION (Cont'd) Legend / Abbreviations: Type: I = input, O = output, S = supply In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 10mA high sink (on N-buffer only) Table 2. Pin Description
Pin n LQFP64 Type QFN24 SO24 Pin Name Level O u tput Input VCARD supplied
Port and control configuration: Input:float = floating, wpu = weak pull-up, int = interrupt, ana = analog Output: OD = open drain, PP = push-pull Refer to "I/O PORTS" on page 32 for more details on the software configuration of the I/O ports.
Port / Control Input Output wpu OD PP int
Main Function (after reset)
Alternate Function
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
2 5 CR DRST NC 3 6 CR DCLK NC 4 7 C4 5 8 CRDIO 6 9 C8 3 G ND PB 0 PB 1 PB 2 PB 3 PB 4 PB 5 PB 6 PB 7
O
CT X
X
Smartcard Reset Not Connected
O
CT X
X
Smartcard Clock Not Connected
O I/O O S O O O O O O O O I S I/O I/O I/O I/O O O O CT
CT X CT X X X
X
Smartcard C4 Smartcard I/O
CT X
X
Smartcard C8 Ground
CT CT CT CT CT CT CT CT X
X X X X X X X X
X X X X X X X X
Port B0 1) Port B1 1) Port B2 1) Port B3 1) Port B4 1) Port B5 1) Port B6 1) Port B7 1) Smartcard Detection Power Supply voltage 4V-5.5V
17 7 10 CR DDET 18 19 8 11 VD D
PA 0/WA KUP2/ ICCDATA PA 1/WA KUP2/ 20 9 12 ICCCLK 21 22 23 24 25 PA 2/WA KUP2 PA 3/WA KUP2 PD 0 PD 1 PD 2
CT CT CT CT CT CT CT
X X X X
X X X X
X X X X X X X
X X X X X X X
Port A0 Port A1 Port A2 1) Port A3 Port D0
1) 1)
Interrupt, In-Circuit Communication Data Input Interrupt, In-Circuit Communication Clock Input Interrupt Interrupt
Port D1 1) Port D2 1)
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ST7SCR
Pin n LQ FP64 Type QFN24 SO 24 Pin Name
Level Output Input
VCARD supplied
Port / Control Input Output wpu OD PP int
Main Function (after reset)
Alternate Function
26 27 28 29 30
PD 3 PD 4 PD 5 PD 6 PD 7
O O O O O CT
CT CT CT CT CT
X X X X X
X X X X X
Port D3 1) Port D4 1) Port D5 1) Port D6 1) Port D7 1) Input/Output Oscillator pins. These pins connect a 4MHz parallel-resonant crystal, or an external source to the on-chip oscillator. Power Supply voltage 4V-5.5V Ground
31 11 14 O SCIN 32 12 15 O SCOUT 33 34 35 36 37 38 39 40 41 42 43 13 VD D G ND PC 0/WA KUP1 PC 1/WA KUP1 PC 2/WA KUP1 PC 3/WA KUP1 PC 4/WA KUP1 PC 5/WA KUP1 PC 6/WA KUP1 PC 7/WA KUP1 1 6 VP P G ND S S I I I I I I I I S S I O I/O I/O
CT
CT CT CT CT CT CT CT CT
X X X X X X X X
X X X X X X X X
PC0 1) P C1 P C2
1) 1)
External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt
PC3 1) PC4 1) P C5 P C6
1) 1)
PC7 1)
Flash programming voltage. Must be held low in normal operating mode. Must be held low in normal operating mode. CT HS CT CT X P A6 Constant Current Output USB Data Minus line USB Data Plus line Not Connected
44 14 17 PA6 45 15 18 LED 0 46 16 19 DM 47 17 20 DP 48 NC
49 18 21 US BVCC 5 0 1 9 2 2 VDDA 5 1 2 0 2 3 VDD 52 53 54 55 56 LED 1 LED 2 LED 3 NC NC
O S S O O O
CT
3.3 V Output for USB power Supply voltage 4V-5.5V power Supply voltage 4V-5.5V
HS HS HS
X X X
Constant Current Output Constant Current Output Constant Current Output Not Connected Not Connected
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ST7SCR
Pin n LQ FP64 Type QFN24 SO 24 Pin Name
Level Output Input
VCARD supplied
Port / Control Input Output wpu OD PP int
Main Function (after reset)
Alternate Function
57 58
PA 4 PA 5
I /O I /O O O S S
CT CT CT CT CT
X X
X X
X X
X X
Port A4 Port A5 An External inductance must be connected to these pins for the step up converter (refer to Figure 5 to choose the right capacitance) An External diode must be connected to this pin for the step up converter (refer to Figure 5 to choose the right component) Ground
59 21 24 SE LF2 60 21 24 SE LF1 61 22 1 DIODE 62 23 2 G NDA 63 24 3 G ND 64 1 4 CD RVCC
S O CT X Smartcard Supply pin
Notes 1. Keyboard interface 2. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground.
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ST7SCR
PIN DESCRIPTION Figure 5. Smartcard Interface Reference Application - 24-Pin SO Package VDD
C1 L1 D1 C3
DIOD E GNDA GND C RDVCC
SELF V DD VDDA US BVcc DP DM LED0 PA6 VP P OSCOU T OSCIN NC LED VDD C2 R
VD D
C4 C5 C6
CRDR ST CRDCLK C4 CRD IO C8 CR DDET PA0 PA 1
D+ D-
CL 1
CL 2
Mandatory values for the external components : C1 : 4.7 F 1) C2 : 100nF 1)
C3 : 1 nF
C4 : 4.7 F,ESR 0.5 Ohm
C5 : 470 pF C6 : 100 pF
R : 1.5kOhm L1 : 10 H, 2 Ohm Crystal 4.0 MHz, Impedance max100 Ohm Cl1, Cl2 2) D1: BAT42 SHOTTKY
Note 1: C1 and C2 must be located close to the chip.
Note 2: Refer to section 6 on page 21 & Section 14.4.3 Crystal Resonator Oscillators.
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ST7SCR
Figure 6. Smartcard Interface Reference Application - 64-Pin LQFP Package
D1
C3
L1 VDD C1
VDD
C2
C4 C5
C6
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
R LED D+ DVDD
CL1 C8 CL 2
Mandatory values for the external components : C1 : 4.7 F 1) C2 : 100nF 1)
C3 : 1 nF
C7
C4 : 4.7 F,ESR 0.5 Ohm
C5 : 470 pF C6 : 100 pF C7 : 100 nF 1) C8 : 100 nF 1)
R : 1.5kOhm L1 : 10 H, 2 Ohm Crystal 4.0 MHz, Impedance max100 Ohm Cl1, Cl2 2) D1: BAT42 SHOTTKY
Note 1: C1, C2, C7 and C8 must be located close to the chip.
Note 2: Refer to section 6 on page 21 & Section 14.4.3 Crystal Resonator Oscillators.
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ST7SCR
3 REGISTER & MEMORY MAP
As shown in Figure 7, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 40 bytes of register locations, up to 512 bytes of RAM and up to 16K bytes of user program memory. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh. Figure 7. Memory Map The highest address bytes contain the user reset and interrupt vectors. IMPORTANT: Memory locations noted "Reserved" must never be accessed. Accessing a reserved area can have unpredictable effects on the device.
0000h 003Fh 0040h
HW Registers (see Table 3)
0040h 00FFh 0100h 017Fh 0180h
Short Addressing RAM (192 Bytes) Stack (128 Bytes)
R AM (512 Bytes)
023Fh 0240h
16-bit Addressing RAM ( 192 Bytes) USB RAM
023Fh
033Fh
256 Bytes Unused
C000h
Program Memory (16K Bytes)
FFDFh FFE0h
FFFFh
Interrupt & Reset Vectors (see Table 8)
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ST7SCR
Table 3. Hardware Register Memory Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh MISC Port D Port C Port B Port A W atchdog CRD Block Register Label CRD CR CRDSR CRDCCR CRDETU1 CRD ETU0 CRD GT1 CRDGT0 CRDWT2 CRDWT1 CRDWT0 CRDIER CRD IPR CRDTXB CRDRXB W DGCR PADR PADD R PAO R PAPU CR PBDR PBO R PBPU CR PCD R PDD R PDO R PDPU CR MISCR1 MISCR2 MISCR3 MISCR4 Register name Smartcard Interface Control Register Smartcard Interface Status Register Smartcard Contact Control Register Smartcard Elementary Time Unit 1 Smartcard Elementary Time Unit 0 Smartcard Guard time 1 Smartcard Guard time 0 Smartcard Character Waiting Time 2 Smartcard Character Waiting Time 1 Smartcard Character Waiting Time 0 Smartcard Interrupt Enable Register Smartcard Interrupt Pending Register Smartcard Transmit Buffer Register Smartcard Receive Buffer Register Watchdog Control Register Port A Data Register Port A Data Direction Register Option Register Pull up Control Register Port B Data Register Option Register Pull up Control Register Port C Data Register Port D Data Register Option Register Pull up Control Register Miscellaneous Register 1 Miscellaneous Register 2 Miscellaneous Register 3 Miscellaneous Register 4 Reset Status 00h 80h xxh 01h 74h 00h 0Ch 00h 25h 80h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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Address 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Eh
Block
Register Label USBISTR USBIMR USBC TLR DAD DR USBS R EPO R CNT0RX R CNT0TXR EP1TXR CNT1TXR
Register name USB Interrupt Status Register USB Interrupt Mask Register USB Control Register Device Address Register USB Status Register Endpoint 0 Register EP 0 ReceptionCounter Register EP 0 Transmission Counter Register EP 1 Transmission Register EP 1 Transmission Counter Register EP 2 Reception Register EP 2 Reception Counter Register EP 2 Transmission Register EP 2 Transmission Counter Register EP 3 Transmission Register EP 3 Transmission Counter Register EP 4 Transmission Register EP 4 Transmission Counter Register EP 5 Transmission Register EP 5 Transmission Counter Register Error Status Register Timer counter value Timer control status Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 Flash Control Status Register LED Control Register
Reset Status 00h 00h 06h 00h 00h 0xh 00h 00h 00h 00h 00h 0xh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh FFh FFh FFh 00h 00h
Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
US B
EP2RX R CNT2RX R EP2TXR CNT2TXR EP3TXR CNT3TXR EP4TXR CNT4TXR EP5TXR CNT5TXR ERR SR TBUCV TBUCS R ITSPR0 ITSPR1 ITSPR2 ITSPR3 FCSR LED_CTR L
TBU
ITC
Flash
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4 FLASH PROGRAM MEMORY
4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming). The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features
user sectors (see Table 4). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 8). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh). Table 4. Sectors available in FLASH devices
Flash Memory Size (bytes) 4K 8K > 8K Available Sectors Sector 0 Sectors 0,1 Sectors 0,1, 2
Three Flash programming modes: Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Read-out protection Register Access Security System (RASS) to prevent accidental programming or erasing
Figure 8. Memory map and sector address
16K USER FLASH M EMO RY SIZE
C000h ex.: user program 8 Kbytes SECTOR 2 ex.: user data 4 Kbytes SECTOR 1 4 Kbytes SECTOR 0 + library ex.: user system library + IAP BootLoader
DFFFh E000h EFFFh F000h FFFFh
4.3 Structure The Flash memory is organised in sectors and can be used for both code and data storage. Depending on the overall FLASH memory size in the microcontroller device, there are up to three
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FLASH PROGRAM MEMORY (Cont'd) 4.4 ICP (In-Circuit Programming) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 9). For more details on the pin locations, refer to the device pinout description. ICP needs six signals to be connected to the programming tool. These signals are: VSS: device power supply ground VDD: for reset by LVD OSCIN: to force the clock during power-up ICCCLK: ICC output serial clock pin ICCDATA: ICC input serial data pin VPP: ICC mode selection and programming voltage. Figure 9. Typical ICP Interface
PROGRAMMING TOOL
If ICCCLK or ICCDATA are used for other purposes in the application, a serial resistor has to be implemented to avoid a conflict in case one of the other devices forces the signal level. Note: To develop a custom programming tool, refer to the ST7 FLASH Programming and ICC Reference Manual which gives full details on the ICC protocol hardware and software. 4.5 IAP (In-Application Programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the USB interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
ICC CONNECTOR ICC Cable ICP PROGRAMMING TOOL CONNECTOR HE10 CONNECTOR TYPE 9 10 7 8 5 6 3 4 1 2 APPLICATION BOARD
TO
10k CL2 CL1
4.7k OSCOUT ICCDATA ICCCLK OSCIN VDD VSS VPP
TH E P AP LI AT C IO N
ST7
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FLASH PROGRAM MEMORY (Cont'd) Note: If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 4.6 Program Memory Read-out Protection The read-out protection is enabled through an option bit. For Flash devices, when this option is selected, the program and data stored in the Flash memory are protected against read-out (including a re-write protection). When this protection is removed by reprogramming the Option Byte, the entire Flash program memory is first automatically erased and the device can be reprogrammed. Refer to the Option Byte description for more details .
4.7 Related Documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.
4.8 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 0 0 0
This register is reserved for use by Programming Tool software. It controls the FLASH programming and erasing operations. For details on customizing FLASH programming methods and In-Circuit Testing, refer to the ST7 FLASH Programming and ICC Reference Manual.
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5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES
5.3 CPU REGISTERS The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
Figure 10. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 CONDITION CODE REGISTER 1 1 I1 H I0 N Z C RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 0 Y INDEX REGISTER 0 X INDEX REGISTER 0 ACCUMULATOR
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CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
7
1 1 I1 H I0 N Z
Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test inst ructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1
0 C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details.
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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 017Fh
15 0 7
SP7 SP6 SP5 SP4 SP3 SP2 SP1
8 0 0 0 0 0 0 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Figure 11. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event P USH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11 When an interrupt is received, the SP is decremented and the context is pushed on the stack. On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
PO P Y
IRET
RET or RSP
SP SP CC A X PC H SP PCH @ 017Fh PCL P CL PCH PCL Y CC A X PCH PCL PCH PC L SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 017Fh Stack Lower Address = 0100h
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6 SUPPLY, RESET AND CLOCK MANAGEMENT
6.1 CLOCK SYSTEM 6.1.1 General Description The MCU accepts either a 4MHz crystal or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the internal oscillator frequency (fOSC), which is 4Mhz. After reset, the internal clock (fCPU) is provided by the internal oscillator (4Mhz frequency). To activate the 48-MHz clock for the USB interface, the user must turn on the PLL by setting the PLL_ON bit in the MISCR4 register. When the PLL is locked, the LOCK bit is set by hardware. Figure 12. Clock, Reset and Supply Block Diagram The user can then select an internal frequency (fCPU) of either 4 MHz or 8MHz by programming the CLK_SEL bit in the MISCR4 register (refer to MISCELLANEOUS REGISTERS section on page 39). The PLL provides a signal with a duty cycle of 50 %. The internal clock signal (fCPU) is also routed to the on-chip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%.
MISCR4
-
PLL_ CLK_ ON SEL -
-
-
-
-
LOCK
4 MHz (fOSC)
PLL X 12
48 MHz DIV
4 Mhz 8 Mhz
INTERNAL CLOCK (fCPU)
48 MHz
USB
The internal oscillator is designed to operate with an AT-cut parallel resonant quartz in the frequency range specified for fosc. The circuit shown in Figure 14 is recommended when using a crystal, and Table 5 lists the recommended capacitance. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. The LOCK bit in the MISCR4 register can also be used to generate the fCPU directly from fOSC if the PLL and the USB interface are not active.
Table 5. Recommended Values for 4 MHz Crystal Resonator
RSMAX COSCIN C OSCOUT 20 56pF 56pF 25 47pF 47pF 70 22pF 22pF
Note: RSMAX is the equivalent serial resistor of the crystal (see crystal specification).
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CLOCK SYSTEM (Cont'd) 6.1.2 External Clock An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 13. Figure 13. .External Clock Source Connections
Figure 14. Crystal Resonator
OSCIN
OSCOUT
COSCIN
COSCOUT
OSCIN
OSCOUT NC
EXTERNAL CLOCK
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6.2 RESET SEQUENCE MANAGER (RSM) 6.2.1 Introduction The reset sequence manager has two reset sources: Internal LVD reset (Low Voltage Detection) which includes both a power-on and a voltage drop reset Internal watchdog reset generated by an internal watchdog counter underflow as shown in Figure 16. 6.2.2 Functional Description The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic reset sequence consists of 3 phases as shown in Figure 15: A first delay of 30s + 127 tCPU cycles during which the internal reset is maintained. Figure 15. LVD RESET Sequence
V I T+ VIT-
A second delay of 512 tCPU cycles after the internal reset is generated. It allows the oscillator to stabilize and ensures that recovery has taken place from the Reset state. Reset vector fetch (duration: 2 clock cycles) Low Voltage Detector The low voltage detector generates a reset when VDD
VDD
LVD RESET
RUN
DELAY 1 DELAY 2
LVD RESET INTERNAL RESET
DELAY 1 = 30s + 127 tCPU DELAY 2 = 512 tCPU FETCH VECTOR (2 tCPU)
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Figure 16. Watchdog RESET Sequence
WATCHDOG RESET
RUN
DELAY 1 DELAY 2
WATCHDOG RESET WATCHDOG UNDERFLOW DELAY 1 = 30s + 127 tCPU DELAY 2 = 512 tCPU FETCH VECTOR (2 tCPU)
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7 INTERRUPTS
7.1 INTRODUCTION The CPU enhanced interrupt management provides the following features: Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: Up to 4 software programmable nesting levels Up to 16 interrupt vectors fixed by hardware 3 non maskable events: RESET, TRAP, TLI This interrupt management is based on: Bit 5 and bit 3 of the CPU CC register (I1:0), Interrupt software priority registers (ISPRx), Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) CPU interrupt controller. 7.2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 6). The processing flow is shown in Figure 17. Figure 17. Interrupt Processing Flowchart
RESET PENDING INTERRUPT N Y TLI Interrupt has the same or a lower software priority than current one N I1:0 Interrupt has a higher software priority than current one Y
When an interrupt request has to be serviced: Normal processing is suspended at the end of the current instruction execution. The PC, X, A and CC registers are saved onto the stack. I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 6. Interrupt Software Priority Levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 0 1 I0 0 1 0 1
High
FETCH NEXT INSTRUCTION
THE INTERRUPT STAYS PENDING
Y
"IRET" N
RESTORE PC, X, A, CC FROM STACK
EXECUTE INSTRUCTION
STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR
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INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 18 describes this decision process. Figure 18. Priority Decision Process
PENDING INTERRUPTS
TLI (Top Level Hardware Interrupt) This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. Caution: A TRAP instruction must not be used in a TLI service routine.
Same
SOFTWARE PRIORITY
Different
TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 17 as a TLI. Caution: TRAP can be interrupted by a TLI. RESET The RESET source has the highest priority in the CPU. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET, TRAP and TLI can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the CPU interrupt controller: the non-maskable type (RESET, TLI, TRAP) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 17). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode.
Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the MISCR3 register. External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically NANDed. Peripheral Interrupts Usually the peripheral interrupts cause the Device to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont'd) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 18. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. Figure 19. Concurrent Interrupt Management
SOFTW ARE PRIORITY LEVEL IT2 IT1 IT4 IT3 TLI IT0 I1 I0
7.4 CONCURRENT & NESTED MANAGEMENT The following Figure 19 and Figure 20 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 20. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure.
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1
3 3 3 3 3 3 3/0 10
11 11 11 11 11 11
11 / 10 Figure 20. Nested Interrupt Management
SOFTW ARE PRIORITY LEVEL
TLI
IT0
IT2
IT1
IT4
IT3
I1
I0
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2
3 3 2 1 3 3 3/0 10
11 11 00 01 11 11
11 / 10
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USED STACK = 20 BY TES
USED STACK = 10 BYTES
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INTERRUPTS (Cont'd) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read / Write Reset Value: 111x 1010 (xAh)
7 1 1 I1 H I0 N Z 0 C ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I0_9 I1_4 I1_8 I0_4 I0_8
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)
7 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 0 I0_0
Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 0 1 I0 0 1 0 1
ISPR2 ISPR3
I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1
I1_13 I0_13 I1_12 I0_12
High
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: TLI, TRAP and RESET events can interrupt a level 3 program.
These four registers contain the interrupt software priority of each interrupt vector. Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits* I1_1 and I0_1 bits ... I1_13 and I0_13 bits
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h) The RESET, TRAP and TLI vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. *Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).
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INTERRUPTS (Cont'd) Table 7. Dedicated Interrupt Instruction Set
Instruction H ALT IRET JRM JRNM POP CC RIM SIM TR AP W FI New Description Entering Halt mode Interrupt routine return Jump if I1:0=11 Jump if I1:0<>11 Pop CC from the Stack Enable interrupt (level 0 set) Disable interrupt (level 3 set) Software trap Wait for interrupt Function/Example Pop CC, A, X, PC I 1:0=11 ? I 1:0<>11 ? Mem => CC Load 10 in I1:0 of CC Load 11 in I1:0 of CC Software NMI I1 1 I1 H H I0 0 I0 N N Z Z C C
I1 1 1 1 1
H
I0 0 1 1 0
N
Z
C
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned inst ructions. In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never be used in an interrupt routine. Table 8. Interrupt Mapping
N Source Block RE SET TRAP ICP UART U SB WA K U P 1 WA K U P 2 TIM CARDDET 1) ES USP Not used Description Register Label Priority Order Highest Priority Exit from HALT yes Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFED h FFEAh-FFEBh
0 1 2 3 4 5 6 7 8
Reset Software Interrupt N/A FLASH Start programming NMI interrupt (TLI) ISO7816-3 UART Interrupt UIC USB Communication Interrupt U SBISTR External Interrupt Port C External Interrupt Port A TBU Timer Interrupt TBUS R 1) Smartcard Insertion/Removal Interrupt USC UR End suspend Interrupt U SBISTR
no
y es y es no yes Lowest Priority no
Note 1: This interrupt can be used to exit from USB suspend mode.
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8 POWER SAVING MODES
8.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency. From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. 8.2 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the "WFI" ST7 software instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is forced to 0, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 21.
N INTERRUP T
Figure 21. WAIT Mode Flow Chart
WFI INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
ON ON OFF CLEAR ED
N RESET
Y
Y
OSCILLATOR PERIPH. CLOCK CPU CLOCK I- BIT
ON ON ON SET
IF RESET 512 CPU CLOCK CYCLES DELAY
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 8.3 HALT MODE The HALT mode is the MCU lowest power consumption mode. The HALT mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. Note: The PLL must be disabled before a HALT inst ruction. When entering HALT mode, the I bit in the Condition Code Register is cleared. Thus, any of the external interrupts (ITi or USB end suspend mode), are allowed and if an interrupt occurs, the CPU clock becomes active. The MCU can exit HALT mode on reception of either an external interrupt on ITi, an end suspend mode interrupt coming from USB peripheral, or a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 512 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. Figure 22. HALT Mode Flow Chart
HALT INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I- BIT
OFF OFF OFF CLEARED
N RE SET N
EXTERNAL INTERRUPT*
Y
Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT ON ON ON SET
512 CPU CLOCK CYCLES DELAY
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
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9 I/O PORTS
9.1 Introduction The I/O ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: alternate signal input/output for the on-chip peripherals. external interrupt detection An I/O port is composed of up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 Functional description Each port is associated to 4 main registers: Data Register (DR) Data Direction Register (DDR) Option Register (OR) Pull Up Register (PU) Each I/O pin may be programmed using the corresponding register bits in DDR register: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. Table 9. I/O Pin Functions
D DR 0 1 M OD E Input Ou t p u t
terrupt request to the CPU. The interrupt sensitivity is given independently according to the description mentioned in the ITRFRE interrupt register. Each pin can independently generate an Interrupt request. Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as interrupt source, this is logically ORed. For this reason if one of the interrupt pins is tied low, it masks the other ones. Output Mode The pin is configured in output mode by setting the corresponding DDR register bit (see Table 7). In this mode, writing "0" or "1" to the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Note: In this mode, the interrupt function is disabled. Digital Alternate Function When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin's state is also digitally readable by addressing the DR register. Notes: 1. Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input. 2. When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0). Warning: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.
Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Note 1: All the inputs are triggered by a Schmitt trigger. Note 2: When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output. Interrupt function When an I/O is configured in Input with Interrupt, an event on this I/O can generate an external In-
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I/O PORTS (Cont'd) 9.3 I/O Port Implementation The hardware implementation on each I/O port depends on the settings in the DDR register and specific feature of the I/O port such as true open drain. 9.3.1 Port A Table 10. Port A Description
PORT A PA[5:0] PA6 *Reset State I/O Input without pull-up * without pull-up Output push-pull or open drain with software selectable pull-up -
Figure 23. PA0, PA1, PA2, PA3, PA4, PA5 Configuration
ALTERNATE 1 OUTPUT 0 ALTERNATE ENABLE VDD
P-BUFFER
DR LATCH ALTERNATE ENABLE DDR LATCH DDR SEL
DATA BUS
PULL-UP 1)
V DD
PAD
N-BUFFER DR SEL 1 DIODES ALTERNATE ENABLE VSS
ALTERNATE INPUT
0
CMOS SCHMITT TRIGGER
Note 1: selectable by PAPUCR register Figure 24. PA6 Configuration
VDD
DATA BUS
DR SEL PAD
CMOS SCHMITT TRIGGER DIODES
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I/O PORTS (Cont'd) 9.3.2 Ports B and D Table 11. Port B and D Description
PORTS B AND D PB[7:0] push-pull or open drain with software selectable pull-up PD[7:0] *Reset State = open drain Ou t p u t *
Figure 25. Port B and D Configuration
ALTERNATE ENABLE ALTERNATE 1 OUTPUT 0 `0' 0 DR LATCH ALTERNATE ENABLE OM LATCH PAD
DATA BUS
1
VDD
P-BUFFER
PULL-UP 1)
VDD
PULL_UP LATCH N-BUFFER DR SEL DIODES ALTERNATE ENABLE VSS
Note 1: selectable by PAPUCR register
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I/O PORTS (Cont'd) 9.3.3 Port C Table 12. Port C Description
PORT C PC[7:0] with pull-up Input
Figure 26. Port C Configuration
VDD PULL-UP
DR SEL PAD
VDD
ALTERNATE INPUT
DATA BUS
CMOS SCHMITT TRIGGER
DIODES
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I/O PORTS (Cont'd) 9.4 Register Description DATA REGISTERS (PxDR) Port A Data Register (PADR): 0011h Port B Data Register (PBDR): 0015h Port C Data Register (PCDR): 0018h Port D Data Register (PCDR): 0019h Read / Write Reset Value Port A: 0000 0000 (00h) Reset Value Port B: 0000 0000 (00h) Reset Value Port C: 0000 0000 (00h) Reset Value Port D: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
OPTION REGISTER (PxOR) Port x Option Register PxOR with x = A, B, or D Port A Option Register (PAOR): 0013h Port B Option Register (PBOR): 0016h Port D Option Register (PDOR): 001Ah Read / Write Reset Value: 0000 0000 (00h)
7 0
OM 7 OM6 OM 5 OM4 O M3 OM 2 OM1 O M0
Bits 7:0 = D[7:0] Data Register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken in account even if the pin is configured as an input. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (PADDR) Port A Data Direction Register (PADDR): 0012h Read/Write Reset Value Port A: 0000 0000 (00h)
7 DD7 DD6 DD5 D D4 DD3 DD2 DD1 0 DD0
Bits 7:0 = OM[7:0] Option register 8 bits. The OR register allows to distinguish in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. 0: Output open drain 1: Output push-pull PULL UP CONTROL REGISTER (PxPUCR) Port x Pull Up Register PxPUCR with x = A, B, or D Port A Pull up Register (PAPUCR): 0014h Port B Pull up Register (PBPUCR): 0017h Port D Pull up Register (PDPUCR): 001Bh Read / Write Reset Value: 0000 0000 (00h)
7 PU7 PU6 PU 5 PU4 PU3 PU2 PU1 0 P U0
Bits 7:0 = DD7-DD0 Data Direction Register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode
Bits 7:0 = PU[7:0] Pull up register 8 bits. The PU register is used to control the pull up. Each bit is set and cleared by software. 0: Pull up inactive 1: Pull up active
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I/O PORTS (Cont'd) Table 13. I/O Ports Register Map
Address (Hex.) 11 12 13 14 15 16 17 18 19 1A 1B Register Label PADR Reset Value PADDR Reset Value PAOR Reset Value PAPUCR Reset Value PBDR Reset Value PBOR Reset Value PBPUCR Reset Value PCDR Reset Value PDDR Reset Value PDOR Reset Value PDPUCR Reset Value 7 MS B 0 MS B 0 MS B 0 MS B 0 MS B 0 MS B 0 MS B 0 MS B 0 MS B 0 MS B 0 MS B 0 6 5 4 3 2 1 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
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10 MISCELLANEOUS REGISTERS
MISCELLANEOUS REGISTER 1 (MISCR1) Reset Value : 0000 0000 (00h) Read/Write
7 ITM 7 ITM 6 ITM 5 ITM 4 ITM 3 ITM 2 ITM 1 0 ITM 0
MISCELLANEOUS REGISTER 2 (MISCR2) Reset Value : 0000 0000 (00h) Read/Write
7 CRD IRM ITM 14 ITM 13 ITM 12 ITM 11 ITM 10 0 ITM 9
Writing the ITIFREC register enables or disables external interrupt on Port C. Each bit can be masked independantly. The ITMx bit masks the external interrupt on PC.x. Bits[7:0] = ITM [7:0] Interrupt Mask 0: external interrupt disabled 1: external interrupt enabled
Writing the ITIFREA register enables or disables external interrupt on port A. Bit 7 = Reserved. Bit 6 = CRDIRM CRD Insertion/Removal Interrupt Mask 0: CRDIR interrupt disabled 1: CRDIR interrupt enabled Bits [5:0] = ITM [14:9] Interrupt Mask Bit x of MISCR2 masks the external interrupt on port A.x. Bit x = ITM n Interrupt Mask n 0: external interrupt disabled on PA.x. 1: external interrupt enabled on PA.x.
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MISCELLANEOUS REGISTER 3 (MISCR3) Reset Value: 0000 0000 (00h) Read/Write
7 C TR CTR CTR CTR L1_A L0_A L1_C L0_C 0 -
MISCELLANEOUS REGISTER 4 (MISCR4) Reser Value : 0000 0000 (00h). Read/Write
7 PLL _ON CLK_ SE L 0 L OC K
This register is used to configure the edge and the level sensitivity of the Port A and Port C external interrupt. This means that all bits of a port must have the same sensitivity. If a write access modifies bits 7:4, it clears the pending interrupts. CTRL0_C, CTRL1_C : Sensitivity on port C CTRL0_A, CTRL1_A : Sensitivity on port A
CTR C TR L1_X L0_X 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
Bit 7 = Reserved. Bit 6 = PLL_ON PLL Activation 0: PLL disabled 1: PLL enabled Note: The PLL must be disabled before a HALT inst ruction. Bit 5 = CLK_SEL Clock Selection This bit is set and cleared by software. 0: CPU frequency = 4MHz 1: CPU frequency = 8MHz Bits 4:1 = Reserved. Bit 0 = LOCK PLL status bit 0: PLL not locked. fCPU = fOSC external clock frequency. 1: PLL locked. fCPU = 4 or 8 MHz depending on CLKSEL bit.
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MISCELLANEOUS REGISTERS (Cont'd) Table 14. Register Map and Reset Values
Address (Hex.) 001C 001D 001E 001Fh Register Label MISCR1 Reset Value MISCR2 Reset Value 7 ITM7 0 0 6 ITM6 0 0 5 ITM 5 0 ITM14 0 4 ITM4 0 ITM 1 3 0 3 ITM3 0 ITM12 0 0 0 2 ITM 2 0 ITM11 0 0 0 1 ITM1 0 ITM 1 0 0 0 0 0 ITM 0 0 ITM 9 0 0 LO CK 0
MISCR3 CTRL1_A CTRL0_A CTRL1_C CTRL0_C Reset Value 0 0 0 0 MISCR4 Reset Value 0 PLL_ON 0 RST_IN 0 CLK_SE 0L
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11 LEDs
Each of the four available LEDs can be selected using the LED_CTRL register. Two types of LEDs are supported: 3mA and 7mA. LED_CTRL REGISTER Reset Value: 0000 0000 (00h) Read / Write
7 LD3 LD2 LD1 LD0 LD3_I LD2_I LD1_I 0 LD0_I
Bits 3:0 = LDx_I Current selection on LDx 0: 3mA current on LDx pad 1: 7mA current on LDx pad
Bits 7:4 = LDx LED Enable 0: LED disabled 1: LED enabled
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12 ON-CHIP PERIPHERALS
12.1 WATCHDOG TIMER (WDG) 12.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 12.1.2 Main Features Programmable free-running downcounter (64 increments of 65536 CPU cycles) Programmable reset Reset (if watchdog activated) when the T6 bit reaches zero Hardware Watchdog selectable by option byte Watchdog Reset indicated by status flag 12.1.3 Functional Description The counter value stored in the CR register (bits T[6:0]), is decremented every 65,536 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. Figure 27. Watchdog Block Diagram
RESET
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is freerunning: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 15): The WDGA bit is set (watchdog enabled) The T6 bit is set to prevent generating an immediate reset The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 15.Watchdog Timing (fCPU = 8 MHz)
CR Register initial value Max Min FFh C0 h WDG timeout period (ms) 524.288 8.192
WATCHDOG CONTROL REGISTER (CR) WDG A T6 T5 T4 T3 T2 T1 T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER ÷65536
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WATCHDOG TIMER (Cont'd) 12.1.4 Software Watchdog Option If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 12.1.5 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. 12.1.6 Low Power Modes WAIT Instruction No effect on Watchdog. HALT Instruction Halt mode can be used when the watchdog is enabled. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 514 CPU clocks. In the case of the Software Watchdog option, if a reset is generated, the WDG is disabled (reset state). Recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode. Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as Input before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 12.1.7 Interrupts None. 12.1.8 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0111 1111 (7Fh)
7 WDG A T6 T5 T4 T3 T2 T1 0 T0
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
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12.2 TIME BASE UNIT (TBU) 12.2.1 Introduction The Timebase unit (TBU) can be used to generate periodic interrupts. 12.2.2 Main Features 8-bit upcounter Programmable prescaler Period between interrupts: max. 8.1ms (at 8 MHz fCPU ) Maskable interrupt 12.2.3 Functional Description The TBU operates as a free-running upcounter. When the TCEN bit in the TBUCSR register is set by software, counting starts at the current value of the TBUCV register. The TBUCV register is incremented at the clock rate output from the prescaler selected by programming the PR[2:0] bits in the TBUCSR register. When the counter rolls over from FFh to 00h, the OVF bit is set and an interrupt request is generated if ITE is set. The user can write a value at any time in the TBUCV register. 12.2.4 Programming Example In this example, timer is required to generate an interrupt after a delay of 1 ms. Assuming that fCPU is 8 MHz and a prescaler division factor of 256 will be programmed using the PR[2:0] bits in the TBUCSR register, 1 ms = 32 TBU timer ticks. In this case, the initial value to be loaded in the TBUCV must be (256-32) = 224 (E0h).
ld ld ld ld A, E0h TBUCV, A ; Initialize counter value A 1Fh ; TBUCSR, A ; Prescaler factor = 256, ; interrupt enable, ; TBU enable
Figure 28. TBU Block Diagram
1
MSB LSB
0
TBU 8-BIT UPCOUNTER (TBUCV REGISTER)
TBU PRESCALER
fCPU
0
0
OVF
ITE TCEN PR2 PR1 PR0
TBUCSR REGISTER INTERRUPT REQUEST
TBU
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TIMEBASE UNIT (Cont'd) 12.2.5 Low Power Modes Mode WAIT HALT Description No effect on TBU TBU halted.
TBU CONTROL/STATUS REGISTER (TBUCSR) Read/Write Reset Value: 0000 0000 (00h)
7 0 0 O VF ITE TCEN PR2 P R1 0 PR0
12.2.6 Interrupts Bits [7:6] = Reserved. Forced by hardware to 0.
Interrupt Event Counter Overflow Event Event Flag OVF Enable Control Bit I TE Exit from Wait Y es Exit from Halt No
Note: The OVF interrupt event is connected to an interrupt vector (see Interrupts chapter). It generates an interrupt if the ITE bit is set in the TBUCSR register and the I-bit in the CC register is reset (RIM instruction). 12.2.7 Register Description TBU COUNTER VALUE REGISTER (TBUCV) Read/Write Reset Value: 0000 0000 (00h)
7 CV 7 CV 6 CV 5 C V4 C V3 C V2 CV1 0 CV0
Bit 5 = OVF Overflow Flag This bit is set only by hardware, when the counter value rolls over from FFh to 00h. It is cleared by software reading the TBUCSR register. Writing to this bit does not change the bit value. 0: No overflow 1: Counter overflow Bit 4 = ITE Interrupt enabled. This bit is set and cleared by software. 0: Overflow interrupt disabled 1: Overflow interrupt enabled. An interrupt request is generated when OVF=1. Bit 3 = TCEN TBU Enable. This bit is set and cleared by software. 0: TBU counter is frozen and the prescaler is reset. 1: TBU counter and prescaler running. Bits 2:0 = PR[2:0] Prescaler Selection These bits are set and cleared by software to select the prescaling factor.
PR 2 PR1 PR0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Prescaler Division Factor 2 4 8 16 32 64 128 256
Bits 7:0 = CV[7:0] Counter Value This register contains the 8-bit counter value which can be read and written anytime by software. It is continuously incremented by hardware if TCEN=1.
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12.3 USB INTERFACE (USB) 12.3.1 Introduction The USB Interface implements a full-speed function interface between the USB and the ST7 microcontroller. It is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and USB Data Buffer interface. No external components are needed apart from the external pullup on USBDP for full speed recognition by the USB host. 12.3.2 Main Features USB Specification Version 1.1 Compliant Supports Full-Speed USB Protocol Seven Endpoints (including default endpoint) CRC generation/checking, NRZI encoding/ decoding and bit-stuffing USB Suspend/Resume operations On-Chip 3.3V Regulator On-Chip USB Transceiver 12.3.3 Functional Description The block diagram in Figure 29, gives an overview of the USB interface hardware. For general information on the USB, refer to the "Universal Serial Bus Specifications" document available at http//:www.usb.org. Serial Interface Engine The SIE (Serial Interface Engine) interfaces with the USB, via the transceiver. The SIE processes tokens, handles data transmission/reception, and handshaking as required by the USB standard. It also performs frame formatting, including CRC generation and checking. Endpoints The Endpoint registers indicate if the microcontroller is ready to transmit/receive, and how many bytes need to be transmitted. Data Transfer to/from USB Data Buffer Memory When a token for a valid Endpoint is recognized by the USB interface, the related data transfer takes place to/from the USB data buffer. At the end of the transaction, an interrupt is generated. Interrupts By reading the Interrupt Status register, application software can know which USB event has occurred.
Figure 29. USB Block Diagram 48 MHz
END POINT R EGISTERS CPU
USBD M U SBDP
Transceiver
BUFFER SIE INTERFAC E
Address, data busses and interrupts
USB V CC
3.3V Voltage Regulator
U SB R EGISTERS
U SB DATA BUFFER
USBGND
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USB INTERFACE (Cont'd) USB Endpoint RAM Buffers There are seven Endpoints including one bidirectional control Endpoint (Endpoint 0), five IN Endpoints (Endpoint 1, 2, 3, 4, 5) and one OUT endpoint (Endpoint 2). Figure 30. Endpoint Buffer Size
Endpoint 0 is 2 x 8 bytes in size, Endpoint 1, 3, 4, and Endpoint 5 are 8 bytes in size and Endpoint 2 is 2 x 64 bytes in size .
Endpoint 0 Buffer OUT Endpoint 0 Buffer IN Endpoint 1 Buffer IN Endpoint 2 Buffer OUT
8 Bytes 8 Bytes 8 Bytes 64 Bytes
Endpoint 2 Buffer IN
64 Bytes
Endpoint 3 Buffer IN Endpoint 4 Buffer IN Endpoint 5 Buffer IN
8 Bytes 8 Bytes 8 Bytes
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USB INTERFACE (Cont'd) 12.3.4 Register Description INTERRUPT STATUS REGISTER (USBISTR) Read/Write Reset Value: 0000 0000 (00h)
7 CTR 0 0 SOVR ERROR SUSP ESUSP RESET SOF
event is the SETUP token reception on the Control Endpoint (EP0). Bit 4 = ERR Error. This bit is set by hardware whenever one of the errors listed below has occurred: 0: No error detected 1: Timeout, CRC, bit stuffing, nonstandard framing or buffer overrun error detected Note: Refer to the ERR[2:0] bits in the USBSR register to determine the error type. Bit 3 = SUSP Suspend mode request. This bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the USB. The suspend request check is active immediately after each USB reset event and is disabled by hardware when suspend mode is forced (FSUSP bit in the USBCTLR register) until the end of resume sequence. Bit 2 = ESUSP End Suspend mode. This bit is set by hardware when, during suspend mode, activity is detected that wakes the USB interface up from suspend mode. This interrupt is serviced by a specific vector, in order to wake up the ST7 from HALT mode. 0: No End Suspend detected 1: End Suspend detected Bit 1 = RESET USB reset. This bit is set by hardware when the USB reset sequence is detected on the bus. 0: No USB reset signal detected 1: USB reset signal detected Note: The DADDR, EP0R, EP1RXR, EP1TXR, EP2RXR and EP2TXR registers are reset by a USB reset. Bit 0 = SOF Start of frame. This bit is set by hardware when a SOF token is received on the USB. 0: No SOF received 1: SOF received Note: To avoid spurious clearing of some bits, it is recommended to clear them using a load instruction where all bits which must not be altered are set, and all bits to be cleared are reset. Avoid readmodify-write instructions like AND, XOR...
These bits cannot be set by software. When an interrupt occurs these bits are set by hardware. Software must read them to determine the interrupt type and clear them after servicing. Note: The CTR bit (which is an OR of all the endpoint CTR flags) cannot be cleared directly, only by clearing the CTR flags in the Endpoint registers. Bit 7 = CTR Correct Transfer. This bit is set by hardware when a correct transfer operation is performed. This bit is an OR of all CTR flags (CTR0 in the EP0R register and CTR_RX and CTR_TX in the EPnRXR and EPnTXR registers). By looking in the USBSR register, the type of transfer can be determined from the PID[1:0] bits for Endpoint 0. For the other Endpoints, the Endpoint number on which the transfer was made is identified by the EP[1:0] bits and the type of transfer by the IN/OUT bit. 0: No Correct Transfer detected 1: Correct Transfer detected Note: A transfer where the device sent a NAK or STALL handshake is considered not correct (the host only sends ACK handshakes). A transfer is considered correct if there are no errors in the PID and CRC fields, if the DATA0/DATA1 PID is sent as expected, if there were no data overruns, bit stuffing or framing errors. Bit 6 = Reserved, forced by hardware to 0. Bit 5 = SOVR Setup Overrun. This bit is set by hardware when a correct Setup transfer operation is performed while the software is servicing an interrupt which occured on the same Endpoint (CTR0 bit in the EP0R register is still set when SETUP correct transfer occurs). 0: No SETUP overrun detected 1: SETUP overrun detected When this event occurs, the USBSR register is not updated because the only source of the SOVR
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USB INTERFACE (Cont'd) INTERRUPT MASK REGISTER (USBIMR) Read/Write Reset Value: 0000 0000 (00h)
7 CTRM 0 0 SOVR SUSP ESUSP RESET ERRM SOFM M M M M
Bits [5:4] = Reserved, forced by hardware to 0. Bit 3 = RESUME Resume. This bit is set by software to wake-up the Host when the ST7 is in suspend mode. 0: Resume signal not forced 1: Resume signal forced on the USB bus. Software should clear this bit after the appropriate delay. Bit 2 = PDWN Power down. This bit is set by software to turn off the 3.3V onchip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: Voltage regulator on 1: Voltage regulator off Note: After turning on the voltage regulator, software should allow at least 3 s for stabilisation of the power supply before using the USB interface. Bit 1 = FSUSP Force suspend mode. This bit is set by software to enter Suspend mode. The ST7 should also be put in Halt mode to reduce power consumption. 0: Suspend mode inactive 1: Suspend mode active When the hardware detects USB activity, it resets this bit (it can also be reset by software). Bit 0 = FRES Force reset. This bit is set by software to force a reset of the USB interface, just as if a RESET sequence came from the USB. 0: Reset not forced 1: USB interface reset forced. The USB is held in RESET state until software clears this bit, at which point a "USB-RESET" interrupt will be generated if enabled.
These bits are mask bits for all the interrupt condition bits included in the USBISTR register. Whenever one of the USBIMR bits is set, if the corresponding USBISTR bit is set, and the I- bit in the CC register is cleared, an interrupt request is generated. For an explanation of each bit, please refer to the description of the USBISTR register. CONTROL REGISTER (USBCTLR) Read/Write Reset value: 0000 0110 (06h)
7 USB_ RST RESU PDWN FSUSP ME 0
RSM
0
0
FRES
Bit 7 = RSM Resume Detected This bit shows when a resume sequence has started on the USB port, requesting the USB interface to wake-up from suspend state. It can be used to determine the cause of an ESUSP event. 0: No resume sequence detected on USB 1: Resume sequence detected on USB Bit 6 = USB_RST USB Reset detected. This bit shows that a reset sequence has started on the USB. It can be used to determine the cause of an ESUSP event (Reset sequence). 0: No reset sequence detected on USB 1: Reset sequence detected on USB
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USB INTERFACE (Cont'd) DEVICE ADDRESS REGISTER (DADDR) Read/Write Reset Value: 0000 0000 (00h)
7 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 0 ADD0
Bits 4:3 = Reserved, forced by hardware to 0. Bits 2:0 = EP[2:0] Endpoint number. These bits identify the endpoint which required attention. 000 = Endpoint 0 001 = Endpoint 1 010 = Endpoint 2 011 = Endpoint 3 100 = Endpoint 4 101 = Endpoint 5 ERROR STATUS REGISTER (ERRSR) Read only Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 ERR2 ERR1 0 ERR0
Bit 7 = Reserved, forced by hardware to 0. Bits 6:0 = ADD[6:0] Device address, 7 bits. Software must write into this register the address sent by the host during enumeration. Note: This register is also reset when a USB reset is received or forced through bit FRES in the USBCTLR register. USB STATUS REGISTER (USBSR) Read only Reset Value: 0000 0000 (00h)
7 PID1 PID0 IN/ OUT 0 0 EP2 EP1 0 EP0
Bits 7:3 = Reserved, forced by hardware to 0. Bits 2:0 = ERR[2:0] Error type. These bits identify the type of error which occurred.
E RR2 ERR1 E RR0 Meaning 0 0 0 No error 0 0 1 Bitstuffing error 0 1 0 CRC error EOP error (unexpected end of 0 1 1 packet or SE0 not followed by J-state) PID error (PID encoding error, 1 0 0 unexpected or unknown PID) Memory over / underrun (memory controller has not an1 0 1 swered in time to a memory data request) Other error (wrong packet, 1 1 1 timeout error)
Bits 7:6 = PID[1:0] Token PID bits 1 & 0 for Endpoint 0 Control. USB token PIDs are encoded in four bits. PID[1:0] correspond to the most significant bits of the PID field of the last token PID received by Endpoint 0. Note: The least significant PID bits have a fixed value of 01. When a CTR interrupt occurs on Endpoint 0 (see register USBISTR) the software should read the PID[1:0] bits to retrieve the PID name of the token received. The USB specification defines PID bits as:
PID 1 0 1 1 PID0 0 0 1 PID Name O UT IN S ET UP
Bit 5 = IN/OUT Last transaction direction for Endpoint 1, 2 , 3, 4 or 5. This bit is set by hardware when a CTR interrupt occurs on Endpoint 1, 2, 3, 4 or 5. 0: OUT transaction 1: IN transaction
Note: these bits are set by hardware when an error interrupt occurs and are reset automatically when the error bit (USBISTR bit 4) is cleared by software.
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USB INTERFACE (Cont'd) ENDPOINT 0 REGISTER (EP0R) Read/Write Reset value: 0000 0000(00h)
7 DTOG STAT_ STAT_ _TX TX1 TX0 0 DTOG STAT_ STAT_ _RX RX1 RX0
These bits contain the information about the endpoint status, which are listed below Table 16. Transmission Status Encoding
STAT_TX1 STAT_TX0 0 0 Meaning DISABLED: no function can be executed on this endpoint and messages related to this endpoint are ignored. STALL: the endpoint is stalled and all transmission requests result in a STALL handshake. NAK: the endpoint is NAKed and all transmission requests result in a NAK handshake. VALID: this endpoint is enabled (if an address match occurs, the USB interface handles the transaction).
CTR0
0
This register is used for controlling Endpoint 0. Bits 6:4 and bits 2:0 are also reset by a USB reset, either received from the USB or forced through the FRES bit in USBCTLR. Bit 7 = CTR0 Correct Transfer. This bit is set by hardware when a correct transfer operation is performed on Endpoint 0. This bit must be cleared after the corresponding interrupt has been serviced. 0: No CTR on Endpoint 0 1: Correct transfer on Endpoint 0 Bit 6 = DTOG_TX Data Toggle, for transmission transfers. It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next transmitted data packet. This bit is set by hardware on reception of a SETUP PID. DTOG_TX toggles only when the transmitter has received the ACK signal from the USB host. DTOG_TX and also DTOG_RX are normally updated by hardware, on receipt of a relevant PID. They can be also written by the user, both for testing purposes and to force a specific (DATA0 or DATA1) token. Bits 5:4 = STAT_TX [1:0] Status bits, for transmission transfers.
0
1
1
0
1
1
These bits are written by software. Hardware sets the STAT_TX and STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint; this allows software to prepare the next set of data to be transmitted. Bit 3 = Reserved, forced by hardware to 0. Bit 2 = DTOG_RX Data Toggle, for reception transfers. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. This bit is cleared by hardware in the first stage (Setup Stage) of a control transfer (SETUP transactions start always with DATA0 PID). The receiver toggles DTOG_RX only if it receives a correct data packet and the packet's data PID matches the receiver sequence bit.
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USB INTERFACE (Cont'd) Bits 1:0 = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the endpoint status, which are listed below: Table 17. Reception Status Encoding
STAT_RX1 STAT_RX0 0 0 Meaning DISABLED: no function can be executed on this endpoint and messages related to this endpoint are ignored. STALL: the endpoint is stalled and all reception requests result in a STALL handshake. NAK: the endpoint is NAKed and all reception requests result in a NAK handshake. VALID: this endpoint is enabled (if an address match occurs, the USB interface handles the transaction).
USB reset, either received from the USB or forced through the FRES bit in the USBCTLR register. Bits [7:4] = Reserved, forced by hardware to 0. Bit 3 = CTR_TX Correct Transmission Transfer. This bit is set by hardware when a correct transfer operation is performed in transmission. This bit must be cleared after the corresponding interrupt has been serviced. 0: No CTR in transmission on Endpoint 1, 2, 3, 4 or 5 1: Correct transfer in transmission on Endpoint 1, 2, 3, 4 or 5 Bit 2 = DTOG_TX Data Toggle, for transmission transfers. This bit contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. DTOG_TX toggles only when the transmitter has received the ACK signal from the USB host. DTOG_TX and DTOG_RX are normally updated by hardware, at the receipt of a relevant PID. They can be also written by the user, both for testing purposes and to force a specific (DATA0 or DATA1) token. Bits [1:0] = STAT_TX [1:0] Status bits, for transmission transfers. These bits contain the information about the endpoint status, which is listed below Table 18. Transmission Status Encoding
STAT_TX1 STAT_TX0 0 0 0 1 Meaning DISABLED: transmission transfers cannot be executed. STALL: the endpoint is stalled and all transmission requests result in a STALL handshake. NAK: the endpoint is naked and all transmission requests result in a NAK handshake. VALID: this endpoint is enabled for transmission.
0
1
1
0
1
1
These bits are written by software. Hardware sets the STAT_RX and STAT_TX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint, so the software has the time to examine the received data before acknowledging a new transaction. Note 1: If a SETUP transaction is received while the status is different from DISABLED, it is acknowleded and the two directional status bits are set to NAK by hardware. Note 2: When a STALL is answered by the USB device, the two directional status bits are set to STALL by hardware. E NDPOINT TRANSMISSION REGISTER (EP1TXR, EP2TXR, EP3TXR, EP4TXR, EP5TXR) Read/Write Reset value: 0000 0000 (00h)
7 0 CTR_T DTOG STAT_ STAT_ X _TX TX1 TX0
1 1
0 1
0
0
0
0
These bits are written by software, but hardware sets the STAT_TX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint. This allows software to prepare the next set of data to be transmitted.
This register is used for controlling Endpoint 1, 2, 3, 4 or 5 transmission. Bits 2:0 are also reset by a
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USB INTERFACE (Cont'd) E NDPOINT 2 RECEPTION (EP2RXR) Read/Write Reset value: 0000 0000 (00h)
7
REGISTER
The receiver toggles DTOG_RX only if it receives acorrect data packet and the packet's data PID matches the receiver sequence bit. Bits [1:0] = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the endpoint status, which is listed below: Table 19. Reception Status Encoding
STAT_RX1 STAT_RX0 0 0 0 1 Meaning DISABLED: reception transfers cannot be executed. STALL: the endpoint is stalled and all reception requests result in a STALL handshake. NAK: the endpoint is naked and all reception requests result in a NAK handshake. VALID: this endpoint is enabled for reception.
0 CTR_R DTOG STAT_ STAT_ X _RX RX1 RX0
0
0
0
0
This register is used for controlling Endpoint 2 reception. Bits 2:0 are also reset by a USB reset, either received from the USB or forced through the FRES bit in the USBCTLR register. Bits [7:4] = Reserved, forced by hardware to 0. Bit 3 = CTR_RX Reception Correct Transfer. This bit is set by hardware when a correct transfer operation is performed in reception. This bit must be cleared after that the corresponding interrupt has been serviced. Bit 2 = DTOG_RX Data Toggle, for reception transfers. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet.
1 1
0 1
These bits are written by software, but hardware sets the STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint, so the software has the time to examine the received data before acknowledging a new transaction.
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USB INTERFACE (Cont'd) RECEPTION COUNTER REGISTER (CNT0RXR) Read/Write Reset Value: 0000 0000 (00h)
7 0
RECEPTION COUNTER REGISTER (CNT2RXR) Read/Write Reset Value: 0000 0000 (00h)
7 0
0
0
0
0
C NT3 CNT2 CNT1 CN T 0
0
CNT6 CN T 5 CNT4 CNT3 CNT2 CN T C NT0
This register contains the allocated buffer size for endpoint 0 reception, setting the maximum number of bytes the related endpoint can receive with the next OUT or SETUP transaction. At the end of a reception, the value of this register is the max size decremented by the number of bytes received (to determine the number of bytes received, the software must subtract the content of this register from the allocated buffer size). TRANSMISSION COUNTER REGISTER (CNT0TXR, CNT1TXR, CNT3TXR, CNT4TXR, CNT5TXR) Read/Write Reset Value 0000 0000 (00h)
7 0
This register contains the allocated buffer size for endpoint 2 reception, setting the maximum number of bytes the related endpoint can receive with the next OUT transaction. At the end of a reception, the value of this register is the max size decremented by the number of bytes received (to determine the number of bytes received, the software must subtract the content of this register from the allocated buffer size). TRANSMISSION COUNTER REGISTER (CNT2TXR) Read/Write Reset Value 0000 0000 (00h)
7 0
0 0 0 0 0 C NT3 CNT2 CNT1 CN T 0
CNT6 CN T 5 CNT4 CNT3 CNT2 CNT1 C NT0
This register contains the number of bytes to be transmitted by Endpoint 0, 1, 3, 4 or 5 at the next IN token addressed to it.
This register contains the number of bytes to be transmitted by Endpoint 2 at the next IN token addressed to it.
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USB INTERFACE (Cont'd) Table 20. USB Register Map and Reset values
Address (Hex.)
20
Register Name
USBISTR Reset Value USBIMR Reset Value USBCTLR Reset Value DADDR Reset Value USBSR Reset Value EP0R Reset Value CNT0RXR Reset Value CNT0TXR Reset Value EP1TXR Reset Value CNT1TXR Reset Value EP2RXR Reset Value CNT2RXR Reset Value EP2TXR Reset Value CNT2TXR Reset Value EP3TXR Reset Value CNT3TXR Reset Value EP4TXR Reset Value CNT4TXR Reset Value EP5TXR Reset Value
7
CTR 0 CTRM 0 RSM 0 0 PID1 0 CTR0 0 0
6
0 0 0 0 USB_RST 0 ADD6 0 PID0 0 DTOG_TX 0 0
5
SOVR 0 SOVRM 0 0 ADD5 0 IN /OUT 0 STAT_TX1 0 0
4
ERR 0 ERRM 0 0 ADD4 0 0 STAT_TX0 0 0
3
SUSP 0 SUSPM 0 RESUME 0 ADD3 0 0 0 0 CNT3 0 CNT3 0 CTR_TX 0 CNT3 0 CTR_RX 0 CNT3 0 CTR_TX 0 CNT3 0 CTR_TX 0 CNT3 0 CTR_TX 0 CNT3 0 CTR_TX 0
2
ESUSP 0 ESUSPM 0 PDWN 1 ADD2 0 EP2 0 DTOG_RX 0 CNT2 0 CNT2 0 DTOG_TX 0 CNT2 0 DTOG_RX 0 CNT2 0 DTOG_TX 0 CNT2 0 DTOG_TX 0 CNT2 0 DTOG_TX 0 CNT2 0 DTOG_TX 0
1
RESET 0 RESETM 0 FSUSP 1 ADD1 0 EP1 0 STAT_RX1 0 CNT1 0 CNT1 0 STAT_TX1 0 CNT1 0 STAT_RX1 0 CNT1 0 STAT_TX1 0 CNT1 0 STAT_TX1 0 CNT1 0 STAT_TX1 0 CNT1 0 STAT_TX1 0
0
SOF 0 SOFM 0 FRES 0 ADD0 0 EP0 0 STAT_RX0 0 CNT0 0 CNT0 0 STAT_TX0 0 CNT0 0 STAT_RX0 0 CNT0 0 STAT_TX0 0 CNT0 0 STAT_TX0 0 CNT0 0 STAT_TX0 0 CNT0 0 STAT_TX0 0
21
22
23
24
25
26
27
0
0
0
0
28
0
0
0
0
29
0
0
0
0
2A
0
0 CNT6 0 0 CNT6 0 0
0 CNT5 0 0 CNT5 0 0
0 CNT4 0 0 CNT4 0 0
2B
0
2C
0
2D
0
2E
0
2F
0
0
0
0
30
0
0
0
0
31
0
0
0
0
32
0
0
0
0
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Address (Hex.)
33
Register Name
CNT5TXR
7
6
5
4
3
CNT3 0 0
2
CNT2 0 ERR2 0
1
CNT1 0 ERR1 0
0
CNT0 0 ERR0 0
0
0
0
0
34
ERRSR
0
0
0
0
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12.4 SMARTCARD INTERFACE (CRD) 12.4.1 Introduction The Smartcard Interface (CRD) provides all the required signals for acting as a smartcard interface device. The interface is electrically compatible with (and certifiable to) the ISO7816, EMV, GSM and WHQL standards. Both synchronous (e.g. memory cards) and asynchronous smartcards (e.g. microprocessor cards) are supported. The CRD generates the required voltages to be applied to the smartcard lines. The power-off sequence is managed by the CRD. Card insertion or card removal is detected by the CRD using a card presence switch connected to the external CRDDET pin. If a card is removed, the CRD automatically deactivates the smartcard using the ISO7816 deactivation sequence. An maskable interrupt is generated when a card is inserted or removed. Any malfunction is reported to the microcontroller via the Smartcard Interrupt Pending Register Figure 31. Smartcard Interface Block Diagram
CRDC4 4 MHz POWER-OFF LOGIC 11-BIT ETU COUNTER C RDCCR
CLK SEL CRD CRD CRD CRD CRD CRD C4 C8 IO CLK RST VCC
(CRDIPR) and Smartcard Status (CRDSR) Registers. 12.4.2 Main features Support for ISO 7816-3 standard Character mode 1 transmit buffer and 1 receive buffer 4-Mhz fixed card clock 11-bit etu (elementary time unit) counter 9-bit guardtime counter 24-bit general purpose waiting time counter Parity generation and checking Automatic character repetition on parity error detection in transmission mode Automatic retry on parity error detection in reception mode Card power-off deactivation sequence generation Manual mode for driving the card I/O directly for synchronous protocols 12.4.3 Functional Description Figure 31 gives an overview of the smartcard interface.
CRDC8 CRDV CC
C RDRST COMMUNICATIONS CONTROL
9-BIT GUARDTIME COUNTER 24-BIT WAITING TIME COUNTER PARITY GENERATION/CHECKING
CLO CK CO NTROL
CRDCLK
0
CRD INTERRUPT
UART SHIFT REGISTER
1 UART BIT
CRDIO
UART RECEIVE BUFFER
UART TRANSMIT BUFFER
CARD DETECTION LOGIC
CRDD ET
CR DRXB
CR DTXB
CARD INSERTION/REMOVAL INTERRUPT
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SMARTCARD INTERFACE (Cont'd) 12.4.3.1 Power Supply Management Smartcard Power Supply Selection The Smartcard interface consists of a power supply output on the CRDVCC pin and a set of card interface I/Os which are powered by the same rail. The card voltage (CRDVCC) is user programmable via the VCARD [1:0] bits in the CRDCR register (refer to the Smartcard Interface section). Four voltage values can be selected: 5V, 3 V, 1.8 V or 0V. Current Overload Detection and Card Removal For each voltage, when an overload current is detected (refer to section 12.4 on page 57), or when a card is removed, the CRDVCC power supply output is directly connected to ground. 12.4.3.2 I/O Driving Modes Smartcard I/Os are driven in two principal modes: UART mode (i.e. when the UART bit of the CRDCR register is set) Manual mode, driven directly by software using the Smartcard Contact register (i.e. when the UART bit of the CRDCR register is reset). Card power-on activation must driven by software. Card deactivation is handled automatically by the Power-off functional state machine hardware. 12.4.3.3 UART Mode Two registers are connected to the UART shift register: CRDTXB for transmission and CRDRXB for reception. They act as buffers to off-load the C P U. A parity checker and generator is coupled to the shifter. Character repetition and retry are supported. The UART is in reception mode by default and switches automatically to transmission mode when a byte is written in the buffer. Priority is given to transmission.
Elementary Time Unit Counter This 11-bit counter controls the working frequency of the UART. The operating frequency of the clock is the same as the card clock frequency (i.e. 4 MH z). A compensation mode can be activated via the COMP bit of the CRDETU1 register to allow a frequency granularity down to a half-etu. Note: The decimal value is limited to a half clock cycle. The bit duration is not fixed. It alternates between n clock cycles and n-1 clock cycles, where n is the value to be written in the CRDETU register. The character duration (10 bits) is also equal to 10*(n - ½) clock cycles This is precise enough to obtain the character duration specified by the ISO7816-3 standard. For example, if F=372 and D=32 (F being the clock rate conversion factor and D the baud rate adjustment), then etu =11.625 clock cycles. To achieve this clock rate, compensation mode must be activated and the etu duration must be programmed to 12 clock cycles. The result will be an average character duration of 11.5 clock cycles (for 10 bits). See Figure 32. Guardtime counter The guardtime counter is a 9-bit counter which manages the character frame. It controls the duration between two consecutive characters in transmission. It is incremented at the etu rate. No guardtime is inserted for the first character transmitted. The guardtime between the last byte received from the card and the next byte transmitted by the reader must be handled by software.
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Figure 32. Compensation Mode
Start bit Data bits
CRDIO
Parity bit
U A RT Working Clock
12cy 12cy 12cy 12cy 12cy 11cy 11cy 11cy 11cy 11cy
F=372 D= 32
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SMARTCARD INTERFACE (Cont'd) Waiting Time Counter The Waiting Time counter is a 24-bit counter used to generate a timeout signal. The elementary time unit counter acts as a prescaler to the Waiting Time counter which is incremented at the etu rate. The Waiting Time Counter can be used in both UART mode and Manual mode and acts in different ways depending on the selected mode. The CRDWT2, CRDWT1 and CRDWT0 are load registers only, the counter itself is not directly accessible. UART Mode The load conditions are either: A Start bit is detected while UART bit =1 and the WTEN bit =1. or A write access to the CRDWT2 register is performed while the UART bit = 1 and the WTEN bit = 0. In this case, the Waiting Time counter can be used as a general purpose timer. In UART mode, if the WTEN bit of the CRDCR register is set, the counter is loaded automatically on start bit detection. Software can change the time out value on-the-fly by writing to the CRDWT registers. For example, in T=1 mode, software must load the Block Waiting Time (BWT) time-out in the CRDWT registers before the start Figure 33. Waiting Time Counter Example
bit of the last transmitted character. Then, after transmission of this last character, signalled by the TXC interrupt, software must write the CWT value (Character Waiting Time) in the CRDWT registers. See example in Figure 33. Manual mode The load conditions are: A write access to the CRDWT2 register is performed while the UART bit = 0 and the WTEN bit =0 In Manual mode, if the WTEN bit of the CRDCR register is reset, the timer acts as a general purpose timer. The timer is loaded when a write access to the CRDWT2 register occurs. The timer starts when the WTEN bit = 1. 12.4.3.4 Interrupt generator The Smartcard Interface has 2 interrupt vectors: Card Insertion/Removal Interrupt CRD Interrupt The CRD interrupt is cleared when software reads the CRDIPR register. The Card Insertion/Removal is an external interrupt and is cleared automatically by hardware at the end of the interrupt service routine (IRET instruction). If an interrupt occurs while the CRDIPR register is being read, the corresponding bit will be set by hardware after the read access is done.
Firmware must program BWT
Firmware must program CWT
Reade r
C HA R0 C HA R1 C HA Rn
TXC Interrupt
Smartcard
CH AR0
BW T CWT
CH A R1
Start bit
Waiting Time Counter loaded on start bit
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SMARTCARD INTERFACE (Cont'd) 12.4.3.5 Card detection mechanism The CRDDET bit in the CRDCR Register indicates if the card presence detector (card switch) is open or closed when a card is inserted. When the CRDIRF bit of the CRDSR is set, it indicates that a card is present. To be able to power-on the smartcard, card presence is mandatory. Removing the smartcard will automatically start the ISO7816-3 card deactivation sequence (see Section 12.4.3.6). There is no hardware debouncing: The CRDIRF bit changes whenever the level on the CRDDET pin changes. The card switch can generate an interrupt which can be used to wake up the device from suspend mode and for software debouncing. Three different cases can occur: The microcontroller is in run mode, waiting for card insertion: Card insertion generates an interrupt and the Figure 34. Card detection block diagram
CRDIRF bit in the CRDSR register is set. Debouncing is managed by software. After the time required for debouncing, if the CRDIRF bit is set, the CRDVCC bit in the CRDCR register is set by software to apply the selected voltage to the CRDVCC pin The microcontroller is in suspend mode and a card is inserted: The ST7 is woken up by the interrupt. The card insertion is then handled in the same way as in the previous case. The card is removed: The CRDIRF bit is reset without hardware debouncing A Card Insertion/Removal interrupt is generated, (if enabled by the CRDIRM bit in the MISCR2 register) The CRDVCC bit is immediately reset by hardware, starting the card deactivation sequence.
SMARTCARD INTERFACE (CRD)
Pull-up
EDGE DETECTOR 1 0 CARD INSERTION/REMOVAL Interrupt Request
C RDDET
7
DET CNF
0
7
CRD IRF C RDSR
CRDCR
0
7
CR D IRM MISCR2
0
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SMARTCARD INTERFACE (Cont'd) 12.4.3.6 Card Deactivation Sequence This sequence can be activated in two different ways: Automatically as soon as the card presence detector detects a card removal (via the CRDIRF bit in the CRDSR register, refer to Section 12.4.3.5). By software, writing the CRDVCC bit in the CRDCR register, for example: If there is a smartcard current overflow (i.e. when the IOVFF bit in the CRDSR register is set) If the voltage is not within the specified range (i.e. when the VCARDOK bit in the CRDSR register is cleared), but software must clear the CRDVCC bit in the CRDCCR register to start the deactivation sequence. When the CRDVCC bit is cleared, this starts the deactivation sequence. CRDCLK, CRDIO, CRDC4 and CRDC8 pins are then deactivated as shown in Figure 35:
Figure 35. Card deactivation sequence
8 CPU Clk cycles
CRDVCC pin CRDRST pin CRDCLK pin CRDIO pin CRDC4 pin CRDC8 pin
Figure 36. Card voltage selection and power OFF block diagram
5V SMARTC ARD POWER SUPPLY BLO CK Card voltage selection
2
CRD VCC
2 2 7 CRD IRF IOVF
VCARD OK
0
7
VCARDVCARD
0 1 0
CRDS R
7 IOVM VCRD M 0
CRDC R
7
0 CRD VCC
C RDIE R
C RDCCR
7 IOVP V C R D P
0
POWER OFF BLO CK
CRDIPR
VCARDOK Interrupt Request IOVF Interrupt Request
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SMARTCARD INTERFACE (Cont'd) Figure 37. Power Off Timing Diagram
VCAR D[1:0]
00
11
00
Software Power-Off
11
Voltage Error
VCARDOK CR DVCC
Power-On
0.4V
Pow e r-On tOFF tOFF tON VCRDP Interrupt VCRDP Interrupt
tON
VCAR DOK
Note: Refer to the Electrical Characteristics section for the values of tON and tOFF. Figure 38. Card clock selection block diagram
OS C
POWER OFF BLOCK
PLL
DIV
4 MHz
IS OCLK
4 MHz 1 0 CRDC LK
CRD CCR CLK SEL CRD CLK
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SMARTCARD INTERFACE (Cont'd) 12.4.4 Register Description SMARTCARD INTERFACE CONTROL REGISTER (CRDCR) Read/Write Reset Value: 0000 0000 (00h)
7 CRD RST CRD DET VCAR D1 VCAR D0 U ART WT EN C REP 0 CO NV
Bit 2 = WTEN Waiting Time Counter enable. 0: Waiting Time counter stopped. While WTEN = 0, a write access to the CRDWT2 register loads the Waiting time counter with the load value held in the CRDWT0, CRDWT1 and CRDWT2 registers. 1: Start counter. In UART mode, the counter is automatically reloaded on start bit detection. Bit 1 = CREP Automatic character repetition in case of parity error. 0: In reception mode: no parity error signal indication (no retry on parity error). In transmission mode: no error signal processing. No retransmission of a refused character on parity error. 1: Automatic parity management: In transmission mode: up to 4 character repetitions on parity error. In reception mode: up to 4 retries are made on parity error. The PARF parity error flag is set by hardware if a parity error is detected. If the transmitted character is refused, the PARF bit is set (but the TXCF bit is reset) and an interrupt is generated if the PARM bit is set. Note: If CREP=1, the PARF flag is set at the 5th error (after 4 character repetitions or 4 retries). If CREP=0, the PARF bit is set after the first parity error. Bit 0 = CONV ISO convention selection. 0: Direct convention, the B0 bit (LSB) is sent first, a '1' is a level 1 on the Card I/O pin, the parity bit is added after the B7 bit. 1: Inverse convention, the B7 bit (MSB) is sent first, a '1' is a level 0 on Card I/O pin, the parity bit is added after the B0 bit. Note: To detect the convention used by any card, apply the following rule. If a card uses the convention selected by the reader, an RXC event occurs at answer to reset. Otherwise a parity error also occurs.
Bit 7 = CRDRST Smartcard Interface Reset. This bit is set by software to reset the UART of the Smartcard interface. 0: No Smartcard UART Reset 1: Smartcard UART Reset Bit 6 = CRDDET Card Presence Detector. This bit is set and cleared by software to configure the card presence detector switch. 0: Switch open if no card is present 1: Switch closed if no card is present Bits [5:4] = VCARD[1:0] Card voltage selection. These bits select the card voltage.
Bit 1 0 0 1 1 Bi t 0 0 1 0 1 Vc a r d 0V 1.8V 3V 5V
Bit 3 = UART UART Mode Selection. This bit is set and cleared by software to select UART or manual mode. 0: CRDIO pin is a copy of the CRDIO bit in the CRDCCR register (Manual mode). 1: CRDIO pin is the output of the smartcard UART (UART mode). Caution: Before switching from Manual mode to UART mode, software must set the CRDIO bit in the CRDCCR register.
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ST7SCR
SMARTCARD INTERFACE (Cont'd) SMARTCARD INTERFACE STATUS REGISTER (CRD SR) Read only (Read/Write on some bits) Reset Value: 1000 0000 (80h)
7 TXBE F CRD IRF VCARD OK TXC F RXC F 0 PAR F
Bit 3 = WTF Waiting Time Counter overflow Flag. - Read only 0: The WT Counter has not reached its maximum value 1: The WT Counter has reached its maximum value Bit 2 = TXCF Transmitted character Flag. - Read/Write This bit is set by hardware and cleared by software. 0: No character transmitted 1: A character has been transmitted Bit 1 = RXCF Received character Flag. - Read only This bit is set by hardware and cleared by hardware when the CRDRXB buffer is read. 0: No character received 1: A character has been received Bit 0 = PARF Parity Error Flag. - Read/Write This bit is set by hardware and cleared by software. 0: No parity error 1: Parity error Note: When a character is received, the RXCF bit is always set.When a character is received with a parity error, the PARF bit is also set.
IOVF
WTF
Bit 7 =TxBEF Transmit Buffer Empty Flag. - Read only 0: Transmit buffer is not empty 1: Transmit buffer is empty Bit 6 = CRDIRF Card Insertion/Removal Flag. - Read only 0: No card is present 1: A card is present Bit 5 = IOVF Card Overload Current Flag. - Read only 0: No card overload current 1: Card overload current Bit 4 = VCARDOK Card voltage status Flag. - Read only 0: The card voltage is not in the specified range 1: The card voltage is within the specified range
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ST7SCR
SMARTCARD INTERFACE (Cont'd) SMARTCARD CONTACT CONTROL REGISTER (CRD CCR ) Read/Write Reset Value: 00xx xx00 (xxh)
7 CLK SEL CRD C8 CRD C4 CRD IO CRD CLK CRD RST 0 CRD VCC
Bit 3 = CRDIO CRDIO pin control. This bit is active only if the UART bit in the CRDCR Register is reset. Reading this bit returns the value present on the CRDIO pin. If the UART bit is reset: Writing "0" forces a low level on the CRDIO pin Writing "1" forces the CRDIO pin to open drain Hi-Z. Bit 2 = CRDCLK CRDCLK pin control This bit is active only if the CLKSEL bit of the CRDCCR register is reset. Reading this bit returns the value present in the register (not the CRDCLK pin value). When the CLKSEL bit is reset: 0: Level 0 to be applied on CRDCLK pin. 1: Level 1 to be applied on CRDCLK pin. Note: To ensure that the clock stops at a given value, write the desired value in the CRDCLK bit prior to changing the CLKSEL bit from 1 to 0. Bit 1 = CRDRST CRDRST pin control. Reading this bit returns the value present on the CRDRST pin. Writing this bit outputs the bit value on the pin. Bit 0 = CRDVCC CRDVCC Pin Control. This bi |
