L6228
DMOS DRIVER FOR BIPOLAR STEPPER MOTOR
s s s s s s s s s s s s s
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V 2.8A OUTPUT PEAK CURRENT (1.4A RMS) RDS(ON) 0.73 TYP. VALUE @ Tj = 25C OPERATING FREQUENCY UP TO 100KHz NON DISSIPATIVE OVERCURRENT PROTECTION DUAL INDEPENDENT CONSTANT tOFF PWM CURRENT CONTROLLERS FAST/SLOW DECAY MODE SELECTION FAST DECAY QUASI-SYNCHRONOUS RECTIFICATION DECODING LOGIC FOR STEPPER MOTOR FULL AND HALF STEP DRIVE CROSS CONDUCTION PROTECTION THERMAL SHUTDOWN UNDER VOLTAGE LOCKOUT INTEGRATED FAST FREE WHEELING DIODES
PowerDIP24 (20+2+2)
PowerSO36
SO24 (20+2+2)
ORDERING NUMBERS: L6228N (PowerDIP24) L6228PD (PowerSO36) L6228D (SO24)
TYPICAL APPLICATIONS s BIPOL AR STEPPER MOTOR DESCRIPTION The L6228 is a DMOS Fully Integrated Stepper Motor Driver with non-dissipative Overcurrent Protection, realized in MultiPower-BCD technology, which comBLOCK DIAGRAM
bines isolated DMOS Power Transistors with CMOS and bipolar circuits on the same chip. The device includes all the circuitry needed to drive a two-phase bipolar stepper motor including: a dual DMOS Full Bridge, the constant off time PWM Current Controller that performs the chopping regulation and the Phase Sequence Generator, that generates the stepping sequence. Available in PowerDIP24 (20+2+2), PowerSO36 and SO24 (20+2+2) packages, the L6228 features a non-dissipative overcurrent protection on the high side Power MOSFETs and thermal shutdown.
VBOOT
VBOOT VBOOT VBOOT CHARGE PUMP OCDA OCDB OVER CURRENT DETECTION 10V 10V
VSA
VCP
OUT1A OUT2A
THERMAL PROTECTION EN CONTROL GATE LOGIC
SENSEA
HALF/FULL CLOCK RESET CW/CCW STEPPING SEQUENCE GENERATION ONE SHOT MONOSTABLE
PWM MASKING TIME + SENSE COMPARATOR BRIDGE A OVER CURRENT DETECTION GATE LOGIC BRIDGE B
VSB
VREFA RCA
VOLTAGE REGULATOR
OUT1B OUT2B SENSEB VREFB RCB
10V
5V
D01IN1225
September 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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L6228
ABSOLUTE MAXIMUM RATINGS
Symbol VS VOD Parameter Supply Voltage Differential Voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Bootstrap Peak Voltage Input and Enable Voltage Range Voltage Range at pins VREFA and VREFB Test conditions VSA = VSB = VS VSA = VSB = VS = 60V; VSENSEA = VSENSEB = GND VSA = VSB = VS Value 60 60 Unit V V
VBOOT VIN,VEN VREFA, VREFB
VS + 10 -0.3 to +7 -0.3 to +7 -0.3 to +7 -1 to +4
V V V V V A
VRCA, VRCB Voltage Range at pins RCA and RCB VSENSEA, VSENSEB IS(peak) Voltage Range at pins SENSEA and SENSEB Pulsed Supply Current (for each VS pin), internally limited by the overcurrent protection RMS Supply Current (for each VS pin) Storage and Operating Temperature Range VSA = VSB = VS; tPULSE < 1ms VSA = VSB = VS
3.55
IS Tstg, TOP
1.4 -40 to 150
A C
REC OMMENDED OPERATING CONDITIONS
Symbol VS VOD Parameter Supply Voltage Differential Voltage Between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Voltage Range at pins VREFA and VREFB Voltage Range at pins SENSEA and SENSEB RMS Output Current Operating Junction Temperature Switching Frequency -25 (pulsed tW < trr) (DC) Test Conditions VSA = VSB = VS VSA = VSB = VS; VSENSEA = VSENSEB -0.1 -6 -1 MIN 8 MAX 52 52 Unit V V
VREFA, VREFB VSENSEA, VSENSEB IO U T Tj fsw
5 6 1 1.4 +125 100
V V V A C KHz
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L 6228
THERMAL DATA
Symbol Rth-j-pins Rth-j-case Rth-j-amb1 Rth-j-amb1 Rth-j-amb1 Rth-j-amb2
(1) (2) (3) (4)
Description Maximum Thermal Resistance Junction-Pins Maximum Thermal Resistance Junction-Case Maximum Thermal Resistance Junction-Ambient
(1)
PowerDIP24 19 44 59
SO24 15 55 78
PowerSO36 2 36 16 63
Unit C/W C/W C/W C/W C/W C/W
Maximum Thermal Resistance Junction-Ambient (2) Maximum Thermal Resistance Junction-Ambient (3) Maximum Thermal Resistance Junction-Ambient (4)
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6cm2 (with a thickness of 35m). Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35m). Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35m), 16 via holes and a ground layer. Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board.
PIN CONNECTIONS (Top View)
GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
D99IN1084
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
GND N.C. N.C. VSB OUT2B N.C. VBOOT EN CONTROL HALF/FULL VREFB SENSEB RCB N.C. OUT1B N.C. N.C. GND
CLOCK CW/CCW SENSEA RCA OUT1A GND GND OUT1B RCB SENSEB VREFB HALF/FULL
1 2 3 4 5 6 7 8 9 10 11 12
D99IN1083
24 23 22 21 20 19 18 17 16 15 14 13
VREFA RESET VCP OUT2A VSA GND GND VSB OUT2B VBOOT EN CONTROL
N.C. N.C. VSA OUT2A N.C. VCP RESET VREFA CLOCK CW/CCW SENSEA RCA N.C. OUT1A N.C. N.C. GND
PowerDIP24/SO24
PowerSO36 (5)
(5)
The slug is internally connected to pins 1,18,19 and 36 (GND pins).
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L6228
PIN DESCRIPTION
PACKAGE SO24/ PowerDIP24 PIN # 1 2 PowerSO36 PIN # 10 11 CLOCK CW/CCW Logic Input Logic Input Step Clock input. The state machine makes one step on each rising edge. Selects the direction of the rotation. HIGH logic level sets clockwise direction, whereas LOW logic level sets counterclockwise direction. If not used, it has to be connected to GND or +5V. Bridge A Source Pin. This pin must be connected to Power Ground through a sensing power resistor. RC Network Pin. A parallel RC network connected between this pin and ground sets the Current Controller OFF-Time of the Bridge A. Bridge A Output 1. Ground terminals. In PowerDIP24 and SO24 packages, these pins are also used for heat dissipation toward the PCB. On PowerSO36 package the slug is connected to these pins. Bridge B Output 1. RC Network Pin. A parallel RC network connected between this pin and ground sets the Current Controller OFF-Time of the Bridge B. Bridge B Source Pin. This pin must be connected to Power Ground through a sensing power resistor. Bridge B Current Controller Reference Voltage. Do not leave this pin open or connected to GND. Step Mode Selector. HIGH logic level sets HALF STEP Mode, LOW logic level sets FULL STEP Mode. If not used, it has to be connected to GND or +5V. Decay Mode Selector. HIGH logic level sets SLOW DECAY Mode. LOW logic level sets FAST DECAY Mode. If not used, it has to be connected to GND or +5V. Chip Enable. LOW logic level switches OFF all Power MOSFETs of both Bridge A and Bridge B. This pin is also connected to the collector of the Overcurrent and Thermal Protection to implement over current protection. If not used, it has to be connected to +5V through a resistor. Bootstrap Voltage needed for driving the upper Power MOSFETs of both Bridge A and Bridge B. Bridge B Output 2. Bridge B Power Supply Voltage. It must be connected to the Supply Voltage together with pin VSA Bridge A Power Supply Voltage. It must be connected to the Supply Voltage together with pin VSB Name Type Function
3 4
12 13
SENSEA RCA
Power Supply RC Pin
5 6, 7, 18, 19
15 1, 18, 19, 36
OUT1A GND
Power Output GND
8 9
22 24
OUT1B RCB
Power Output RC Pin
10 11 12
25 26 27
SENSEB VREFB HALF/FULL
Power Supply Analog Input Logic Input
13
28
CONTROL
Logic Input
14
29
EN
Logic Input (6)
15 16 17 20
30 32 33 4
VBOOT OUT2B VSB VSA
Supply Voltage Power Output Power Supply Power Supply
4/26
L 6228
PIN DESCRIPTION (continued)
PACKAGE SO24/ PowerDIP24 PIN # 21 22 23 PowerSO36 PIN # 5 7 8 OUT2A VCP RESET Power Output Output Logic Input Bridge A Output 2. Charge Pump Oscillator Output. Reset Pin. LOW logic level restores the Home State (State 1) on the Phase Sequence Generator State Machine. If not used, it has to be connected to +5V. Bridge A Current Controller Reference Voltage. Do not leave this pin open or connected to GND. Name Type Function
24
9
VREFA
Analog Input
(6)
Also connected at the output drain of the Over current and Thermal protection MOSFET. Therefore, it has to be driven putting in series a resistor with a value in the range of 2.2K - 180K, recommended 100K.
ELECTRICAL CHARACTERISTICS (Tamb = 25C, Vs = 48V, unless otherwise specified)
Symbol Parameter Test Conditions Min 5.8 5 All Bridges OFF; Tj = -25C to 125C (7) Typ 6.3 5.5 5 Max 6.8 6 10 Unit V V mA C
VSth(ON) Turn-on Threshold VSth(OFF) Turn-off Threshold IS Quiescent Supply Current
Tj(OFF)
Thermal Shutdown Temperature
165
Output DMOS Transistors RDS(ON) High-Side + Low-Side Switch ON Tj = 25 C Resistance Tj =125 C (7) Leakage Current EN = Low; OUT = VS EN = Low; OUT = GND Source Drain Diodes V SD trr tfr Forward ON Voltage Reverse Recovery Time Forward Recovery Time ISD = 1.4A, EN = LOW If = 1.4A 1.15 300 200 1.3 V ns ns -0.3 1.47 2.35 1.69 2.70 2 mA mA
IDSS
Logic Inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW) VIL VIH IIL IIH Low level logic input voltage High level logic input voltage Low Level Logic Input Current High Level Logic Input Current GND Logic Input Voltage 7V Logic Input Voltage -0.3 2 -10 10 0.8 7 V V A A
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L6228
ELECTRICAL CHARACTERISTICS (continued) (Tamb = 25C, Vs = 48V, unless otherwise specified)
Symbol Vth(ON) Vth(OFF) Vth(HYS) Parameter Turn-on Input Threshold Turn-off Input Threshold Input Threshold Hysteresis 0.8 0.25 Test Conditions Min Typ 1.8 1.3 0.5 Max 2.0 Unit V V V
Switching Characteristics tD(ON)EN Enable to Output Turn-on Delay Time (8) tD(OFF)EN Enable to Output Turn-off Delay Time (8) tRISE tFALL tDCLK Output Rise Time (8) Output Fall Time (8) Clock to Output Delay Time (9) ILOAD =1.4A, Resistive Load ILOAD =1.4A, Resistive Load ILOAD =1.4A, Resistive Load ILOAD =1.4A, Resistive Load ILOAD =1.4A, Resistive Load 500 650 800 ns
500
800
1000
ns
40 40 2
250 250
ns ns s
tCLK(min)L Minimum Clock Time (10) tCLK(min) Minimum Clock Time (10)
H
1 1 100 1 1 1 1
s s KHz s s s s
fCLK tS(MIN) tH(MIN) tR(MIN)
Clock Frequency Minimum Set-up Time (11) Minimum Hold Time (11) Minimum Reset Time (11)
tRCLK(MIN Minimum Reset to Clock Delay ) Time (11) tD T f CP Dead Time Protection Charge Pump Frequency Tj = -25C to 125C (7) 0.5 1 0.6
s 1 MHz
PWM Comparator and Monostable IRCA, IRCB Source Current at pins RCA and RCB Voffset tPROP tBLANK tON(MIN) tOFF Offset Voltage on Sense Comparator Turn OFF Propagation Delay (12) Internal Blanking Time on SENSE pins Minimum On Time PWM Recirculation Time ROFF = 20K; COFF = 1nF ROFF = 100K; COFF = 1nF VRCA = VRCB = 2.5V VREFA, VREFB = 0.5V 3.5 5.5 mA
5 500 1 2.5 13 61 3
mV ns s s s s
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L 6228
ELECTRICAL CHARACTERISTICS (continued) (Tamb = 25C, Vs = 48V, unless otherwise specified)
Symbol IBIAS Parameter Input Bias Current at pins VREFA and VREFB Test Conditions Min Typ Max 10 Unit A
Over Current Protection ISOVER ROPDR Input Supply Overcurrent Protection Threshold Open Drain ON Resistance Tj = -25C to 125C (7) I = 4mA I = 4mA; CEN < 100pF I = 4mA; CEN < 100pF 2 2.8 40 200 100 3.55 60 A ns ns
tOCD(ON) OCD Turn-on Delay Time (13) tOCD(OFF) OCD Turn-off Delay Time (13)
(7) (8) (9) (10) (11) (12) (13)
Tested at 25C in a restricted range and guaranteed by characterization. See Fig. 1. See Fig. 2. See Fig. 3. See Fig. 4. Measured applying a voltage of 1V to pin SENSE and a voltage drop from 2V to 0V to pin VREF. See Fig. 5.
Figure 1. Switching Characteristic Definition
EN
Vth(ON) Vth(OFF) t IOUT 90%
10%
D01IN1316
t tFALL tD(OFF)EN tD(ON)EN tRISE
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L6228
Figure 2. Clock to Output Delay Time
CLOCK
Vth(ON)
t IOUT
D01IN1317
t tDCLK
Figure 3. Minimum Timing Definition; Clock Input
CLOCK Vth(ON) tCLK(MIN)L
Vth(OFF)
Vth(OFF) tCLK(MIN)H
D01IN1318
Figure 4. Minimum Timing Definition; Logic Inputs
CLOCK
Vth(ON)
LOGIC INPUTS
tS(MIN) RESET Vth(OFF) Vth(ON)
tH(MIN)
tR(MIN)
tRCLK(MIN)
D01IN1319
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L 6228
Figure 5. Overcurrent Detection Timing Definition
IOUT ISOVER
ON BRIDGE OFF VEN 90%
10% tOCD(ON) tOCD(OFF)
D02IN1399
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L6228
CIRCUIT DESCRIPTION POWER STAGES and CHARGE PUMP The L6228 integrates two independent Power MOS Full Bridges. Each Power MOS has an RDS(ON) = 0.73 (typical value @ 25C), with intrinsic fast freewheeling diode. Switching patterns are generated by the PWM Current Controller and the Phase Sequence Generator (see below). Cross conduction protection is achieved using a dead time (tDT = 1s typical value) between the switch off and switch on of two Power MOSFETSs in one leg of a bridge. Pins VSA and VSB MUST be connected together to the supply voltage VS. The device operates with a supply voltage in the range from 8V to 52V. It has to be noticed that the RDS(ON) increases of some percents when the supply voltage is in the range from 8V to 12V. Using N-Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The bootstrapped supply voltage VBOOT is obtained through an internal Oscillator and few external components to realize a charge pump circuit as shown in Figure 6. The oscillator output (VCP) is a square wave at 600KHz (typical) with 10V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table 1. Table 1. Charge Pump External Components Values
CBOOT CP RP D1 D2 220nF 10nF 100 1N4148 1N4148
REN OPEN COLLECTOR OUTPUT EN CEN ESD PROTECTION
D01IN1330
LOGIC INPUTS Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS and uC compatible logic inputs. The internal structure is shown in Fig. 7. Typical value for turn-on and turn-off thresholds are respectively Vth(ON)= 1.8V and Vth(OFF)= 1.3V. Pin EN (Enable) has identical input structure with the exception that the drain of the Overcurrent and thermal protection MOSFET is also connected to this pin. Due to this connection some care needs to be taken in driving this pin. The EN input may be driven in one of two configurations as shown in Fig. 8 or 9. If driven by an open drain (collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Fig. 8. If the driver is a standard Push-Pull structure the resistor REN and the capacitor CEN are connected as shown in Fig. 9. The resistor REN should be chosen in the range from 2.2K to 180K. Recommended values for REN and CEN are respectively 100K and 5.6nF. More information on selecting the values is found in the Overcurrent Protection section. Figure 7. Logic Inputs Internal Structure
5V
ESD PROTECTION
D01IN1329
Figure 8. EN Pin Open Collector Driving
5V 5V
Figure 6. Charge Pump Circuit
VS D1 D2 RP CP VCP VBOOT VSA VSB
D01IN1328
CBOOT
Figure 9. EN Pin Push-Pull Driving
5V REN
PUSH-PULL OUTPUT
EN CEN ESD PROTECTION
D01IN1331
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L 6228
PWM CURRENT CONTROL The L6228 includes a constant off time PWM current controller for each of the two bridges. The current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power MOS transistors and ground, as shown in Figure 10. As the current in the motor builds up the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor becomes greater than the voltage at the reference input (VREFA or VREFB) the sense comparator triggers the monostable switching the bridge off. The power MOS remain off for the time set by the monostable and the motor current recirculates as defined by the selected decay mode, described in the next section. When the monostable times out the bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective off time is the sum of the monostable time plus the dead time. Figure 10. PWM Current Controller Simplified Schematic
VSA (or B) TO GATE LOGIC BLANKING TIME MONOSTABLE 1s FROM THE LOW-SIDE GATE DRIVERS 2H MONOSTABLE SET 1H 2 PHASE STEPPER MOTOR
5mA
Q (0) (1)
S R
BLANKER
IOUT OUT2A(or B) DRIVERS + DEAD TIME DRIVERS + DEAD TIME OUT1A(or B)
5V 2.5V +
SENSE COMPARATOR + COMPARATOR OUTPUT RCA(or B) COFF ROFF -
2L
1L
VREFA(or B) RSENSE
SENSEA(or B)
D01IN1332
Figure 11 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the RC pin voltage and the status of the bridge. More details regarding the Synchronous Rectification and the output stage configuration are included in the next section. Immediately after the Power MOS turns on, a high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. The L6228 provides a 1s Blanking Time tBLANK that inhibits the comparator output so that this current spike cannot prematurely re-trigger the monostable.
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L6228
Figure 11. Output Current Regulation Waveforms
IOUT VREF RSENSE tOFF 1s tBLANK tON tOFF 1s tBLANK
VSENSE VREF 0
Slow Decay
c Fast De ay
Slow Decay
c Fast De ay
VRC 5V 2.5V
tRCRISE
tRCRISE
tRCFALL 1s tDT ON
SYNCHRONOUS OR QUASI SYNCHRONOUS RECTIFICATION
D01IN1334
tRCFALL 1s tDT
OFF
B
C
D
A
B
C
D
Figure 12 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be approximately calculated from the equations: tRCFALL = 0.6 · ROFF · COFF tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT where ROFF and COFF are the external component values and tDT is the internally generated Dead Time with: 20K ROFF 100K 0.47nF COFF 100nF tDT = 1s (typical value) Therefore: tOFF(MIN) = 6.6s tOFF(MAX) = 6ms These values allow a sufficient range of tOFF to implement the drive circuit for most motors. The capacitor value chosen for COFF also affects the Rise Time tRCRISE of the voltage at the pin RCOFF. The Rise Time tRCRISE will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. Therefore, the on time tON, which depends by motors and supply parameters, has to be bigger than tRCRISE for allowing a good current regulation by the PWM stage. Furthermore, the on time tON can not be smaller than the minimum on time tON(MIN).
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L 6228
t O N > t O N ( M I N ) = 2.5 s (typ. value) tO N > t R C R I S E tD T
tRCRISE = 600 · COFF Figure 13 shows the lower limit for the on time tON for having a good PWM current regulation capacity. It has to be said that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be smaller than tRCRISE - tDT. In this last case the device continues to work but the off time tOFF is not more constant. So, small COFF value gives more flexibility for the applications (allows smaller on time and, therefore, higher switching frequency), but, the smaller is the value for COFF, the more influential will be the noises on the circuit performance. Figure 12. tOFF versus COFF and ROFF
1 .10
4
R off = 100k
3
1 .10
R off = 47k R off = 20k
toff [s]
100
10
1 0.1 1 Coff [nF] 10 100
Figure 13. Area where tON can vary maintaining the PWM regulation.
100
ton(min) [us]
10
2.5s (typ. value)
1 0.1
1 Coff [nF]
10
100
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L6228
DECAY MODES The CONTROL input is used to select the behavior of the bridge during the off time. When the CONTROL pin is low, the Fast Decay mode is selected and both transistors in the bridge are switched off during the off time. When the CONTROL pin is high, the Slow Decay mode is selected and only the low side transistor of the bridge is switched off during the off time. Figure 14 shows the operation of the bridge in the Fast Decay mode. At the start of the off time, both of the power MOS are switched off and the current recirculates through the two opposite free wheeling diodes. The current decays with a high di/dt since the voltage across the coil is essentially the power supply voltage. After the dead time, the lower power MOS in parallel with the conducting diode is turned on in synchronous rectification mode. In applications where the motor current is low it is possible that the current can decay completely to zero during the off time. At this point if both of the power MOS were operating in the synchronous rectification mode it would then be possible for the current to build in the opposite direction. To prevent this only the lower power MOS is operated in synchronous rectification mode. This operation is called Quasi-Synchronous Rectification Mode. When the monostable times out, the power MOS are turned on again after some delay set by the dead time to prevent cross conduction. Figure 15 shows the operation of the bridge in the Slow Decay mode. At the start of the off time, the lower power MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the synchronous rectification mode. When the monostable times out, the lower power MOS is turned on again after some delay set by the dead time to prevent cross conduction. Figure 14. Fast Decay Mode Output Stage Configurations
A) ON TIME
D01IN1335
B) 1s DEAD TIME
C) QUASI-SYNCHRONOUS RECTIFICATION
D) 1s SLOW DECAY
Figure 15. Slow Decay Mode Output Stage Configurations
A) ON TIME
D01IN1336
B) 1s DEAD TIME
C) SYNCHRONOUS RECTIFICATION
D) 1s DEAD TIME
STEPPING SEQUENCE GENERATION The phase sequence generator is a state machine that provides the phase and enable inputs for the two bridges to drive a stepper motor in either full step or half step. Two full step modes are possible, the Normal Drive Mode where both phases are energized each step and the Wave Drive Mode where only one phase is energized at a
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L 6228
time. The drive mode is selected by the HALF/FULL input and the current state of the sequence generator as described below. A rising edge of the CLOCK input advances the state machine to the next state. The direction of rotation is set by the CW/CCW input. The RESET input resets the state machine to state. HALF STEP MODE A HIGH logic level on the HALF/FULL input selects Half Step Mode. Figure 16 shows the motor current waveforms and the state diagram for the Phase Sequencer Generator. At Start-Up or after a RESET the Phase Sequencer is at state 1. After each clock pulse the state changes following the sequence 1,2,3,4,5,6,7,8,... if CW/ CCW is high (Clockwise movement) or 1,8,7,6,5,4,3,2,... if CW/CCW is low (Counterclockwise movement). NORMAL DRIVE MODE (Full-step two-phase-on) A LOW level on the HALF/FULL input selects the Full Step mode. When the low level is applied when the state machine is at an ODD numbered state the Normal Drive Mode is selected. Figure Fig. 17 shows the motor current waveform state diagram for the state machine of the Phase Sequencer Generator. The Normal Drive Mode can easily be selected by holding the HALF/FULL input low and applying a RESET. AT start -up or after a RESET the State Machine is in state1. While the HALF/FULL input is kept low, state changes following the sequence 1,3,5,7,... if CW/CCW is high (Clockwise movement) or 1,7,5,3,... if CW/CCW is low (Counterclockwise movement). WAVE DRIVE MODE (Full-step one-phase-on) A LOW level on the pin HALF/FULL input selects the Full Step mode. When the low level is applied when the state machine is at an EVEN numbered state the Wave Drive Mode is selected. Figure 18 shows the motor current waveform and the state diagram for the state machine of the Phase Sequence Generator. To enter the Wave Drive Mode the state machine must be in an EVEN numbered state. The most direct method to select the Wave Drive Mode is to first apply a RESET, then while keeping the HALF/FULL input high apply one pulse to the clock input then take the HALF/FULL input low. This sequence first forces the state machine to sate 1. The clock pulse, with the HALF/FULL input high advances the state machine from state 1 to either state 2 or 8 depending on the CW/CCW input. Starting from this point, after each clock pulse (rising edge) will advance the state machine following the sequence 2,4,6,8,... if CW/CCW is high (Clockwise movement) or 8,6,4,2,... if CW/ CCW is low (Counterclockwise movement). Figure 16. Half Step Mode
IOUTA
3 4 5
2
6
IOUTB
1
8
7
Star t Up or Reset
CLOCK
D01IN1320
1
2
3
4
5
6
7
8
Figure 17. Normal Drive Mode
IOUTA
3 4 5
2
6
IOUTB
1
8
7
Star t Up or Reset
CLOCK
D01IN1322
1
3
5
7
1
3
5
7
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L6228
Figure 18. Wave Drive Mode
IOUTA
3 4 5
2
6
IOUTB
1
8
7
CLOCK
Star t Up or Reset
D01IN1321
2
4
6
8
2
4
6
8
NON-DISSIPATIVE OVERCURRENT PROTECTION The L6228 integrates an Overcurrent Detection Circuit (OCD) for full protection. This circuit provides protection against a short circuit to ground or between two phases of the bridge. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 19 shows a simplified schematic of the overcurrent detection circuit. To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current reaches the detection threshold (typically 2.8A) the OCD comparator signals a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3V typical) by an internal open drain MOS with a pull down capability of 4mA. By using an external R-C on the EN pin, the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. Figure 19. Overcurrent Protection Simplified Schematic
OUT1A POWER SENSE 1 cell
VSA
OUT2A HIGH SIDE DMOSs OF THE BRIDGE A
I1A POWER DMOS n cells
I2A POWER DMOS n cells POWER SENSE 1 cell
TO GATE LOGIC
C or LOGIC
+
OCD COMPARATOR I1A / n (I1A+I2A) / n I2A / n
VDD REN. CEN. EN RDS(ON) 40 TYP.
INTERNAL OPEN-DRAIN
IREF
OVER TEMPERATURE
OCD COMPARATOR
FROM THE BRIDGE B
D01IN1337
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L 6228
Figure 20 shows the Overcurrent Detection operation. The Disable Time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN values and its magnitude is reported in Figure 21. The Delay Time tDELAY before turning off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 22. CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable Delay Time and the REN value should be chosen according to the desired Disable Time. The resistor REN should be chosen in the range from 2.2K to 180K. Recommended values for REN and CEN are respectively 100K and 5.6nF that allow obtaining 200s Disable Time. Figure 20. Overcurrent Protection Waveforms
IOUT ISOVER
VEN VDD Vth(ON) Vth(OFF) VEN(LOW)
ON OCD OFF ON BRIDGE OFF tOCD(ON) tEN(FALL) tD(OFF)EN tOCD(OFF) tEN(RISE) tD(ON)EN
D02IN1400
tDELAY
tDISABLE
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L6228
Figure 21. tDISABLE versus C EN and REN (VDD = 5V).
3 1 .1 0
R EN = 2 20 k
R EN = 1 00 k
R EN = 47 k R EN = 33 k R EN = 10 k
tDISABLE [s]
100
10
1
1
10
100
C E N [n F ]
Figure 22. tDELAY versus CEN (VDD = 5V).
10
td elay [s]
1
0.1
1
10 Cen [nF]
100
THERMAL PROTECTION In addition to the Ovecurrent Protection, the L6228 integrates a Thermal Protection for preventing the device destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switch-off when the junction temperature reaches 165C (typ. value) with 15C hysteresis (typ. value).
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L 6228
APPLICATION INFORMATION A typical Bipolar Stepper Motor Driver application using L6228 is shown in Fig. 23. Typical component values for the application are shown in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near the L6228 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitor connected from the EN input to ground sets the shut down time when an over current is detected (see Overcurrent Protection). The two current sensing inputs (SENSEA and SENSEB) should be connected to the sensing resistors with a trace length as short as possible in the layout. The sense resistors should be non-inductive resistors to minimize the di/dt transients across the resistor. To increase noise immunity, unused logic pins (except EN) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground and Signal Ground separated on PCB. Table 2. Component Values for Typical Application
C1 C2 CA CB CBOOT CP CEN CREF 100F 100nF 1nF 1nF 220nF 10nF 5.6nF 68nF D1 D2 RA RB REN RP RSENSEA RSENSEB 1N4148 1N4148 39K 39K 100K 100 0.6 0.6
Figure 23. Typical Application
+ VS 8-52VDC VSA C1 C2 D1 CP VSB 20 17 VREFA VREFB CREF VCP 22 23 14 15 3 10 5 21 13 12 1 2 OUT1B OUT2B GND GND GND GND 8 16 18 19 6 7 9 RCB RB 4 RCA RA CB RESET EN REN ENABLE CEN CONTROL HALF/FULL CLOCK CW/CCW CA RESET
24 11
VREF = 0-1V
POWER GROUND -
RP D2
SIGNAL GROUND
CBOOT
VBOOT RSENSEA RSENSEB SENSEA SENSEB OUT1A OUT2A M
FAST/SLOW DECAY HALF/FULL CLOCK CW/CCW
D01IN1341
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L6228
Output Current Capability and IC Power Dissipation In Fig. 24, 25, 26 and 27 are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving a two-phase stepper motor, for different driving sequences: HALF STEP mode (Fig. 24) in which alternately one phase / two phases are energized. NORMAL DRIVE (FULL-STEP TWO PHASE ON) mode (Fig. 25) in which two phases are energized during each step. WAVE DRIVE (FULL-STEP ONE PHASE ON) mode (Fig. 26) in which only one phase is energized at each step. MICROSTEPPING mode (Fig. 27), in which the current follows a sine-wave profile, provided through the Vref pins. For a given output current and driving sequence the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125C maximum).
Figure 24. IC Power Dissipation versus Output Current in HALF STEP Mode.
HALF STEP
10 8
IA IB
I OUT
6
PD [W]
4 2 0
I OUT Test Conditions: Supply Voltage = 24V No PWM fSW = 30 kHz (slow decay)
0
0.25 0.5 0.75 1
1.25 1.5
I OUT [A]
Figure 25. IC Power Dissipation versus Output Current in NORMAL Mode (full step two phase on).
NORM AL DRIVE
10 8 6
IA
I OUT
IB I OUT
PD [W ]
4 2 0
Test Conditions: Supply Volt age =24 V
0 0.25 0.5 0.75 1 1.25 1.5
I OUT [A ]
No PWM f SW = 30 kHz (slow decay)
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L 6228
Figure 26. IC Power Dissipation versus Output Current in WAVE Mode (full step one phase on).
WAVE DRIVE
10 8
IA IB
I OUT
6
PD [W]
4 2 0
I OUT Test Conditions: Supply Voltage = 24V
0 0.25 0.5 0.75 1 1.25 1.5
No PW M fSW = 3 0 kHz (slow decay)
I OUT [A]
Figure 27. IC Power Dissipation versus Output Current in MICROSTEPPING Mode.
MICROSTEPPING
10 8 6
IA
I OUT
I OUT IB
PD [W]
4 2 0
0
0.25 0.5 0.75 1
1.25 1.5
I OUT [A]
Test Conditions: Supply Voltage = 24V f SW = 30 kHz (slow decay) f SW = 50 kHz (slow decay)
Thermal Management In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. Figures 28, 29 and 30 show the Junction-to-Ambient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO24 packages. For instance, using a PowerSO package with copper slug soldered on a 1.5mm copper thickness FR4 board with 6cm2 dissipating footprint (copper thickness of 35m), the Rth(j-amb) is about 35C/W. Fig. 31 shows mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15C/W.
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L6228
Figure 28. PowerSO36 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
C / W
43
38
33
W i th o u t G ro u nd La ye r
28
W i th Gro un d La ye r W i th Gro un d La ye r + 16 via H o le s
23
18
On-Board Copper Area
13 1 2 3 4 5 6 7 8 9 10 11 12 13
s q. cm
Figure 29. PowerDIP24 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
C / W
49 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 12
s q . cm
C o p p e r Are a is o n To p S i de C o p p e r Are a is o n Bo tto m S id e
O n-Board Copper Area
Figure 30. SO24 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
C / W 68 66 64 62 60 58 56 54 52 50 48 1 2 3 4 5 6 7 8 9 10 11 12 s q . cm
C o p p e r A re a is o n T o p S i d e
On-Board Copper Area
Figure 31. Mounting the PowerSO Package.
Slug soldered to PCB with dissipating area
Slug soldered to PCB with dissipating area plus ground layer
Slug soldered to PCB with dissipating area plus ground layer contacted through via holes
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L 6228
mm TYP. inch TYP.
DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 E4 G H h L N S
MIN. 0.10 0 0.22 0.23 15.80 9.40 13.90
MAX. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50
MIN. 0.004 0 0.008 0.009 0.622 0.370 0.547
MAX. 0.141 0.012 0.130 0.004 0.015 0.012 0.630 0.385 0.570
OUTLINE AND MECHANICAL DATA
0.65 11.05 10.90 5.80 2.90 0 15.50 0.80 11.10 0.429 2.90 6.20 0.228 3.20 0.114 0.10 0 15.90 0.610 1.10 1.10 0.031 10(max.) 8 (max.)
0.0256 0.435 0.437 0.114 0.244 0.126 0.004 0.626 0.043 0.043
PowerSO36
(1): "D" and "E1" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - Critical dimensions are "a3", "E" and "G".
N
N a2 A DETAIL A e3 H lead e A a1 E DETAIL A
c DETAIL B
D a3
36 19
slug BOTTOM VIEW E3
B E2 E1 DETAIL B
0.35 Gage Plane
D1
1
1
8
-C-
S h x 45 b
0.12
M
L
SEATING PLANE G C
AB
PSO36MEC
(COPLANARITY)
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L6228
DIM. MIN. A A1 A2 B B1 c D E e E1 e1 L M 3.180 6.350 0.410 1.400 0.200 31.62 7.620 0.380
mm TYP. MAX. 4.320 0.015 3.300 0.460 1.520 0.250 31.75 0.510 1.650 0.300 31.88 8.260 2.54 6.600 7.620 3.430 0.125 6.860 0.250 0.016 0.055 0.008 1.245 0.300 MIN.
inch TYP. MAX. 0.170
OUTLINE AND MECHANICAL DATA
0.130 0.018 0.060 0.010 1.250 0.020 0.065 0.012 1.255 0.325 0.100 0.260 0.300 0.270
0.135
Powerdip 24
0 min, 15 max.
E1
A2
A
L
A1
B
B1
e
e1
D
24
13 c
1
12 M
SDIP24L
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L 6228
mm DIM. M IN. A A1 B C D (1) E e H h L k ddd 10.0 0.25 0.40 2.35 0.10 0.33 0.23 15.20 7.40 1.27 10.65 0;75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 15.60 7.60 MIN. 0.093 0.004 0.013 0.009 0.598 0.291
inch TYP. MA X. 0.104 0.012 0.200 0.013 0.614 0.299 0.050 0.419 0.030 0.050 Weight: 0.60gr
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 0.10 0.004
(1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.
SO24
0070769 C
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L6228
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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