uPSD33xx
Turbo Series Fast 8032 MCU with Programmable Logic
PRELIMINARY DATA
FEATURES SUMMARY
FAST 8-BIT TURBO 8032 MCU, 40MHz Advanced core, 4-clocks per instruction 10 MIPs peak performance at 40MHz (5V) JTAG Debug and In-System Programming Branch Cache & 6 instruction Prefetch Queue Dual XDATA pointers with auto incr & decr Compatible with 3rd party 8051 tools D UAL FLASH MEMORIES WITH MEMORY MANAGEMENT Place either memory into 8032 program address space or data address space READ-while-WRITE operation for InApplication Programming and EEPROM emulation Single voltage program and erase 100K guaranteed erase cycles, 15-year retention C LOCK, RESET, AND SUPPLY MANAGEMENT SRAM is Battery Backup capable Flexible 8-level CPU clock divider register Normal, Idle, and Power Down Modes Power-on and Low Voltage reset supervisor Programmable Watchdog Timer PROGRAMMABLE LOGIC, GENERAL PURPOSE 16 macrocells Create shifters, state machines, chipselects, glue-logic to keypads, panels, LCDs, others C OMMUNICATION INTERFACES I2C Master/Slave controller, 833KHz SPI Master controller, 10MHz Two UARTs with independent baud rate IrDA protocol support up to 115K baud Up to 46 I/O, 5V tolerant on 3.3V uPSD33xxV
Figure 1. Packages
TQFP52 (T) 52-lead, Thin, Quad, Flat
TQFP80 (U) 80-lead, Thin, Quad, Flat
A/D CONVERTER Eight Channels, 10-bit resolution, 6s TIMERS AND INTERRUPTS Three 8032 standard 16-bit timers Programmable Counter Array (PCA), six 16-bit modules for PWM, CAPCOM, and timers 8/10/16-bit PWM operation 11 Interrupt sources with two external interrupt pins OPERATING VOLTAGE SOURCE (10%) 5V devices use both 5.0V and 3.3V sources 3.3V devices use only 3.3V source
January 2005
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
uPSD33xx
Table 1. Device Summary
Part Number uPSD3312D-40T6 uPSD3312DV-40T6 uPSD3333D-40T6 uPSD3333DV-40T6 uPSD3333D-40U6 uPSD3333DV-40U6 uPSD3334D-40U6 uPSD3334DV-40U6 uPSD3354D-40T6 uPSD3354DV-40T6 uPSD3354D-40U6 uPSD3354DV-40U6 1st Flash (bytes) 64K 64K 128K 128K 128K 128K 256K 256K 256K 256K 256K 256K 2nd Flash (bytes) 16K 16K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K SRAM (bytes) 2K 2K 8K 8K 8K 8K 8K 8K 32K 32K 32K 32K GPIO 37 37 37 37 46 46 46 46 37 37 46 46 8032 Bus No No No No Yes Yes Yes Yes No No Yes Yes VCC 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V VDD 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V Pkg. Temp.
TQFP52 40C to 85C TQFP52 40C to 85C TQFP52 40C to 85C TQFP52 40C to 85C TQFP80 40C to 85C TQFP80 40C to 85C TQFP80 40C to 85C TQFP80 40C to 85C TQFP52 40C to 85C TQFP52 40C to 85C TQFP80 40C to 85C TQFP80 40C to 85C
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TABLE OF CONTENTS
FEATUR ES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 uPSD33xx HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Internal Memory (MCU Module, Standard 8032 Memory: DATA, IDATA, SFR) . . . . . . . . . . . . 16 External Memory (PSD Module: Program memory, Data memory). . . . . . . . . . . . . . . . . . . . . . 16 8032 MCU CORE PERFORMANCE ENHANCEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pre-Fetch Queue (PFQ) and Branch Cache (BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PFQ Example, Multi-cycle Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 A ggregate Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MCU MODULE DISCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8032 MCU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 D ata Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program Counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 A ccumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 B Register (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 General Purpose Registers (R0 - R7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPECIAL FUNCTION REGISTERS (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8032 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 R egister Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 D irect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 R egister Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 External Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 External Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 R elative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 A bsolute Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Long Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 B it Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 uPSD33xx INSTRUCTION SET SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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DUAL DATA POINTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 D ata Pointer Control Register, DPTC (85h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 D ata Pointer Mode Register, DPTM (86h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DEB UG UNIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Individual Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 MCU CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 MCU_C LK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PERIPH _CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 R educed Frequency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 OSCILLATOR AND EXTERNAL COMPONENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I/O PORTS of MCU MODULE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 MCU Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 B us Read Cycles (PSEN or RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 B us Write Cycles (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 C ontrolling the PFQ and BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SUPERVISORY FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 External Reset Input Pin, RESET_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Low VCC Voltage Detect, LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Power-up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 JTAG Debug Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 W atchdog Timer, WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 STANDARD 8032 TIMER/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Standard Timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C lock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SFR, TCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SFR, TMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tim er 0 and Timer 1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tim er 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 . . . . 69 . . . . 71 . . . . 71 . . . . 71 . . . . 74
SERIAL UART INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 U ART Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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Serial Port Control Registers . . . . . . . . . . . . . . . . U ART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . More About UART Mode 0 . . . . . . . . . . . . . . . . . . More About UART Mode 1 . . . . . . . . . . . . . . . . . . More About UART Modes 2 and 3 . . . . . . . . . . . . . . ... . . ... . . ... . . ... . . ... . . .. . . .. . . .. . . .. . . .. . . ... . . ... . . ... . . ... . . ... . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . . . 82 . . . . 84 . . . . 85 . . . . 87 . . . . 89
IrDA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Pulse Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I2C Interface Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 C ommunication Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 B us Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 C lock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 General Call Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Serial I/O Engine (SIOE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 I2C Interface Control Register (S1CON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 I2C Interface Status Register (S1STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 I2C Data Shift Register (S1DAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I2C Address Register (S1ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I2C START Sample Setting (S1SETUP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 I2C Operating Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SPI (SYNCHRONOUS PERIPHERAL INTERFACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SPI Bus Features and Communication Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 B us-Level Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SPI SFR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 D ynamic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Port 1 ADC Channel Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 PROGRAMMABLE COUNTER ARRAY (PCA) WITH PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PCA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PCA Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Operation of TCM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 C apture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Tim er Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Toggle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 PW M Mode - (X8), Fixed Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 PW M Mode - (X8), Programmable Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 PW M Mode - Fixed Frequency, 16-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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PW M Mode - Fixed Frequency, 10-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . W riting to Capture/Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . C ontrol Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . .. . . . 129 . . . 129 . . . 129 . . . 132
PSD MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 PSD Module Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 R untime Control Register Definitions (csiop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 PSD Module Detailed Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 PSD Module Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 PAC KAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 PAR T NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
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SUMMARY DESCRIPTION
The Turbo uPSD33xx Series combines a powerful 8051-based microcontroller with a flexible memory structure, programmable logic, and a rich peripheral mix to form an ideal embedded controller. At its core is a fast 4-cycle 8032 MCU with a 6-byte instruction prefetch queue (PFQ) and a 4-entry fully associative branching cache (BC) to maximize MCU performance, enabling loops of code in smaller localities to execute extremely fast. Code development is easily managed without a hardware In-Circuit Emulator by using the serial JTAG debug interface. JTAG is also used for InSystem Programming (ISP) in as little as 10 seconds, perfect for manufacturing and lab development. The 8032 core is coupled to Programmable System Device (PSD) architecture to optimize the 8032 memory structure, offering two independent Figure 2. Block Diagram
uPSD33xx
(3) 16-bit Timer/ Counters (2) External Interrupts Turbo 8032 Core PFQ & BC 1st Flash Memory: 64K, 128K, or 256K Bytes
banks of Flash memory that can be placed at virtually any address within 8032 program or data address space, and easily paged beyond 64K bytes using on-chip programmable decode logic. Dual Flash memory banks provide a robust solution for remote product updates in the field through In-Application Programming (IAP). Dual Flash banks also support EEPROM emulation, eliminating the need for external EEPROM chips. General purpose programmable logic (PLD) is included to build an endless variety of glue-logic, saving external logic devices. The PLD is configured using the software development tool, PSDsoft Express, available from the web at www.st.com/psm, at no charge. The uPSD33xx also includes supervisor functions such as a programmable watchdog timer and low-voltage reset.
Programmable Decode and Page Logic
P3.0:7
I2C
2nd Flash Memory: 16K or 32K Bytes SRAM: 2K, 8K, or 32K Bytes
UART0 (8) GPIO, Port A (80-pin only) (8) GPIO, Port 3 General Purpose Programmable Logic, 16 Macrocells (8) GPIO, Port B (2) GPIO, Port D (4) GPIO, Port C
PA0:7 PB0:7 PD1:2
(8) 10-bit ADC Optional IrDA Encoder/Decoder
SYSTEM BUS
P1.0:7
(8) GPIO, Port 1
PC0:7
JTAG ICE and ISP 8032 Address/Data/Control Bus (80-pin device only) Supervisor: Watchdog and Low-Voltage Reset VCC, VDD, GND, Reset, Crystal In
UART1
SPI 16-bit PCA (6) PWM, CAPCOM, TIMER
MCU Bus
P4.0:7
(8) GPIO, Port 4
Dedicated Pins
AI08875
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PIN DESCRIPTIONS
Figure 3. TQFP52 Connections
40 P1.6/SPITXD(2)/ADC6 41 P1.7/SPISEL(2)/ADC7
47 AVCC/VREF(3)
44 RESET_IN
45 GND
46 PB5
43 PB6
42 PB7
52 PB0
51 PB1
50 PB2
49 PB3
48 PB4
PD1/CLKIN 1 PC7 2 JTAG TDO 3 JTAG TDI 4 DEBUG 5 3.3V VCC 6 PC4/TERR 7 VDD(1) 8 GND 9 PC3/TSTAT 10 PC2/VSTBY 11 JTAG TCK 12 JTAG TMS 13
39 P1.5/SPIRXD(2)/ADC5 38 P1.4/SPICLK(2)/ADC4 37 P1.3/TXD1(IrDA)(2)/ADC3 36 P1.2/RXD1(IrDA)(2)/ADC2 35 P1.1/T2X(2)/ADC1 34 P1.0/T2(2)/ADC0 33 VDD(1) 32 XTAL2 31 XTAL1 30 P3.7/SCL 29 P3.6/SDA 28 P3.5/C1 27 P3.4/C0
SPISEL(2)/PCACLK1/P4.7 14
SPITXD(2)/TCM5/P4.6 15
SPIRXD(2)/TCM4/P4.5 16
SPICLK(2)/TCM3/P4.4 17
TXD1(IrDA)(2)/PCACLK0/P4.3 18
GND 19
20
T2X(2)/TCM1/P4.1 21
T2(2)/TCM0/P4.0 22
RXD0/P3.0 23
TXD0/P3.1 24
EXTINT0/TG0/P3.2 25
RXD1(IrDA)(2)/TCM2/P4.2
EXTINT1/TG1/P3.3 26
AI07822
Note: 1. For 5V applications, VDD must be connected to a 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1. 3. VREF and 3.3V AV CC are shared in the 52-pin package only. ADC channels must use AVCC as VREF for the 52-pin package.
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Figure 4. TQFP80 Connections
61 P1.6/SPITXD(2)/ADC6 64 P1.7/SPISEL(2)/ADC7 79 P3.2/EXINT0/TG0
75 P3.0/RXD0
77 P3.1/TXD0
68 RESET_IN
63 PSEN
72 AVCC
70 VREF
69 GND
80 PB0
78 PB1
76 PB2
74 PB3
73 PB4
71 PB5
67 PB6
66 PB7
62 WR
65 RD
PD2/CSI 1 P3.3/TG1/EXINT1 2 PD1/CLKIN 3 ALE 4 PC7 5 JTAG TDO 6 JTAG TDI 7 DEBUG 8 PC4/TERR 9 3.3V VCC 10 NC 11 VDD(1) 12 GND 13 PC3/TSTAT 14 PC2/VSTBY 15 JTAG TCK 16 NC 17 SPISEL(2)/PCACLK1/P4.7 18 SPITXD(2)/TCM5/P4.6 19 JTAG TMS 20
60 P1.5/SPIRXD(2)/ADC5 59 P1.4/SPICLK(2)/ADC4 58 P1.3/TXD1(IrDA)(2)/ADC3 57 MCU A11 56 P1.2/RXD1(IrDA)(2)/ADC2 55 MCU A10 54 P1.1/T2X(2)/ADC1 53 MCU A9 52 P1.0/T2(2)/ADC0 51 MCU A8 50 VDD(1) 49 XTAL2 48 XTAL1 47 MCU AD7 46 P3.7/SCL 45 MCU AD6 44 P3.6/SDA 43 MCU AD5 42 P3.5/C1 41 MCU AD4
PA7 21
PA6 22
SPIRXD(2)/TCM4/P4.5 23
PA5 24
SPICLK(2)/TCM3/P4.4 25
PA4 26
TXD1(IrDA)(2)/PCACLK0/P4.3 27
PA3 28
GND 29
RXD1(IrDA)(2)/TCM2/P4.2 30
T2X(2)/TCM1/P4.1 31
PA2 32
T2(2)/TCM0/P4.0 33
PA1 34
PA0 35
MCU AD0 36
MCU AD1 37
MCU AD2 38
MCU AD3 39
P3.4/C0 40
AI07823
Note: NC = Not Connected Note: 1. For 5V applications, VDD must be connected to a 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1.
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Table 2. Pin Definitions
Port Pin MCUAD0 MCUAD1 MCUAD2 MCUAD3 MCUAD4 MCUAD5 MCUAD6 MCUAD7 MCUA8 MCUA9 MCUA10 MCUA11 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 Signal Name A D0 A D1 A D2 A D3 A D4 A D5 A D6 A D7 A8 A9 A10 A11 T2 ADC0 T2X ADC1 Rx D1 ADC2 TXD1 ADC3 SPICLK ADC4 SPIRxD ADC6 SPITXD ADC6 SPISEL A D C7 RxD0 TXD0 EXINT0 TGO INT1 C0 80-Pin 52-Pin In/Out No. No.(1) 36 37 38 39 41 43 45 47 51 53 55 57 52 54 56 58 59 60 61 64 75 77 79 N/ A N/ A N/ A N/ A N/ A N/ A N/ A N/ A N/ A N/ A N/ A N/ A 34 35 36 37 38 39 40 41 23 24 25 I/O I/O I/O I/O I/O I/O I/O I/O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Func tion Basic External Bus Multiplexed Address/ Data bus A0/D0 Multiplexed Address/ Data bus A1/D1 Multiplexed Address/ Data bus A2/D2 Multiplexed Address/ Data bus A3/D3 Multiplexed Address/ Data bus A4/D4 Multiplexed Address/ Data bus A5/D5 Multiplexed Address/ Data bus A6/D6 Multiplexed Address/ Data bus A7/D7 External Bus, Addr A8 External Bus, Addr A9 External Bus, Addr A10 External Bus, Addr A11 General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin Timer 2 Count input (T2) Timer 2 Trigger input (T2X) UART1 or IrDA Receive (RxD1) UART or IrDA Transmit (TxD1) SPI Clock Out (SPICLK) SPI Receive (SPIRxD) SPI Transmit (SPITxD) SPI Slave Select (SPISEL) UART0 Receive (RxD0) UART0 Transmit (TxD0) Interrupt 0 input (EXTINT0)/Timer 0 gate control (TG0) Interrupt 1 input (EXTINT1)/Timer 1 gate control (TG1) Counter 0 input (C0) ADC Channel input (ADC0) ADC Channel input (ADC1) ADC Channel input (ADC2) ADC Channel input (ADC3) ADC Channel input (ADC4) ADC Channel input (ADC5) ADC Channel input (ADC6) ADC Channel input (ADC7) 0 1 2 3 4 5 6 7 Alternate 1 Alternate 2
P3.3 P3.4
2 40
26 27
I/O I/O
General I/O port pin General I/O port pin
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Port Pin P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 VREF RD WR PSEN ALE RESET_IN XTAL1 XTAL2 DEBUG PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Signal Name C1 SDA S CL T2 TC M0 T2X TCM1 RX D1 TCM2 TXD1 PCACLK0 SPICLK TCM3 SPIRXD TCM4 SPITXD SPISEL PCACLK1 80-Pin 52-Pin In/Out No. No.(1) Basic 42 28 I/O General I/O port pin 44 46 33 31 30 27 25 23 19 18 70 65 62 63 4 68 48 49 8 35 34 32 28 26 24 22 21 29 30 22 21 20 18 17 16 15 14 N/A N/A N/A N/A N/A 44 31 32 5 N/ A N/ A N/ A N/ A N/ A N/ A N/ A N/ A I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O O O O I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin Reference Voltage input for ADC READ Signal, external bus WRITE Signal, external bus PSEN Signal, external bus Address Latch signal, external bus Active low reset input Oscillator input pin for system clock Oscillator output pin for system clock I/O to the MCU Debug Unit General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin Func tion Alternate 1 Counter 1 input (C1) I2C Bus serial data (I2CSDA) I2C Bus clock (I2CSCL) Program Counter Array0 PCA0-TCM0 PCA0-TCM1 PCA0-TCM2 PCACLK0 Program Counter Array1 PCA1-TCM3 PCA1-TCM4 PCA1-TCM5 PCACLK1 Alternate 2
Timer 2 Count input (T2) Timer 2 Trigger input (T2X) UART1 or IrDA Receive (RxD1) UART1 or IrDA Transmit (TxD1) SPI Clock Out (SPICLK) SPI Receive (SPIRxD) SPI Transmit (SPITxD) SPI Slave Select (SPISEL)
All Port A pins support: 1. PLD Macro-cell outputs, or 2. PLD inputs, or 3. Latched Address Out (A0-A7), or 4. Peripheral I/O Mode
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Port Pin PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 JTAGTMS JTAGTCK PC2 PC3 PC4 JTAGTDI JTAGTDO PC7 PD1 CLKIN Signal Name 80-Pin 52-Pin In/Out No. No.(1) 80 78 76 74 73 71 67 66 20 16 15 14 9 7 6 5 3 52 51 50 49 48 46 43 42 13 12 11 10 7 4 3 2 1 I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I O I/O I/O Func tion Basic General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin JTAG pin (TMS) JTAG pin (TCK) General I/O port pin General I/O port pin General I/O port pin JTAG pin (TDI) JTAG pin (TDO) General I/O port pin General I/O port pin PLD, Macrocell output, or PLD input 1. PLD I/O 2. Clock input to PLD and APD 1. PLD I/O 2. Chip select ot PSD Module SRAM Standby voltage input (VSTBY) Optional JTAG Status (TSTAT) Optional JTAG Status (TERR) Alternate 1 Alternate 2 All Port B pins support: 1. PLD Macro-cell outputs, or 2. PLD inputs, or 3. Latched Address Out (A0-A7)
TMS TCK VSTBY TSTAT TE R R TDI TDO
PLD Macrocell output, or PLD input PLD, Macrocell output, or PLD input PLD, Macrocell output, or PLD input
PD2 3.3V-VCC AVCC VDD 3.3V or 5V VDD 3.3V or 5V GND GND GND NC NC
CSI
1 10 72 12
N/ A 6 47 8
I/O
General I/O port pin VCC - MCU Module Analog VCC Input VDD - PSD Module VDD - 3.3V for 3V VDD - 5V for 5V VDD - PSD Module VDD - 3.3V for 3V VDD - 5V for 5V
50 13 29 69 11 17
33 9 19 45 N/ A N/ A
Note: 1. N/A = Signal Not Available on 52-pin package.
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uPSD33xx HARDWARE DESCRIPTION
The uPSD33xx has a modular architecture built from a stacked die process. There are two die, one is designated "MCU Module" in this document, and the other is designated "PSD Module" (see Figure 5., page 14). In all cases, the MCU Module die operates at 3.3V with 5V tolerant I/O. The PSD Module is either a 3.3V die or a 5V die, depending on the uPSD33xx device as described below. The MCU Module consists of a fast 8032 core, that operates with 4 clocks per instruction cycle, and has many peripheral and system supervisor functions. The PSD Module provides the 8032 with multiple memories (two Flash and one SRAM) for program and data, programmable logic for address decoding and for general-purpose logic, and additional I/O. The MCU Module communicates with the PSD Module through internal address and data busses (A8 A15, AD0 AD7) and control signals (RD, WR, PSEN, ALE, RESET). There are slightly different I/O characteristics for each module. I/Os for the MCU module are designated as Ports 1, 3, and 4. I/Os for the PSD Module are designated as Ports A, B, C, and D. For all 5V uPSD33xx devices, a 3.3V MCU Module is stacked with a 5V PSD Module. In this case, a 5V uPSD33xx device must be supplied with 3.3VCC for the MCU Module and 5.0VDD for the PSD Module. Ports 3 and 4 of the MCU Module are 3.3V ports with tolerance to 5V devices (they can be directly driven by external 5V devices and they can directly drive external 5V devices while producing a VOH of 2.4V min and VCC max). Ports A, B, C, and D of the PSD Module are true 5V ports. For all 3.3V uPSD33xxV devices, a 3.3V MCU Mod ule is stacked with a 3.3V PSD Module. In this case, a 3.3V uPSD33xx device needs to be supplied with a single 3.3V voltage source at both VCC and VDD. I/O pins on Ports 3 and 4 are 5V tolerant and can be connected to external 5V peripherals devices if desired. Ports A, B, C, and D of the PSD Module are 3.3V ports, which are not tolerant to external 5V devices. Refer to Table 3 for port type and voltage source requirements. 80-pin uPSD33xx devices provide access to 8032 address, data, and control signals on external pins to connect external peripheral and memory devices. 52-pin uPSD33xx devices do not provide access to the 8032 system bus. All non-volatile memory and configuration portions of the uPSD33xx device are programmed through the JTAG interface and no special programming voltage is needed. This same JTAG port is also used for debugging of the 8032 core at runtime providing breakpoint, single-step, display, and trace features. A non-volatile security bit may be programmed to block all access via JTAG interface for security. The security bit is defeated only by erasing the entire device, leaving the device blank and ready to use again.
Table 3. Port Type and Voltage Source Combinations
Device Type 5V: uPSD33xx 3.3V: uPSD33xxV VCC for MCU Module 3.3V 3.3V VDD for PSD Module 5.0V 3.3V Ports 3 and 4 on MCU Module 3.3V but 5V tolerant 3.3V but 5V tolerant Ports A, B, C, and D on PSD Module 5V 3.3V. NOT 5V tolerant
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Figure 5. uPSD33xx Functional Modules
Port 3 - UART0, Intr, Timers Port 1 - Tmer, ADC, SPI i Port 4 - PCA, PWM, UART1 Port 3 I2C
M CU Module
Port 3 Port 1 T rbo 8032 Core u Dual UARTs Interrupt 3 Tmer / i Counters 256 Byte SRAM
XT L A Clock Unit
10-bit ADC
SP I
PCA PWM Counters
IC Unit
2
VCC Pins 3.3V
Dedicated Memory Interface Prefetch, Branch Cache 8-Bit Die-to-Die Bus Enhanced MCU Interface
PSD Page Register
8032 Internal Bus
Ext. Bus Reset Input
LVD
JT G A DEBUG
Internal Reset
Reset Logic
WDT
Reset Pin
Main Flash
Decode PLD
Secondary Flash
PS D Reset SRAM
P S D Module
PSD Internal Bus
JT G ISP A
CPLD - 16 MACROCELLS
VDD Pins 3.3V or 5V
u PS D 3 3X X
Port C JTAG and GPIO
Port A,B,C PLD I/O and GPIO
Port D GPIO
AI07842
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MEMORY ORGANIZATION
The 8032 MCU core views memory on the MCU module as "internal" memory and it views memory on the PSD module as "external" memory, see Figure 6. Internal memory on the MCU Module consists of DATA, IDATA, and SFRs. These standard 8032 memories reside in 384 bytes of SRAM located at a fixed address space starting at address 0x0000. External memory on the PSD Module consists of four types: main Flash (64K, 128K, or 256K bytes), a smaller secondary Flash (16K, or 32K), SRAM (2K, 8K, or 32K bytes), and a block of PSD Module control registers called CSIOP (256 bytes). These external memories reside at programmable address ranges, specified using the software tool PSDsoft Express. See the PSD Module section of this document for more details on these memories. External memory is accessed by the 8032 in two separate 64K byte address spaces. One address space is for program memory and the other adFigure 6. uPSD33xx Memories
Internal SRAM on MCU Module External Memory on PSD Module
dress space is for data memory. Program memory is accessed using the 8032 signal, PSEN. Data memory is accessed using the 8032 signals, RD and WR. If the 8032 needs to access more than 64K bytes of external program or data memory, it must use paging (or banking) techniques provided by the Page Register in the PSD Module. Note: When referencing program and data memory spaces, it has nothing to do with 8032 internal SRAM areas of DATA, IDATA, and SFR on the MCU Module. Program and data memory spaces only relate to the external memories on the PSD Module. External memory on the PSD Module can overlap the internal SRAM memory on the MCU Module in the same physical address range (starting at 0x0000) without interference because the 8032 core does not assert the RD or WR signals when accessing internal SRAM.
Fixed Addresses FF Indirect Addressing
Main Flash 384 Bytes SRAM 128 Bytes
· External memories may be placed at virtually any address using software tool PSDsoft Express. · The SRAM and Flash memories may be placed in 8032 Program Space or Data Space using PSDsoft Express. · Any memory in 8032 Data Space is XDATA.
IDATA
80 128 Bytes 7F
SFR
Direct Addressing
64KB, 128KB, or 256KB
Secondar y Flash
SRAM
128 Bytes
DATA
0 Direct or Indirect Addressing
16KB or 32KB
2KB, 8KB, or 32KB
CSIOP 256 Bytes
AI07843
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Internal Memory (MCU Module, Standard 8032 Memory: DATA, IDATA, SFR) DATA Memory. The first 128 bytes of internal SRAM ranging from address 0x0000 to 0x007F are called DATA, which can be accessed using 8032 direct or indirect addressing schemes and are typically used to store variables and stack. Four register banks, each with 8 registers (R0 R7), occupy addresses 0x0000 to 0x001F. Only one of these four banks may be enabled at a time. The next 16 locations at 0x0020 to 0x002F contain 128 directly addressable bit locations that can be used as software flags. SRAM locations 0x0030 and above may be used for variables and stack. IDATA Memory. The next 128 bytes of internal SRAM are named IDATA and range from address 0x0080 to 0x00FF. IDATA can be accessed only through 8032 indirect addressing and is typically used to hold the MCU stack as well as data variables. The stack can reside in both DATA and IDATA memories and reach a size limited only by the available space in the combined 256 bytes of these two memories (since stack accesses are always done using indirect addressing, the boundary between DATA and IDATA does not exist with regard to the stack). SFR Memory. Special Function Registers (Table 5., page 24) occupy a separate physical memory, but they logically overlap the same 128 bytes as IDATA, ranging from address 0x0080 to 0x00FF. SFRs are accessed only using direct addressing. There 86 active registers used for many functions: changing the operating mode of the 8032 MCU core, controlling 8032 peripherals, controlling I/O, and managing interrupt functions. The remaining unused SFRs are reserved and should not be accessed. 16 of the SFRs are both byte- and bit-addressable. Bit-addressable SFRs are those whose address ends in "0" or "8" hex. External Memory (PSD Module: Program memory, Data memory) The PSD Module has four memories: main Flash, secondary Flash, SRAM, and CSIOP. See the PSD MODULE section for more detailed information on these memories. Memory mapping in the PSD Module is implemented with the Decode PLD (DPLD) and optionally the Page Register. The user specifies decode equations for individual segments of each of the memories using the software tool PSDsoft Express. This is a very easy point-and-click process allow ing total flexibility in mapping memories. Additionally, each of the memories may be placed in various combinations of 8032 program address space or 8032 data address space by using the software tool PSDsoft Express. Program Memory. External program memory is addressed by the 8032 using its 16-bit Program Counter (PC) and is accessed with the 8032 signal, PSEN. Program memory can be present at any address in program space between 0x0000 and 0xFFFF. After a power-up or reset, the 8032 begins program execution from location 0x0000 where the reset vector is stored, causing a jump to an initialization routine in firmware. At address 0x0003, just following the reset vector are the interrupt service locations. Each interrupt is assigned a fixed interrupt service location in program memory. An interrupt causes the 8032 to jump to that service location, where it commences execution of the service routine. External Interrupt 0 (EXINT0), for example, is assigned to service location 0x0003. If EXINT0 is going to be used, its service routine must begin at location 0x0003. Interrupt service locations are spaced at 8-byte intervals: 0x0003 for EXINT0, 0x000B for Timer 0, 0x0013 for EXINT1, and so forth. If an interrupt service routine is short enough, it can reside entirely within the 8-byte interval. Longer service routines can use a jump instruction to somewhere else in program memory. Data Memory. External data is referred to as XDATA and is addressed by the 8032 using Indirect Addressing via its 16-bit Data Pointer Register (DPTR) and is accessed by the 8032 signals, RD and WR. XDATA can be present at any address in data space between 0x0000 and 0xFFFF. Note: the uPSD33xx has dual data pointers (source and destination) making XDATA transfers much more efficient. Mem ory Placement. PSD Module architecture allow s the placement of its external memories into different combinations of program memory and data memory spaces. This means the main Flash, the secondary Flash, and the SRAM can be viewed by the 8032 MCU in various combinations of program memory or data memory as defined by PSDsoft Express. As an example of this flexibility, for applications that require a great deal of Flash memory in data space (large lookup tables or extended data recording), the larger main Flash memory can be placed in data space and the smaller secondary Flash memory can be placed in program space. The opposite can be realized for a different application if more Flash memory is needed for code and less Flash memory for data.
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By default, the SRAM and CSIOP memories on the PSD Module must always reside in data memory space and they are treated by the 8032 as XDATA. However, the SRAM may optionally reside in program space in addition to data space if it is desired to execute code from SRAM. The main Flash and secondary Flash memories may reside in program space, data space, or both. These memory placement choices specified by PSDsoft Express are programmed into non-volatile sections of the uPSD33xx, and are active at power-up and after reset. It is possible to override these initial settings during runtime for In-Application Programming (IAP). Standard 8032 MCU architecture cannot write to its own program memory space to prevent accidental corruption of firmware. However, this becomes an obstacle in typical 8032 systems when a remote update to firmware in Flash memory is required using IAP. The PSD module provides a solution for remote updates by allowing 8032 firmware to temporarily "reclassify" Flash memory to reside in data space during a remote update, then returning Flash memory back to program space when finished. See the VM Register (Table 78., page 143) in the PSD Module section of this document for more details.
8032 MCU CORE PERFORMANCE ENHANCEMENTS
Before describing performance features of the uPSD33xx, let us first look at standard 8032 architecture. The clock source for the 8032 MCU creates a basic unit of timing called a machine-cycle, which is a period of 12 clocks for standard 8032 MCUs. The instruction set for traditional 8032 MCUs consists of 1, 2, and 3 byte instructions that execute in different combinations of 1, 2, or 4 machine-cycles. For example, there are one-byte instructions that execute in one machine-cycle (12 clocks), one-byte instructions that execute in four machine-cycles (48 clocks), two-byte, two-cycle instructions (24 clocks), and so on. In addition, standard 8032 architecture will fetch two bytes from program memory on almost every machinecycle, regardless if it needs them or not (dummy fetch). This means for one-byte, one-cycle instructions, the second byte is ignored. These one-byte, one-cycle instructions account for half of the 8032's instructions (126 out of 255 opcodes). There are inefficiencies due to wasted bus cycles and idle bus times that can be eliminated. The uPSD33xx 8032 MCU core offers increased performance in a number of ways, while keeping the exact same instruction set as the standard 8032 (all opcodes, the number of bytes per instruction, and the native number a machine-cycles per instruction are identical to the original 8032). The first way performance is boosted is by reducing the machine-cycle period to just 4 MCU clocks as compared to 12 MCU clocks in a standard 8032. This shortened machine-cycle improves the instruction rate for one-byte, one-cycle instructions by a factor of three (Figure 7., page 18) compared to standard 8051 architectures, and significantly improves performance of multiple-cycle instruction types. The example in Figure 7 shows a continuous execution stream of one-byte, one-cycle instructions. The 5V uPSD33xx will yield 10 MIPS peak performance in this case while operating at 40MHz clock rate. In a typical application however, the effective performance will be lower since programs do not use only one-cycle instructions, but special techniques are implemented in the uPSD33xx to keep the effective MIPS rate as close as possible to the peak MIPS rate at all times. This is accomplished with an instruction Pre-Fetch Queue (PFQ) and a Branch Cache (BC) as shown in Figure 8., page 18.
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Figure 7. Comparison of uPSD33xx with Standard 8032 Performance
1-byte, 1-Cycle Instructions Instruction A Turbo uPSD33XX
Execute Instruction and Pre-Fetch Next Instruction
Instruction B
Execute Instruction and Pre-Fetch Next Instruction
Instruction C
Execute Instruction and Pre-Fetch Next Instruction
4 clocks (one machine cycle)
one machine cycle
one machine cycle
MCU Clock
12 clocks (one machine cycle)
Instruction A Standard 8032
Fetch Byte for Instruction A Execute Instruction A and Fetch a Second Dummy Byte
Dummy Byte is Ignored (wasted bus access)
Turbo uPSD33XX executes instructions A, B, and C in the same amount of time that a standard 8032 executes only instruction A.
AI08808
Figure 8. Instruction Pre-Fetch Queue and Branch Cache
Branch 4 Code Branch Cache (BC) Branch 4 Code Branch 4 Code Branch 4 Code Branch 4 Code Branch 4 Code Previous Branch 4 Compare
Branch 3 Branch 3 Branch 3 Branch 3 Branch 3 Branch 3 Previous Code Code Code Code Code Code Branch 3 Branch 2 Branch 2 Branch 2 Branch 2 Branch 2 Branch 2 Previous Code Branch 2 Code Code Code Code Code Branch 1 Code Branch 1 Code Branch 1 Code Branch 1 Code Branch 1 Code Branch 1 Code Previous Branch 1 Address
Load on Branch Address Match Current Branch Address Instruction Byte Program Memory on PSD Module
8
Instruction Byte
8
8032 MCU
Address
16
6 Bytes of Instruction
Address
16
Wait
Instruction Pre-Fetch Queue (PFQ)
Stall
AI08809
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Pre-Fetch Queue (PFQ) and Branch Cache (BC) The PFQ is always working to minimize the idle bus time inherent to 8032 MCU architecture, to eliminate wasted memory fetches, and to maximize memory bandwidth to the MCU. The PFQ does this by running asynchronously in relation to the MCU, looking ahead to pre-fetch code from program memory during any idle bus periods. Only necessary bytes will be fetched (no dummy fetches like standard 8032). The PFQ will queue up to six code bytes in advance of execution, which significantly optimizes sequential program performance. However, when program execution becomes non-sequential (program branch), a typical pre-fetch queue will empty itself and reload new code, causing the MCU to stall. The Turbo uPSD33xx diminishes this problem by using a Branch Cache with the PFQ. The BC is a four-way, fully associative cache, meaning that when a program branch occurs, it's branch destination address is compared simultaneously with four recent previous branch destinations stored in the BC. Each of the four cache entries contain up to six bytes of code related to a branch. If there is a hit (a match), then all six code bytes of the matching program branch are transferred immediately and simultaneously from the BC to the PFQ, and execution on that branch continues with minimal delay. This greatly reduces the chance that the MCU will stall from an empty PFQ, and improves performance in embedded control systems where it is quite common to branch and loop in relatively small code localities. By default, the PFQ and BC are enabled after power-up or reset. The 8032 can disable the PFQ and BC at runtime if desired by writing to a specific SFR (BUSCON). The memory in the PSD module operates with variable wait states depending on the value specified in the SFR named BUSCON. For example, a 5V uPSD33xx device operating at a 40MHz crystal frequency requires four memory wait states (equal to four MCU clocks). In this example, once the PFQ has one or more bytes of code, the wait states become transparent and a full 10 MIPS is achieved when the program stream consists of sequential one-byte, one machine-cycle instructions as shown in Figure 7., page 18 (transparent because a machine-cycle is four MCU clocks which equals the memory pre-fetch wait time that is also four MCU clocks). But it is also important to understand PFQ operation on multi-cycle instructions. PFQ Example, Multi-cycle Instructions Let us look at a string of two-byte, two-cycle instructions in Figure 9., page 20. There are three instructions executed sequentially in this example, instructions A, B, and C. Each of the time divisions in the figure is one machine-cycle of four clocks, and there are six phases to reference in this discussion. Each instruction is pre-fetched into the PFQ in advance of execution by the MCU. Prior to Phase 1, the PFQ has pre-fetched the two instruction bytes (A1 and A2) of instruction A. During Phase one, both bytes are loaded into the MCU execution unit. Also in Phase 1, the PFQ is prefetching the first byte (B1) of instruction B from program memory. In Phase 2, the MCU is processing Instruction A internally while the PFQ is pre-fetching the second byte (B2) of Instruction B. In Phase 3, both bytes of instruction B are loaded into the MCU execution unit and the PFQ begins to pre-fetch bytes for the third instruction C. In Phase 4 Instruction B is processed and the prefetching continues, eliminating idle bus cycles and feeding a continuous flow of operands and opcodes to the MCU execution unit. The uPSD33xx MCU instructions are an exact 1/3 scale of all standard 8032 instructions with regard to number of cycles per instruction. Figure 10., page 20 shows the equivalent instruction sequence from the example above on a standard 8032 for comparison. Aggregate Performance The stream of two-byte, two-cycle instructions in Figure 9., page 20, running on a 40MHz, 5V, uPSD33xx will yield 5 MIPs. And we saw the stream of one-byte, one-cycle instructions in Figure 7., page 18, on the same MCU yield 10 MIPs. Effective performance will depend on a number of things: the MCU clock frequency; the mixture of instructions types (bytes and cycles) in the application; the amount of time an empty PFQ stalls the MCU (mix of instruction types and misses on Branch Cache); and the operating voltage. A 5V uPSD33xx device operates with four memory wait states, but a 3.3V device operates with five memory wait states yielding 8 MIPS peak compared to 10 MIPs peak for 5V device. The same number of wait states will apply to both program fetches and to data READ/WRITEs unless otherwise specified in the SFR named BUSCON. In general, a 3X aggregate performance increase is expected over any standard 8032 application running at the same clock frequency.
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Figure 9. PFQ Operation on Multi-cycle Instructions
Three 2-byte, 2-cycle Instructions on uPSD33XX Pre-Fetch Inst A Pre-Fetch Inst B Pre-Fetch Inst C
PFQ
Inst A, Byte 1 Inst A, Byte 2 Inst B, Byte 1 Inst B, Byte 2 Inst C, Byte 1 Inst C, Byte 2 4-clock Macine Cycle
Continue to Pre-Fetch
Phase 1 MCU Execution
Previous Instruction A1 A2
Phase 2
Process A
Phase 3
B1 B2
Phase 4
Process B
Phase 5
C1 C2
Phase 6
Process C Next Inst
Instruction A
Instruction B
Instruction C
AI08810
Figure 10. uPSD33xx Multi-cycle Instructions Compared to Standard 8032
Three 2-byte, 2-cycle Instructions, uPSD33XX vs. Standard 8032 24 Clocks Total (4 clocks per cycle) uPSD33XX A1 A2 Inst A B1 B2 Inst B C1 C2 Inst C
1 Cycle 72 Clocks (12 clocks per cycle) Std 8032 Byte 1 Byte 2 Process Inst A 1 Cycle
AI08811
Byte 1
Byte 2
Process Inst B
Byte 1
Byte 2
Process Inst C
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MCU MODULE DISCRIPTION
This section provides a detail description of the MCU Module system functions and peripherals, including: 8032 MCU Registers Special Function Registers 8032 Addressing Modes uPSD33xx Instruction Set Summary D ual Data Pointers D ebug Unit Interrupt System MCU Clock Generation Power Saving Modes Oscillator and External Components I/O Ports MCU Bus Interface Supervisory Functions Standard 8032 Timer/Counters Serial UART Interfaces IrDA Interface I2C Interface SPI Interface Analog to Digital Converter Programmable Counter Array (PCA) Note: A full description of the 8032 instruction set may be found in the uPSD33xx Programmers Guid e.
8032 MCU REGISTERS
The uPSD33xx has the following 8032 MCU core registers, also shown in Figure 11. Figure 11. 8032 MCU Registers
A B SP PCH PCL PSW R0-R7 DPTR(DPH)
AI06636
Accumulator B Register Stack Pointer Program Counter Program Status Word General Purpose Register (Bank0-3) Data Pointer Register
DPTR(DPL)
Stack Pointer (SP) The SP is an 8-bit register which holds the current location of the top of the stack. It is incremented before a value is pushed onto the stack, and decremented after a value is popped off the stack. The SP is initialized to 07h after reset. This causes the stack to begin at location 08h (top of stack). To avoid overlapping conflicts, the user must initialize the top of the stack to 20h if all four banks of registers R0 - R7 are used, and the user must initialize the top of stack to 30h if all of the 8032 bit memory locations are used. Data Pointer (DPTR) DPTR is a 16-bit register consisting of two 8-bit registers, DPL and DPH. The DPTR Register is used as a base register to create an address for indirect jumps, table look-up operations, and for external data transfers (XDATA). When not used for addressing, the DPTR Register can be used as a general purpose 16-bit data register.
Very frequently, the DPTR Register is used to access XDATA using the External Direct addressing mode. The uPSD33xx has a special set of SFR registers (DPTC, DPTM) to control a secondary DPTR Register to speed memory-to-memory XDATA transfers. Having dual DPTR Registers allows rapid switching between source and destination addresses (see details in DUAL DATA POINTERS, page 37). Program Counter (PC) The PC is a 16-bit register consisting of two 8-bit registers, PCL and PCH. This counter indicates the address of the next instruction in program memory to be fetched and executed. A reset forces the PC to location 0000h, which is where the reset jump vector is stored. Accumulator (ACC) This is an 8-bit general purpose register which holds a source operand and receives the result of arithmetic operations. The ACC Register can also be the source or destination of logic and data movement operations. For MUL and DIV instructions, ACC is combined with the B Register to hold 16-bit operands. The ACC is referred to as "A" in the MCU instruction set. B Register (B) The B Register is a general purpose 8-bit register for temporary data storage and also used as a 16bit register when concatenated with the ACC Register for use with MUL and DIV instructions.
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General Purpose Registers (R0 - R7) There are four banks of eight general purpose 8bit registers (R0 - R7), but only one bank of eight registers is active at any given time depending on the setting in the PSW word (described next). R0 R7 are generally used to assist in manipulating values and moving data from one memory location to another. These register banks physically reside in the first 32 locations of 8032 internal DATA SRAM, starting at address 00h. At reset, only the first bank of eight registers is active (addresses 00h to 07h), and the stack begins at address 08h. Program Status Word (PSW) The PSW is an 8-bit register which stores several important bits, or flags, that are set and cleared by many 8032 instructions, reflecting the current state of the MCU core. Figure 12., page 22 shows the individual flags. Carry Flag (CY). This flag is set when the last arithmetic operation that was executed results in a carry (addition) or borrow (subtraction). It is cleared by all other arithmetic operations. The CY flag is also affected by Shift and Rotate Instructions. Auxiliary Carry Flag (AC). This flag is set when the last arithmetic operation that was executed results in a carry into (addition) or borrow from (subtraction) the high-order nibble. It is cleared by all other arithmetic operations. Figure 12. Program Status Word (PSW) Register
MSB PSW Carry Flag Auxillary Carry Flag General Purpose Flag Register Bank Select Flags (to select Bank0-3)
AI06639
General Purpose Flag (F0). This is a bit-addressable, general-purpose flag for use under software control. Register Bank Select Flags (RS1, RS0). These bits select which bank of eight registers is used during R0 - R7 register accesses (see Table 4) Overflow Flag (OV). The OV flag is set when: an ADD , ADDC, or SUBB instruction causes a sign change; a MUL instruction results in an overflow (result greater than 255); a DIV instruction causes a divide-by-zero condition. The OV flag is cleared by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. The CLRV instruction will clear the OV flag at any time. Parity Flag (P). The P flag is set if the sum of the eight bits in the Accumulator is odd, and P is cleared if the sum is even. Table 4. .Register Bank Select Addresses
RS1 0 0 1 1 RS0 0 1 0 1 Register Bank 0 1 2 3 8032 Internal DATA Address 00h - 07h 08h - 0Fh 10h - 17h 18h - 1Fh
LSB P Reset Value 00h Parity Flag Bit not assigned Overflow Flag
CY AC FO RS1 RS0 OV
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SPECIAL FUNCTION REGISTERS (SFR)
A group of registers designated as Special Function Register (SFR) is shown in Table 5., page 24. SFRs control the operating modes of the MCU core and also control the peripheral interfaces and I/O pins on the MCU Module. The SFRs can be accessed only by using the Direct Addressing method within the address range from 80h to FFh of internal 8032 SRAM. Sixteen addresses in SFR address space are both byte- and bit-addressable. The bit-addressable SFRs are noted in Table 5. 86 of a possible 128 SFR addresses are occupied. The remaining unoccupied SFR addresses (designated as "RESERVED" in Table 5) should not be written. Reading unoccupied locations will return an undefined value. Note: There is a separate set of control registers for the PSD Module, designated as csiop, and they are described in the PSD MODULE, page 133 . The I/O pins, PLD, and other functions on the PSD Module are NOT controlled by SFRs. SFRs are categorized as follows: MCU core registers: IP, A, B, PSW, SP, DPTL, DPTH, DPTC, DPTM MCU Module I/O Port registers: P1, P3, P4, P1SFS0, P1SFS1, P3SFS, P4SFS0, P4SFS1 Standard 8032 Timer registers TCON, TMOD, T2CON, TH0, TH1, TH2, TL0, TL1, TL2, RCAP2L, RCAP2H Standard Serial Interfaces (UART)
SCON0, SBUF0, SCON1, SBUF1 Power, clock, and bus timing registers PCON, CCON0, BUSCON H ardware watchdog timer registers W DKEY, WDRST Interrupt system registers IP, IPA, IE, IEA Prog. Counter Array (PCA) control registers PCACL0, PCACH0, PCACON0, PCASTA, PCACL1, PCACH1, PCACON1, CCON2, CCON3 PCA capture/compare and PWM registers C APCOML0, CAPCOMH0, TCMMODE0, CAPCOML1, CAPCOMH1, TCMMODE2, CAPCOML2, CAPCOMH2, TCMMODE2, CAPCOML3, CAPCOMH3, TCMMODE3, CAPCOML4, CAPCOMH4, TCMMODE4, CAPCOML5, CAPCOMH5, TCMMODE5, PWMF0, PMWF1 SPI interface registers SPICLKD, SPISTAT, SPITDR, SPIRDR, SPICON0, SPICON1 I2C interface registers S1SETUP, S1CON, S1STA, S1DAT, S1ADR A nalog to Digital Converter registers ACON, ADCPS, ADAT0, ADAT1 IrDA interface register I R D A C ON
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Table 5. SFR Memory Map with Direct Address and Reset Value
SFR Addr (hex) 80 S FR Name Bit Name and 7 6 5 4 3 2 1 0 Reset Re g. Value Descr. (hex) with Link
RESERVED Stack Pointer (SP), page 21 Data Pointer (DPTR), p age 21
81
SP
SP[7:0]
07
82 83 84 85
DPL DPH
DPL[7:0] DPH[7:0] RESERVED
00 00
DPTC
AT
DPSEL[2:0]
00
Table 13., page 37 Table 14., page 38 Table 24., page 50 Table 39., page 70 Table 40., page 72 Standard Timer SFRs, pag e 69 Table 29., page 60 Table 30., page 60 Table 25., page 57 Table 28., page 60 Table 32., page 61 Table 33., page 61
86
DPTM
MD1[1:0]
MD0[1:0]
00
87
PCON
SMOD0
SMOD1
POR
RCLK1
TCLK1
PD
IDLE
00
88(1)
TCON
TF1 <8Fh>
T R1 <8Eh>
T F0 <8Dh>
T R0 <8Ch>
IE1 <8Bh>
IT1 <8Ah>
IE0 I T0 <89h> <88h>
00
89 8A 8B 8C 8D 8E
TMOD TL0 TL1 T H0 T H1 P1SFS0
GATE
C/T
M1
M0 TL0[7:0] TL1[7:0] TH0[7:0] TH1[7:0]
GATE
C/ T
M1
M0
00 00 00 00 00 00
P1SFS0[7:0]
8F
P1SFS1
P1SFS1[7:0]
00
90(1)
P1
P1.7 <97h>
P1.6 <96h>
P1.5 <95h>
P1.4 <94h>
P1.3 <93h>
P1.2 <92h>
P1.1 P1.0 <91h> <90h>
FF
91
P3SFS
P3SFS[7:0]
00
92
P4SFS0
P4SFS0[7:0]
00
93
P4SFS1
P4SFS1[7:0]
00
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SFR Addr (hex) 94 S FR Name Bit Name and 7 6 5 4 3 ADCCE 2 1 ADCPS[2:0] 0 Reset Re g. Value Descr. (hex) with Link 00 Table 64., page 122 Table 65., page 122 Table 66., page 122 Table 63., page 121 Table 45., page 82 Figure 25., page 79
ADCPS
95
ADAT0
ADATA[7:0]
00
96
ADAT1
ADATA[9:8]
00
97
ACON
AINTF
AINTEN
ADEN
ADS[2:0]
ADST
ADSF
00
98(1)
SCON0
SM0 <9Fh>
S M1 <9Eh>
S M2 <9Dh>
REN <9Ch>
TB8 <9Bh>
RB 8 <9Ah>
TI RI <99h> <9h8>
00
99 9A 9B 9C 9D 9E 9F A0 A1 A2
SBUF0
SBUF0[7:0] RESERVED RESERVED RESERVED
00
BUSCON
EPFQ
EBC
WRW1
WRW0
RDW1
RDW0
CW 1
C W0
EB
Table 35., page 63
RESERVED RESERVED RESERVED RESERVED PCACL0 PCACL0[7:0] 00 Table 67., page 124 Table 67., page 124 Table 70., page 129 Table 72., page 131 Table 38., page 68 Table 18., page 44
A3
PCACH0
PCACH0[7:0]
00
A4
PCACON0 EN_ALL EN_PCA
EOVF1
PCA_IDL
CLK_SEL[1:0]
00
A5
PCASTA
OVF1
INTF5
INTF4
INTF3
OVF0
INTF2
INTF1 INTF0
00
A6
WDTRST
WDTRST[7:0]
00
A7
IEA
EADC
ESPI
EPCA
ES1
EI2C
00
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SFR Addr (hex) A8(1) S FR Name Bit Name and 7 EA 6 5 E T2 4 ES0 3 ET1 2 EX1 1 0 Reset Re g. Value Descr. (hex) with Link 00 Table 17., page 43
IE
ET0 EX0 PWM[1:0] PWM[1:0] PWM[1:0]
A9 AA AB AC AD
TCMMODE EINTF 0 TCMMODE EINTF 1 TCMMODE EINTF 2 CAPCOML 0 CAPCOMH 0 WDTKEY
E_COMP CAP_PE E_COMP CAP_PE E_COMP CAP_PE
CAP_NE MATCH TOGGLE CAP_NE MATCH TOGGLE CAP_NE MATCH TOGGLE CAPCOML0[7:0] CAPCOMH0[7:0]
00 00 00 00 00 Table 67., page 124 Table 37., page 68 Table 67., page 124 Table 26., page 58 Table 73., page 132
AE
WDTKEY[7:0]
55
AF
CAPCOML 1 P3.7 P3.6 P3.5
CAPCOML1[7:0]
00
B0(1)
P3 CAPCOMH 1 CAPCOML 2 CAPCOMH 2 PWMF0
P3.4
P3.3
P3.2
P3.1 P3.0
FF
B1 B2 B3 B4 B5 B6 B7
CAPCOMH1[7:0] CAPCOML2[7:0] CAPCOMH2[7:0] PWMF0[7:0] RESERVED RESERVED
00 00 00 00 Table 67., page 124
IPA
PADC
PSPI
PPCA
PS1
PI2C
00
Table 20., page 45 Table 19., page 44
B8(1) B9 BA BB BC
IP
P T2
PS0
PT1
PX1
PT0 PX0
00
RESERVED PCACL1 PCACH1 PCACON1 EN_PCA EOVF1 PCACL1[7:0] PCACH1[7:0] PCA_IDL CLK_SEL[1:0] 00 00 00 Table 67., page 124 Table 71., page 130
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SFR Addr (hex) BD BE BF S FR Name Bit Name and 7 6 5 4 3 2 1 0 Reset Re g. Value Descr. (hex) with Link 00 00 00 Table 27., page 58 Table 73., page 132
TCMMODE EINTF 3 TCMMODE EINTF 4 TCMMODE EINTF 5 P4 CAPCOML 3 CAPCOMH 3 CAPCOML 4 CAPCOMH 4 CAPCOML 5 CAPCOMH 5 PWMF1 T2 CON TF2 P4.7
E_COMP CAP_PE E_COMP CAP_PE E_COMP CAP_PE P4.6 P4.5
CAP_NE MATCH TOGGLE CAP_NE MATCH TOGGLE CAP_NE MATCH TOGGLE P4.4 P4.3 P4.2
PWM[1:0] PWM[1:0] PWM[1:0] P4.1 P4.0
C0(1)
FF
C1 C2 C3 C4 C5 C6 C7 C8(1) C9 CA CB CC CD CE
CAPCOML3[7:0] CAPCOMH3[7:0] CAPCOML4[7:0] CAPCOMH4[7:0] CAPCOML5[7:0] CAPCOMH5[7:0] PWMF1[7:0] EXF2 RCLK TCLK EXEN2 TR 2 C/T2 CP/ RL2
00 00 00 00 00 00 00 00 Table 41., page 75 Table 67., page 124
RESERVED RCAP2L RCAP2H TL2 T H2 IRDACON IRDA_EN BIT_PULS RCAP2L[7:0] RCAP2H[7:0] TL2[7:0] TH2[7:0] CDIV4 CDIV3 CDIV2 CDIV1 CDIV0 00 00 00 00 0F Table 48., page 93 Program Status Word (PSW), pa ge 22 Standard Timer SFRs, pag e 69
D0(1)
PSW
CY
AC
F0
RS[1:0]
OV
P
00
D1 D2 SPICLKD
RESERVED SPICLKD[5:0] 04 Table 61., page 118 Table 62., page 119
D3
SPISTAT
BUSY
TEISF
RORISF
TISF
RISF
02
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SFR Addr (hex) D4 D5 D6 S FR Name SPITDR SPIRDR SPICON0 TE RE Bit Name and 7 6 5 4 SPITDR[7:0] SPIRDR[7:0] SPIEN SSEL FLSB SPO 3 2 1 0 Reset Re g. Value Descr. (hex) with Link 00 00 00 Table 62., page 119 Table 59., page 117 Table 60., page 118 Table 46., page 83 Figure 25., page 79
D7
SPICON1
TEIE
RORIE
TIE
RIE
00
D8(1)
SCON1
SM0
S M1
S M2
REN
TB8
RB 8
TI
RI
00
D9 DA DB
SBUF1
SBUF1[7:0] RESERVED
00
S1SETUP
SS_EN
SMPL_SET[6:0]
00
Table 55., page 105 Table 50., page 100 Table 52., page 103 Table 53., page 104 Table 54., page 104 Accumulat or (ACC), pa ge 21
DC
S1CON
CR2
E N1
STA
STO
ADDR
AA
CR1
C R0
00
DD
S1STA
GC
STOP
INTR
TX_MD B_BUSY B_LOST ACK_R
SLV
00
DE
S1DAT
S1DAT[7:0]
00
DF
S1ADR
S1ADR[7:0]
00
E0
(1 )
A
A[7:0]
00
E1 to EF F0(1) F1 F2 F3 F4 F5 F6 B
RESERVED B Register (B), page 21
B[7:0] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
00
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SFR Addr (hex) F7 F8 F9 FA FB CCON2 CCON0 S FR Name Bit Name and 7 6 5 4 3 2 1 0 Reset Re g. Value Descr. (hex) with Link
RESERVED RESERVED DBGCE CPU_AR RESERVED PCA0CE PCA0PS[3:0] 10 Table 68., page 125 Table 69., page 125 CPUPS[2:0] 10 Table 21., page 47
FC FD FE FF
CCON3
PCA1CE RESERVED RESERVED RESERVED
PCA1PS[3:0]
10
Note: 1. This SFR can be addressed by individual bits (Bit Address mode) or addressed by the entire byte (Direct Address mode).
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8032 ADDRESSING MODES
The 8032 MCU uses 11 different addressing modes listed below: R egister D irect R egister Indirect Immediate External Direct External Indirect Indexed R elative Absolute L ong Bit Register Addressing This mode uses the contents of one of the registers R0 - R7 (selected by the last three bits in the instruction opcode) as the operand source or destination. This mode is very efficient since an additional instruction byte is not needed to identify the operand. For example:
MOV A, R7 ; Move contents of R7 to accumulator
Immediate Addressing This mode uses 8-bits of data (a constant) contained in the second byte of the instruction, and stores it into the memory location or register indicated by the first byte of the instruction. Thus, the data is immediately available within the instruction. This mode is commonly used to initialize registers and SFRs or to perform mask operations. There is also a 16-bit version of this mode for loading the DPTR Register. In this case, the two bytes following the instruction byte contain the 16-bit value. For example:
MOV A, 40# ; Move the constant, 40h, into ; the accumulator
MOV DPTR, 1234# ; Move the constant, 1234h, into ; DPTR
Direct Addressing This mode uses an 8-bit address, which is contained in the second byte of the instruction, to directly address an operand which resides in either 8032 DATA SRAM (internal address range 00h07Fh) or resides in 8032 SFR (internal address range 80h-FFh). This mode is quite fast since the range limit is 256 bytes of internal 8032 SRAM. For example:
MOV A, 40h ; Move contents of DATA SRAM ; at location 40h into the accumulator
External Direct Addressing This mode will access external memory (XDATA) by using the 16-bit address stored in the DPTR Register. There are only two instructions using this mode and both use the accumulator to either receive a byte from external memory addressed by DPTR or to send a byte from the accumulator to the address in DPTR. The uPSD33xx has a special feature to alternate the contents (source and destination) of DPTR rapidly to implement very efficient memory-to-memory transfers. For example:
MOVX A, @DPTR ; Move contents of accumulator to ; XDATA at address contained in ; DPTR MOVX @DPTR, A ; Move XDATA to accumulator
Note: See details POINTERS, page 37.
in
DUAL
DATA
Register Indirect Addressing This mode uses an 8-bit address contained in either Register R0 or R1 to indirectly address an operand which resides in 8032 IDATA SRAM (internal address range 80h-FFh). Although 8032 SFR registers also occupy the same physical address range as IDATA, SFRs will not be accessed by Register Indirect mode. SFRs may only be accesses using Direct address mode. For example:
MOV A, @R0 ; Move into the accumulator the ; contents of IDATA SRAM that is ; pointed to by the address ; contained in R0.
External Indirect Addressing This mode will access external memory (XDATA) by using the 8-bit address stored in either Register R0 or R1. This is the fastest way to access XDATA (least bus cycles), but because only 8-bits are available for address, this mode limits XDATA to a size of only 256 bytes (the traditional Port 2 of the 8032 MCU is not available in the uPSD33xx, so it is not possible to write the upper address byte). This mode is not supported by uPSD33xx. For example:
MOVX @R0,A ; Move into the accumulator the ; XDATA that is pointed to by ; the address contained in R0.
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Indexed Addressing This mode is used for the MOVC instruction which allow s the 8032 to read a constant from program memory (not data memory). MOVC is often used to read look-up tables that are embedded in program memory. The final address produced by this mode is the result of adding either the 16-bit PC or DPTR value to the contents of the accumulator. The value in the accumulator is referred to as an index. The data fetched from the final location in program memory is stored into the accumulator, overwriting the index value that was previously stored there. For example:
MOVC A, @A+DPTR; Move code byte relative to ; DPTR into accumulator MOVC A, @A+PC ; Move code byte relative to PC ; into accumulator
Absolute Addressing This mode will append the 5 high-order bits of the address of the next instruction to the 11 low-order bits of an ACALL or AJUMP instruction to produce a 16-bit jump address. The jump will be within the same 2K byte page of program memory as the first byte of the following instruction. For example:
AJMP 0500h ; If next instruction is located at ; address 4000h, the resulting jump ; will be made to 4500h.
Long Addressing This mode will use the 16-bits contained in the two bytes following the instruction byte as a jump destination address for LCALL and LJMP instructions. For example:
LJMP 0500h ; Unconditionally jump to address ; 0500h in program memory
Relative Addressing This mode will add the two's-compliment number stored in the second byte of the instruction to the program counter for short jumps within +128 or 127 addresses relative to the program counter. This is commonly used for looping and is very efficient since no additional bus cycle is needed to fetch the jump destination address. For example:
SJMP 34h ; Jump 34h bytes ahead (in program ; memory) of the address at which ; the SJMP instruction is stored. If ; SJMP is at 1000h, program ; execution jumps to 1034h.
Bit Addressing This mode allows setting or clearing an individual bit without disturbing the other bits within an 8-bit value of internal SRAM. Bit Addressing is only available for certain locations in 8032 DATA and SFR memory. Valid locations are DATA addresses 20h - 2Fh and for SFR addresses whose base address ends with 0h or 8h. (Example: The SFR, IE, has a base address of A8h, so each of the eight bits in IE can be addressed individually at address A8h, A9h, ...up to AFh.) For example:
SETB AFh ; Set the individual EA bit (Enable All ; Interrupts) inside the SFR Register, ; IE.
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uPSD33xx INSTRUCTION SET SUMMARY
Tables 6 through 11 list all of the instructions supported by the uPSD33xx, including the number of bytes and number of machine cycles required to implement each instruction. This is the standard 8051 instruction set. The meaning of "machine cycles" is how many 8032 MCU core machine cycles are required to execute the instruction. The "native" duration of all machine cycles is set by the memory wait state settings in the SFR, BUSCON, and the MCU clock divider selections in the SFR, CCON0 (i.e. a machine cycle is typically set to 4 MCU clocks for a 5V uPSD33xx). However, an individual machine cycle may grow in duration when either of two things happen : Table 6. Arithmetic Instruction Set
Mnemonic(1) and Use A DD A DD A DD A DD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC M UL DIV DA A, Rn A, Direct A, @Ri A, #data A, Rn A, direct A, @Ri A, #data A, Rn A, direct A, @Ri A, #data A Rn direct @Ri A Rn direct @Ri DPTR AB AB A Description Add register to ACC Add direct byte to ACC Add indirect SRAM to ACC Add immediate data to ACC Add register to ACC with carry Add direct byte to ACC with carry Add indirect SRAM to ACC with carry Add immediate data to ACC with carry Subtract register from ACC with borrow Subtract direct byte from ACC with borrow Subtract indirect SRAM from ACC with borrow Subtract immediate data from ACC with borrow Increment A Increment register Increment direct byte Increment indirect SRAM Decrement ACC Decrement register Decrement direct byte Decrement indirect SRAM Increment Data Pointer Multiply ACC and B Divide ACC by B Decimal adjust ACC Length/Cycles 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 1 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 1 byte/2 cycle 1 byte/4 cycle 1 byte/4 cycle 1 byte/1 cycle
1. a stall is imposed while loading the 8032 PreFetch Queue (PFQ); or 2. the occurrence of a cache miss in the Branch Cache (BC) during a branch in program execution flow. See 8032 MCU CORE PERFORMANCE ENH ANCEMENTS, page 17 or more details. But generally speaking, during typical program execution, the PFQ is not empty and the BC has no misses, producing very good performance without extending the duration of any machine cycles. The uPSD33xx Programmers Guide describes each instruction operation in detail.
Note: 1. All mnemonics copyrighted Intel Corporation 1980.
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Table 7. Logical Instruction Set
Mnemonic(1) and Use A NL A NL A NL A NL A NL A NL O RL O RL O RL O RL O RL O RL SWAP X RL X RL X RL X RL X RL X RL CLR CPL RL RLC RR R RC A, Rn A, direct A, @Ri A, #data direct, A direct, #data A, Rn A, direct A, @Ri A, #data direct, A direct, #data A A, Rn A, direct A, @Ri A, #data direct, A direct, #data A A A A A A Description AND register to ACC AND direct byte to ACC AND indirect SRAM to ACC AND immediate data to ACC AND ACC to direct byte AND immediate data to direct byte OR register to ACC OR direct byte to ACC OR indirect SRAM to ACC OR immediate data to ACC OR ACC to direct byte OR immediate data to direct byte Swap nibbles within the ACC Exclusive-OR register to ACC Exclusive-OR direct byte to ACC Exclusive-OR indirect SRAM to ACC Exclusive-OR immediate data to ACC Exclusive-OR ACC to direct byte Exclusive-OR immediate data to direct byte Clear ACC Compliment ACC Rotate ACC left Rotate ACC left through the carry Rotate ACC right Rotate ACC right through the carry Length/Cycles 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 2 byte/1 cycle 3 byte/2 cycle 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 2 byte/1 cycle 3 byte/2 cycle 1 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 2 byte/1 cycle 3 byte/2 cycle 1 byte/1 cycle 1 byte/1 cycle 1 byte/1 cycle 1 byte/1 cycle 1 byte/1 cycle 1 byte/1 cycle
Note: 1. All mnemonics copyrighted Intel Corporation 1980.
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Table 8. Data Transfer Instruction Set
Mnemonic(1) and Use MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX PUSH POP X CH X CH X CH XCHD A, Rn A, direct A, @Ri A, #data Rn, A Rn, direct Rn, #data direct, A direct, Rn direct, direct direct, @Ri direct, #data @Ri, A @Ri, direct @Ri, #data DPTR, #data16 A, @A+DPTR A, @A+PC A, @Ri A, @DPTR @Ri, A @DPTR, A direct direct A, Rn A, direct A, @Ri A, @Ri Description Move register to ACC Move direct byte to ACC Move indirect SRAM to ACC Move immediate data to ACC Move ACC to register Move direct byte to register Move immediate data to register Move ACC to direct byte Move register to direct byte Move direct byte to direct Move indirect SRAM to direct byte Move immediate data to direct byte Move ACC to indirect SRAM Move direct byte to indirect SRAM Move immediate data to indirect SRAM Load Data Pointer with 16-bit constant Move code byte relative to DPTR to ACC Move code byte relative to PC to ACC Move XDATA (8-bit addr) to ACC Move XDATA (16-bit addr) to ACC Move ACC to XDATA (8-bit addr) Move ACC to XDATA (16-bit addr) Push direct byte onto stack Pop direct byte from stack Exchange register with ACC Exchange direct byte with ACC Exchange indirect SRAM with ACC Exchange low-order digit indirect SRAM with ACC Length/Cycles 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 2 byte/2 cycle 2 byte/1 cycle 2 byte/1 cycle 2 byte/2 cycle 3 byte/2 cycle 2 byte/2 cycle 3 byte/2 cycle 1 byte/1 cycle 2 byte/2 cycle 2 byte/1 cycle 3 byte/2 cycle 1 byte/2 cycle 1 byte/2 cycle 1 byte/2 cycle 1 byte/2 cycle 1 byte/2 cycle 1 byte/2 cycle 2 byte/2 cycle 2 byte/2 cycle 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 1 byte/1 cycle
Note: 1. All mnemonics copyrighted Intel Corporation 1980.
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Table 9. Boolean Variable Manipulation Instruction Set
Mnemonic(1) and Use CLR CLR SETB SETB CPL CPL A NL A NL O RL O RL MOV MOV JC JNC JB JNB JBC C bit C bit C bit C, bit C, /bit C, bit C, /bit C, bit bit, C rel rel rel rel bit, rel Clear carry Clear direct bit Set carry Set direct bit Compliment carry Compliment direct bit AND direct bit to carry AND compliment of direct bit to carry OR direct bit to carry OR compliment of direct bit to carry Move direct bit to carry Move carry to direct bit Jump if carry is set Jump if carry is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Description Length/Cycles 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 1 byte/1 cycle 2 byte/1 cycle 2 byte/2 cycle 2 byte/2 cycle 2 byte/2 cycle 2 byte/2 cycle 2 byte/1 cycle 2 byte/2 cycle 2 byte/2 cycle 2 byte/2 cycle 3 byte/2 cycle 3 byte/2 cycle 3 byte/2 cycle
Note: 1. All mnemonics copyrighted Intel Corporation 1980.
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Table 10. Program Branching Instruction Set
Mnemonic(1) and Use ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ CJNE CJNE CJNE CJNE DJNZ DJNZ addr11 addr16 rel @A+DPTR rel rel A, direct, rel A, #data, rel Rn, #data, rel @Ri, #data, rel Rn, rel direct, rel addr11 addr16 Description Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative addr) Jump indirect relative to the DPTR Jump if ACC is zero Jump if ACC is not zero Compare direct byte to ACC, jump if not equal Compare immediate to ACC, jump if not equal Compare immediate to register, jump if not equal Compare immediate to indirect, jump if not equal Decrement register and jump if not zero Decrement direct byte and jump if not zero Length/Cycles 2 byte/2 cycle 3 byte/2 cycle 1 byte/2 cycle 1 byte/2 cycle 2 byte/2 cycle 3 byte/2 cycle 2 byte/2 cycle 1 byte/2 cycle 2 byte/2 cycle 2 byte/2 cycle 3 byte/2 cycle 3 byte/2 cycle 3 byte/2 cycle 3 byte/2 cycle 2 byte/2 cycle 3 byte/2 cycle
Note: 1. All mnemonics copyrighted Intel Corporation 1980.
Table 11. Miscellaneous Instruction Set
Mnemonic(1) and Use NOP No Operation Description Length/Cycles 1 byte/1 cycle
Note: 1. All mnemonics copyrighted Intel Corporation 1980.
Table 12. Notes on Instruction Set and Addressing Modes
Rn direct @ Ri #data #data16 addr16 addr11 rel bit Register R0 - R7 of the currently selected register bank. 8-bit address for internal 8032 DATA SRAM (locations 00h - 7Fh) or SFR registers (locations 80h - FFh). 8-bit internal 8032 SRAM (locations 00h - FFh) addressed indirectly through contents of R0 or R1. 8-bit constant included within the instruction. 16-bit constant included within the instruction. 16-bit destination address used by LCALL and LJMP. 11-bit destination address used by ACALL and AJMP. Signed (two-s compliment) 8-bit offset byte. Direct addressed bit in internal 8032 DATA SRAM (locations 20h to 2Fh) or in SFR registers (88h, 90h, 98h, A8h, B0, B8h, C0h, C8h, D0h, D8h, E0h, F0h).
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DUAL DATA POINTERS
XDATA is accessed by the External Direct addressing mode, which uses a 16-bit address stored in the DPTR Register. Traditional 8032 architecture has only one DPTR Register. This is a burden when transferring data between two XDATA locations because it requires heavy use of the working registers to manipulate the source and destination pointers. However, the uPSD33xx has two data pointers, one for storing a source address and the other for storing a destination address. These pointers can be configured to automatically increment or decrement after each data transfer, further reducing the burden on the 8032 and making this kind of data movement very efficient. Data Pointer Control Register, DPTC (85h) By default, the DPTR Register of the uPSD33xx will behave no different than in a standard 8032 MCU. The DPSEL0 Bit of SFR register DPTC shown in Table 13, selects which one of the two "background" data pointer registers (DPTR0 or DPTR1) will function as the traditional DPTR Register at any given time. After reset, the DPSEL0 Bit is cleared, enabling DPTR0 to function as the DPTR, and firmware may access DPTR0 by reading or writing the traditional DPTR Register at SFR addresses 82h and 83h. When the DPSEL0 bit is set, then the DPTR1 Register functions as DPTR, and firmware may now access DPTR1 through SFR registers at 82h and 83h. The pointer which is not selected by the DPSEL0 bit remains in the background and is not accessible by the 8032. If the DPSEL0 bit is never set, then the uPSD33xx will behave like a traditional 8032 having only one DPTR Register. To further speed XDATA to XDATA transfers, the SFR bit, AT, may be set to automatically toggle the two data pointers, DPTR0 and DPTR1, each time the standard DPTR Register is accessed by a MOVX instruction. This eliminates the need for firmware to manually manipulate the DPSEL0 bit between each data transfer. Detailed description for the SFR register DPTC is shown in Table 13.
Table 13. DPTC: Data Pointer Control Register (SFR 85h, reset value 00h)
Bit 7 Details Bit 7 6 5-1 0 Symbol AT DPSE0 R/W R,W R,W Reser ved 0 = Manually Select Data Pointer 1 = Auto Toggle between DPTR0 and DPTR1 Reser ved 0 = DPTR0 Selected for use as DPTR 1 = DPTR1 Selected for use as DPTR Definition Bit 6 AT Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DPSEL0
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Data Pointer Mode Register, DPTM (86h) The two "background" data pointers, DPTR0 and DPTR1, can be configured to automatically increment, decrement, or stay the same after a MOVX instruction accesses the DPTR Register. Only the currently selected pointer will be affected by the increment or decrement. This feature is controlled by the DPTM Register defined in Table 14. The automatic increment or decrement function is effective only for the MOVX instruction, and not MOVC or any other instruction that uses the DTPR Register.
Firmware Example. The 8051 assembly code illustrated in Table 15 shows how to transfer a block of data bytes from one XDATA address region to another XDATA address region. Auto-address incrementing and auto-pointer toggling will be used.
Table 14. DPTM: Data Pointer Mode Register (SFR 86h, reset value 00h)
Bit 7 Details Bit 7-4 Symbol R/W DPTR1 Mode Bits 3-2 MD[11:10] R,W 00: DPTR1 No Change 01: Reserved 10: Auto Increment 11: Auto Decrement DPTR0 Mode Bits 1-0 MD[01:00] R,W 00: DPTR0 No Change 01: Reserved 10: Auto Increment 11: Auto Decrement Definition Reser ved Bit 6 Bit 5 Bit 4 Bit 3 M D1 1 Bit 2 M D1 0 Bit 1 MD01 Bit 0 MD00
Table 15. 8051 Assembly Code Example
MOV MOV MOV MOV MOV MOV LOOP: MOVX(1) R7, #COUNT DPTR, #SOURCE_ADDR 85h, #01h DPTR, #DEST_ADDR 85h, #40h 86h, #0Ah A, @DPTR ; initialize size of data block to transfer ; load XDATA source address base into DPTR0 ; load DPTC to access DPTR1 pointer ; load XDATA destination address base into DPTR1 ; load DPTC to access DPTR0 pointer and auto toggle ; load DPTM to auto-increment both pointers ; load XDATA byte from source into ACC. ; after load completes, DPTR0 increments and DPTR ; switches DPTR1 ; store XDATA byte from ACC to destination. ; after store completes, DPTR1 increments and DPTR ; switches to DPTR0 ; continue until done ; disable auto-increment ; disable auto-toggle, now back to single DPTR mode
MOVX(1)
@DPTR, A
DJNZ(1) MOV MOV
R7, LOOP 86h, #00 85h, #00
Note: 1. The code loop where the data transfer takes place is only 3 lines of code.
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DEBUG UNIT
The 8032 MCU Module supports run-time debugging through the JTAG interface. This same JTAG interface is also used for In-System Programming (ISP) and the physical connections are described in the PSD Module section, JTAG ISP and JTAG Debug, page 195. Debugging with a serial interface such as JTAG is a non-intrusive way to gain access to the internal state of the 8032 MCU core and various memories. A traditional external hardware emulator cannot be completely effective on the uPSD33xx because of the Pre-Fetch Queue and Branch Cache. The nature of the PFQ and BC hide the visibility of actual program flow through traditional external bus connections, thus requiring on-chip serial debugging instead. Debugging is supported by Windows PC based software tools used for 8051 code development from 3rd party vendors listed at www.st.com/psm. Debug capabilities include: H alt or Start MCU execution R eset the MCU Single Step 3 Match Breakpoints 1 Range Breakpoint (inside or outside range) Program Tracing R ead or Modify MCU core registers, DATA, IDATA, SFR, XDATA, and Code External Debug Event Pin, Input or Output Some key points regarding use of the JTAG Debugger. The JTAG Debugger can access MCU registers, data memory, and code memory while the MCU is executing at full speed by cycle-stealing. This means "watch windows" may be displayed and periodically updated on the PC during full speed operation. Registers and data content may also be modified during full speed operation. There is no on-chip storage for Program Trace data, but instead this data is scanned from the uPSD33xx through the JTAG channel at runtime to the PC host for proccessing. As such, full speed program tracing is possible only when the 8032 MCU is operating below approximately one MIPS of performance. Above one MIPS, the program will not run real-time while tracing. One MIPS performance is determined by the combination of choice for MCU clock frequency, and the bit settings in SFR registers BUSCON and CCON0. Breakpoints can optionally halt the MCU, and/ or assert the external Debug Event pin. Breakpoint definitions may be qualified with read or write operations, and may also be qualified with an address of code, SFR, DATA, IDATA, or XDATA memories. Three breakpoints will compare an address, but the fourth breakpoint can compare an address and also data content. Additionally, the fouth breakpoint can be logically combined (AND/OR) with any of the other three breakpoints. The Debug Event pin can be configured by the PC host to generate an output pulse for external triggering when a break condition is met. The pin can also be configured as an event input to the breakpoint logic, causing a break on the falling-edge of an external event signal. If not used, the Debug Event pin should be pulled up to VCC as described in the section, Debugging the 8032 MCU Module., page 201. The duration of a pulse, generated when the Event pin configured as an output, is one MCU clock cycle. This is an active-low signal, so the first edge when an event occurs is high-to-low. The clock to the Watchdog Timer, ADC, and I2C interface are not stopped by a breakpoint halt. The Watchdog Timer should be disabled while debugging with JTAG, else a reset will be generated upon a watchdog time-out.
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INTERRUPT SYSTEM
The uPSD33xx has an 11-source, two priority level interrupt structure summarized in Table 16. Firmware may assign each interrupt source either high or low priority by writing to bits in the SFRs named, IP and IPA, shown in Table 16. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority interrupt is being serviced, it will be stopped and the new interrupt is serviced. When the new interrupt is finished, the lower priority interrupt that was stopped will be completed. If new interrupt requests are of the same priority level and are received simultaneously, an internal polling sequence determines which request is selected for service. Thus, within each of the two priority levels, there is a second priority structure determined by the polling sequence. Firmware may individually enable or disable interrupt sources by writing to bits in the SFRs named, IE and IEA, shown in Table 16., page 41. The SFR named IE contains a global disable bit (EA), which can be cleared to disable all 11 interrupts at once, as shown in Table 17., page 43. Figure 13., page 42 illustrates the interrupt priority, polling, and enabling process. Each interrupt source has at least one interrupt flag that indicates whether or not an interrupt is pending. These flags reside in bits of various SFRs shown in Table 16., page 41. All of the interrupt flags are latched into the interrupt control system at the beginning of each MCU machine cycle, and they are polled at the beginning of the following machine cycle. If polling determines one of the flags was set, the interrupt control system automatically generates an LCALL to the user's Interrupt Service Routine (ISR) firmware stored in program memory at the appropriate vector address. The specific vector address for each of the interrupt sources are listed in Table 16., page 41. However, this LCALL jump may be blocked by any of the following conditions: An interrupt of equal or higher priority is already in progress The current machine cycle is not the final cycle in the execution of the instruction in progress The current instruction involves a write to any of the SFRs: IE, IEA, IP, or IPA The current instruction is an RETI Note: Interrupt flags are polled based on a sample taken in the previous MCU machine cycle. If an interrupt flag is active in one cycle but is denied serviced due to the conditions above, and then later it is not active when the conditions above are finally satisfied, the previously denied interrupt will not be serviced. This means that active interrupts are not remembered. Every poling cycle is new. Assuming all of the listed conditions are satisfied, the MCU executes the hardware generated LCALL to the appropriate ISR. This LCALL pushes the contents of the PC onto the stack (but it does not save the PSW) and loads the PC with the appropriate interrupt vector address. Program execution then jumps to the ISR at the vector address. Execution precedes in the ISR. It may be necessary for the ISR firmware to clear the pending interrupt flag for some interrupt sources, because not all interrupt flags are automatically cleared by hardware when the ISR is called, as shown in Table 16., page 41. If an interrupt flag is not cleared after servicing the interrupt, an unwanted interrupt will occur upon exiting the ISR. After the interrupt is serviced, the last instruction executed by the ISR is RETI. The RETI informs the MCU that the ISR is no longer in progress and the MCU pops the top two bytes from the stack and loads them into the PC. Execution of the interrupted program continues where it left off. Note: An ISR must end with a RETI instruction, not a RET. An RET will not inform the interrupt control system that the ISR is complete, leaving the MCU to think the ISR is still in progress, making future interrupts impossible.
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Table 16. Interrupt Summary
Inte rrupt Source Polling Vector Priority Addr Flag Bit Name (SFR.bit position) 1 = Intr Pending 0 = No Interrupt IE0 (TCON.1) TF0 (TCON.5) IE1 (TCON.3 TF1 (TCON.7) RI (SCON0.0) TI (SCON0.1) TF2 (T2CON.7) EXF2 (T2CON.6) TEISF, RORISF, TISF, RISF (SPISTAT[3:0]) INTR (S1STA.5) AINTF (ACON.7) OFVx, INTFx (PCASTA[0:7]) RI (SCON1.0) TI (SCON1.1) Flag Bit AutoCleared by Hardware? Edge - Yes Level - No Yes Edge - Yes Level - No Yes No Enable Bit Name (SFR.bit position) 1 = Intr Enabled 0 = Intr Disabled EX0 (IE.0) ET0 (IE.1) EX1 (IE.2) ET1 (IE.3) ES0 (IE.4) Priority Bit Name (SFR.bit position) 1= High Priority 0 = Low Priority PX0 (IP.0) PT0 (IP.1) PX1 (IP.2) PT1 (IP.3) PS0 (IP.4)
Reserved External Interrupt INT0 Timer 0 Overflow External Interrupt INT1 Timer 1 Overflow UART0 Timer 2 Overflow or TX2 Pin SPI Reserved I2C A DC P CA UART1
0 (high) 1 2 3 4 5
0063h 0003h 000Bh 0013h 001Bh 0023h
6
002Bh
No
ET2 (IE.5)
PT2 (IP.5)
7 8 9 10 11 12 (low)
0053h 0033h 0043h 003Bh 005Bh 004Bh
Yes Yes No No No
ESPI (IEA.6) EI2C (IEA.1) EADC (IEA.7) EPCA (IEA.5) ES1 (IEA.4)
PSPI (IPA.6) PI2C (IPA.1) PADC (IPA.7) PPCA (IPA.5) PS1 (IPA.4)
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Figure 13. Enabling and Polling Interrupts
Interrupt Sources Reser ved Priority IE/IEA IP/IPA High Low
Ext INT0 Timer 0 Ext INT1
Timer 1
UART0 Interrupt Polling Sequence
Timer 2
SPI
USB
IC
2
ADC
PCA
UART1
Global Enable
AI07844
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Individual Interrupt Sources External Interrupts Int0 and Int1. External interrupt inputs on pins EXTINT0 and EXTINT1 (pins 3.2 and 3.3) are either edge-triggered or level-triggered, depending on bits IT0 and IT1 in the SFR named TCON. When an external interrupt is generated from an edge-triggered (falling-edge) source, the appropriate flag bit (IE0 or IE1) is automatically cleared by hardware upon entering the ISR. When an external interrupt is generated from a level-triggered (low-level) source, the appropriate flag bit (IE0 or IE1) is NOT automatically cleared by hardware. Timer 0 and 1 Overflow Interrupt. Timer 0 and Timer 1 interrupts are generated by the flag bits TF0 and TF1 when there is an overflow condition in the respective Timer/Counter register (except for Timer 0 in Mode 3). Timer 2 Overflow Interrupt. This interrupt is generated to the MCU by a logical OR of flag bits, TF2 and EXE2. The ISR must read the flag bits to determine the cause of the interrupt. TF2 is set by an overflow of Timer 2. EXE2 is generated by the falling edge of a signal on the external pin, T2X (pin P1.1). UART0 and UART1 Interrupt. Each of the UAR Ts have identical interrupt structure. For each UAR T, a single interrupt is generated to the MCU by the logical OR of the flag bits, RI (byte received) and TI (byte transmitted).
The ISR must read flag bits in the SFR named SCON0 for UART0, or SCON1 for UART1 to determine the cause of the interrupt. SPI Interrupt. The SPI interrupt has four interrupt sources, which are logically ORed together when interrupting the MCU. The ISR must read the flag bits to determine the cause of the interrupt. A flag bit is set for: end of data transmit (TEISF); data receive overrun (RORISF); transmit buffer empty (TISF); or receive buffer full (RISF). I2C Interrupt. The flag bit INTR is set by a variety of conditions occurring on the I2C interface: received own slave address (ADDR flag); received general call address (GC flag); received STOP condition (STOP flag); or successful transmission or reception of a data byte.The ISR must read the flag bits to determine the cause of the interrupt. ADC Interrupt. The flag bit AINTF is set when an A-to-D conversion has completed. PCA Interrupt. The PCA has eight interrupt sources, which are logically ORed together when interrupting the MCU.The ISR must read the flag bits to determine the cause of the interrupt. Each of the six TCMs can generate a "match or capture" interrupt on flag bits OFV5..0 respectively. Each of the two 16-bit counters can generate an overflow interrupt on flag bits INTF1 and INTF0 respectively. Tables 17 through Table 20., page 45 have detailed bit definitions of the interrupt system SFRs.
Table 17. IE: Interrupt Enable Register (SFR A8h, reset value 00h)
Bit 7 EA Details Bit 7 Symbol EA R/W R,W Function Global disable bit. 0 = All interrupts are disabled. 1 = Each interrupt source can be individually enabled or disabled by setting or clearing its enable bit. Do not modify this bit. It is used by the JTAG debugger for instruction tracing. Always read the bit and write back the same bit value when writing this SFR. Enable Timer 2 Interrupt Enable UART0 Interrupt Enable Timer 1 Interrupt Enable External Interrupt INT1 Enable Timer 0 Interrupt Enable External Interrupt INT0 Bit 6 Bit 5 ET2 Bit 4 ES0 Bit 3 ET1 Bit 2 EX1 Bit 1 ET0 Bit 0 EX0
6 5(1) 4(1) 3(1) 2(1) 1
(1)
ET2 ES0 ET1 EX1 ET0 EX0
R,W R,W R,W R,W R,W R,W R,W
0(1)
Note: 1. 1 = Enable Interrupt, 0 = Disable Interrupt
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Table 18. IEA: Interrupt Enable Addition Register (SFR A7h, reset value 00h)
Bit 7 EADC Details Bit 7(1) 6(1) 5(1) 4(1) 3 2 1
(1)
Bit 6 ESPI
Bit 5 EPCA
Bit 4 ES1
Bit 3
Bit 2
Bit 1 EI2C
Bit 0
Symbol EADC ESPI EPCA ES1 EI C
2
R/W R,W R,W R,W R,W R,W Enable ADC Interrupt Enable SPI Interrupt
Function
Enable Programmable Counter Array Interrupt Enable UART1 Interrupt Reser ved, do not set to logic '1.' Reser ved, do not set to logic '1.' Enable I2C Interrupt Reser ved, do not set to logic '1.'
0
Note: 1. 1 = Enable Interrupt, 0 = Disable Interrupt
Table 19. IP: Interrupt Priority Register (SFR B8h, reset value 00h)
Bit 7 Details Bit 7 6 5(1) 4(1) 3(1) 2(1) 1(1) 0(1) Symbol PT2 PS0 PT1 PX1 PT0 PX0 R/W R,W R,W R,W R,W R,W R,W Reser ved Reser ved Timer 2 Interrupt priority level UART0 Interrupt priority level Timer 1 Interrupt priority level External Interrupt INT1 priority level Timer 0 Interrupt priority level External Interrupt INT0 priority level Function Bit 6 Bit 5 PT2 Bit 4 PS0 Bit 3 PT1 Bit 2 PX1 Bit 1 PT0 Bit 0 PX0
Note: 1. 1 = Assigns high priority level, 0 = Assigns low priority level
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Table 20. IPA: Interrupt Priority Addition register (SFR B7h, reset value 00h)
Bit 7 PADC Details Bit 7(1) 6(1) 5(1) 4(1) 3 2 1
(1)
Bit 6 PSPI
Bit 5 PPCA
Bit 4 PS1
Bit 3
Bit 2
Bit 1 PI2C
Bit 0
Symbol PADC PSPI PPCA PS1 PI C
2
R/W R,W R,W R,W R,W R,W ADC Interrupt priority level SPI Interrupt priority level PCA Interrupt level UART1 Interrupt priority level Reser ved Reser ved I2C Interrupt priority level Reser ved
Function
0
Note: 1. 1 = Assigns high priority level, 0 = Assigns low priority level
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uPSD33xx
MCU CLOCK GENERATION
Internal system clocks generated by the clock generation unit are derived from the signal, XTAL1, shown in Figure 14. XTAL1 has a frequency fOSC, which comes directly from the external crystal or oscillator device. The SFR named CCON0 (Table 21., page 47) controls the clock generation unit. There are two clock signals produced by the clock generation unit: M C U _ C LK PERIPH _CLK MCU_CLK This clock drives the 8032 MCU core and the Watchdog Timer (WDT). The frequency of MCU_CLK is equal to fOSC by default, but it can be divided by as much as 2048, shown in Figure 14. The bits CPUPS[2:0] select one of eight different divisors, ranging from 2 to 2048. The new frequency is available immediately after the CPUPS[2:0] bits are written. The final frequency of MCU_CLK is fMCU. MCU_CLK is blocked by either bit, PD or IDL, in the SFR named PCON during MCU Power-down Mode or Idle Mode respectively. MCU_CLK clock can be further divided as required for use in the WDT. See details of the WDT in SUPERVISORY FUNCTIONS, page 65 . PERIPH_CLK This clock drives all the uPSD33xx peripherals except the WDT. The Frequency of PERIPH_CLK is always fOSC. Each of the peripherals can indepenFigure 14. Clock Generation Logic
PCON[1]: PD, Power-Down Mode PCON[2:0]: CPUPS[2:0], Clock Pre-Scaler Select
3 XTAL1 (default) 0 1 2 3 4 5 6 7
dently divide PERIPH_CLK to scale it appropriately for use. PERIPH_CLK runs at all times except when blocked by the PD bit in the SFR named PCON during MCU Power-down Mode. JTAG Interface Clock. The JTAG interface for ISP and for Debugging uses the externally supplied JTAG clock, coming in on pin TCK. This means the JTAG ISP interface is always available, and the JTAG Debug interface is available when enabled, even during MCU Idle mode and Powerdown Mode. However, since the MCU participates in the JTAG debug process, and MCU_CLK is halted during Idle and Power-down Modes, the majority of debug functions are not available during these low power modes. But the JTAG debug interface is capable of executing a reset command while in these low power modes, which will exit back to normal operating mode where all debug commands are available again. The CCON0 SFR contains a bit, DBGCE, which enables the breakpoint comparators inside the JTAG Debug Unit when set. DBGCE is set by default after reset, and firmware may clear this bit at run-time. Disabling these comparators will reduce current consumption on the MCU Module, and it's recommended to do so if the Debug Unit will not be used (such as in the production version of an end-produc t ) .
PCON[0]: IDL, Idle Mode
XTAL1 (fOSC)
Q Q Q Q Q Q Q
XTAL1 /2 XTAL1 /4 XTAL1 /8 XTAL1 /16 XTAL1 /32 XTAL1 /1024 XTAL1 /2048
MCU_CLK (fMCU) M U X (to: 8032, WDT)
Clock Divider PERIPH_CLK (fOSC) (to: TIMER0/1/2, UART0/1, PCA0/1, SPI, I2C, ADC)
AI09197
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Table 21. CCON0: Clock Control Register (SFR F9h, reset value 10h)
Bit 7 Details Bit 7 6 5 Symbol R/W Reser ved Reser ved Reser ved Debug Unit Breakpoint Comparator Enable 4 DBGCE R,W 0 = JTAG Debug Unit comparators are disabled 1 = JTAG Debug Unit comparators are enabled (Default condition after reset) Automatic MCU Clock Recovery 3 CPUAR R,W 0 = There is no change of CPUPS[2:0] when an interrupt occurs. 1 = Contents of CPUPS[2:0] automatically become 000b whenever any interrupt occurs. MCUCLK Pre-Scaler 000b: 001b: 010b: 011b: 100b: 101b: 110b: 111b: fMCU = fOSC (Default after reset) fMCU = fOSC/2 fMCU = fOSC/4 fMCU = fOSC/8 fMCU = fOSC/16 fMCU = fOSC/32 fMCU = fOSC/1024 fMCU = fOSC/2048 Definition Bit 6 Bit 5 Bit 4 DBGCE Bit 3 CPUAR Bit 2 Bit 1 CPUPS[2:0] Bit 0
2:0
CPUPS
R,W
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uPSD33xx
POWER SAVING MODES
The uPSD33xx is a combination of two die, or modules, each module having it's own current consumption characteristics. This section describes reduced power modes for the MCU Module. See the section, Power Management, page 137 for reduced power modes of the PSD Module. Total current consumption for the combined modules is determined in the DC specifications at the end of this document. The MCU Module has three software-selectable modes of reduced power operation. Idle Mode Power-down Mode R educed Frequency Mode Idle Mode Idle Mode will halt the 8032 MCU core while leaving the MCU peripherals active (Idle Mode blocks MCU_CLK only). For lowest current consumption in this mode, it is recommended to disable all unused peripherals, before entering Idle mode (such as the ADC and the Debug Unit breakpoint comparators). The following functions remain fully active during Idle Mode (except if disabled by SFR settings). External Interrupts INT0 and INT1 Timer 0, Timer 1 and Timer 2 Supervisor reset from: LVD, JTAG Debug, External RESET_IN_, but not the WTD A DC I2C Interface U ART0 and UART1 Interfaces SPI Interface Programmable Counter Array An interrupt generated by any of these peripherals, or a reset generated from the supervisor, will cause Idle Mode to exit and the 8032 MCU will resume normal operation. The output state on I/O pins of MCU ports 1, 3, and 4 remain unchanged during Idle Mode. To enter Idle Mode, the 8032 MCU executes an instruction to set the IDL bit in the SFR named PCON, shown in Table 24., page 50. This is the last instruction executed in normal operating mode before Idle Mode is activated. Once in Idle Mode, the MCU status is entirely preserved, and there are no changes to: SP, PSW, PC, ACC, SFRs, DATA, IDATA, or XDATA. The following are factors related to Idle Mode exit: Activation of any enabled interrupt will cause the IDL bit to be cleared by hardware, terminating Idle Mode. The interrupt is serviced, and following the Return from Interrupt instruction (RETI), the next instruction to be executed will be the one which follows the instruction that set the IDL bit in the PCON SFR. After a reset from the supervisor, the IDL bit is cleared, Idle Mode is terminated, and the MCU restarts after three MCU machine cycles. Power-down Mode Power-down Mode will halt the 8032 core and all MCU peripherals (Power-down Mode blocks MCU_CLK and PERIPH_CLK). This is the lowest power state for the MCU Module. When the PSD Module is also placed in Power-down mode, the lowest total current consumption for the combined die is achieved for the uPSD33xx. See Power Management, page 137 in the PSD Module section for details on how to also place the PSD Module in Power-down mode. The sequence of 8032 instructions is important when placing both modules into Power-down Mode. The instruction that sets the PD Bit in the SFR named PCON (Table 24., page 50) is the last instruction executed prior to the MCU Module going into Power-down Mode. Once in Power-down Mode, the on-chip oscillator circuitry and all clocks are stopped. The SFRs, DATA, IDATA, and XD ATA are preserved. Power-down Mode is terminated only by a reset from the supervisor, originating from the RESET_IN_ pin, the Low-Voltage Detect circuit (LVD ), or a JTAG Debug reset command. Since the clock to the WTD is not active during Powerdown mode, it is not possible for the supervisor to generate a WDT reset. Table 22., page 49 summarizes the status of I/O pins and peripherals during Idle and Power-down Modes on the MCU Module. Table 23., page 49 shows the state of 8032 MCU address, data, and control signals during these modes. Reduced Frequency Mode The 8032 MCU consumes less current when operating at a lower clock frequency. The MCU can reduce it's own clock frequency at run-time by writing to three bits, CPUPS[2:0], in the SFR named CCON0 described in Table 21., page 47. These bits effectively divide the clock frequency (fOSC) coming in from the external crystal or oscillator device. The clock division range |
