ST92195 ST92T195 ST92E195
48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER
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Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW and HALT modes 0C to +70C operating temperature range Up to 24 MHz. operation @ 5V10% Min. instruction cycle time: 165ns at 24 MHz. 48, 56, 64, 84 or 96 Kbytes ROM 256 bytes RAM of Register file (accumulators or index registers) 256 to 512 bytes of on-chip static RAM 2 or 8 Kbytes of TDSRAM (Teletext and Display Storage RAM) 28 fully programmable I/O pins Serial Peripheral Interface Flexible Clock controller for OSD, Data Slicer and Core clocks running from a single low frequency external crystal. Enhanced display controller with 26 rows of 40/80 characters 2 sets of 512 characters Serial and Parallel attributes 10x10 dot matrix, definable by user 4/3 and 16/9 supported in 50/60Hz and 100/ 120 Hz mode Rounding, fringe, double width, double height, scrolling, cursor, full background color, halfintensity color, translucency and half-tone m odes Teletext unit, including Data Slicer, Acquisition Unit and up to 8 Kbytes RAM for data storage VPS and Wide Screen Signalling slicer Integrated Sync Extractor and Sync Controller 14-bit Voltage Synthesis for tuning reference voltage Up to 6 external interrupts plus one NonMaskable Interrupt 8 x 8-bit programmable PWM outputs with 5V open-drain or push-pull capability 16-bit watchdog timer with 8-bit prescaler 1 or 2 16-bit standard timer(s) with 8-bit prescaler
PSDIP56
TQFP64
See end of Datasheet for ordering information
I²C Master/Slave (on some devices) 4-channel A/D converter; 5-bit guaranteed s Rich instruction set and 14 addressing modes s Versati le development tools, including Assembler, Linker, C-compiler, Archiver, Source Level Debugger and hardware emulators with Real-Time Operating System available from third parties s Pin-com patible EPROM and OTP devices available Device Summary
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Device ST92195C3 ST92195C4 ST92195C5 ST92195C6 ST92195C7 ST92195C8 ST92195C9 ST92195D5 ST92195D6 ST92195D7
ROM 48K 56K 64K 84K 96K 48K 56K 64K
RAM TDSRAM 256 2K 6K
I²C
Timer
512
No 8K
1
512
8K
Yes
2
October 2003
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Table of Contents
ST92195C/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.1 ST9+ Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.3 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.4 TV Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.5 On Screen Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.6 Teletext and Display Storage RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.7 Teletext, VPS and WSS Data Slicers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.8 Voltage Synthesis Tuning Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.9 PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.10 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.11 Standard Timer (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.12 I²C Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.13 Analog/Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.1 I/O Port Alternate Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.1 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.2 Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.1 Central Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 Register Pointing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 Paged Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.6 Stack Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 28 29 32 32 33 35
2.5 MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6 ADDRESS SPACE EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.6.1 Addressing 16-Kbyte Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.6.2 Addressing 64-Kbyte Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.7 MMU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.7.1 DPR[3:0]: Data Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.2 CSR: Code Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.3 ISR: Interrupt Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.4 DMASR : DMA Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 MMU USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 2.8.1 Normal Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 40 40 40 42 42 42
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2.8.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2 INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2.1 Divide by Zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2.2 Segment Paging During Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4 PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4.1 Priority Level 7 (Lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Maximum Depth of Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Simultaneous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Dynamic Priority Level Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 44 45 45 45
3.5.1 Concurrent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.5.2 Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.7 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.8 ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.9 INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.10 INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4 RESET AND CLOCK CONTROL UNIT (RCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2 RESET / STOP MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 OSC ILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.4 CLOCK CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.5 RESET CONTROL UNIT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5 TIMING AND CLOCK CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1 FREQUENCY MULTIPLIERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.2.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.2 SPECIFIC PORT CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3 POR T CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.4 INPUT/OUTPU T BIT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.5 ALTER NATE FUNCTION ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.5.1 Pin Declared as I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.5.2 Pin Declared as an Alternate Function Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.5.3 Pin Declared as an Alternate Function Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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6.6 I/O STATUS AFTER WFI, HALT AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.1 TIMER/W ATCHDOG (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.4 WD T Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 STANDARD TIMER (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.4 Register Mappingl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 TELETEXT DISPLAY STORAGE RAM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.3 Initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 ON SCREEN DISPLAY (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. 4. 1 7. 4. 2 7. 4. 3 7. 4. 4 7. 4. 5 7. 4. 6 7. 4. 7 7. 4. 8 7. 4. 9 7. 4. 10 7.5 SYNC 7. 5. 1 7. 5. 2 7. 5. 3 7. 5. 4 7. 5. 5 7.6 SYNC 74 75 76 78 79 81 81 82 83 83 84 85 85 86 89 90 93
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Programming the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Vertical Scrolling Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Display Memory Mapping Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Font Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Font Mapping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Application Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 H/V Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sync Controller Working Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXTRACTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 140 140 140 143 145 145 145 145 145 145 146
7.6.1 Time Windowing For Slicers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.2 Field Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.3 CVBS Amplitude Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.4 CVBS Signal Quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.5 Sync Extractor Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 TELETEXT SLICER AND ACQUISITION UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. 7. 1 7. 7. 2 7. 7. 3 7. 7. 4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Teletext Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 147 ... Acquisition Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
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7.7.5 Hamming Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.6 Teletext Signal Quality Measure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 VPS & WSS SLICER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.2 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.3 About Video Programming System (VPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.4 About Wide-Screen-Signaling (WSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.5 WSS Signal Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.6 WSS Data Group Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.2 Device-Specific Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.4 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.5 Working With Other Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.6 I2C-bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.7 S-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.8 IM-bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10 TWO-CHANNEL I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10.2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10.4 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10.5 Error Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11 A/D CONVERTER (A/D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12 VOLTAGE SYNTHESIS TUNING CONVERTER (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12.2 Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.12.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.13 PWM GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.13.2 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 156 157 164 164 165 166 167 167 168 169 173 173 173 174 175 176 176 179 180 181 183 183 184 185 187 187 188 195 195 195 195 197 199 199 199 203 204 204 205 209 215 215
9.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 9.2.1 Transfer Of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
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ST92E195C/D-ST92T195C/D . . . . . . . . . . . . . . . . . . . . . . . . . 217
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0.1 ST9+ Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0.3 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0.4 TV Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0.5 On Screen Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0.6 Teletext and Display Storage RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0.7 Teletext, VPS and WSS Data Slicers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0.8 Voltage Synthesis Tuning Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0.9 PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0.10 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0.11 Standard Timer (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0.12 I²C Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0.13 Analog/Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 219 219 219 219 219 219 220 220 220 220 220 220 220 222
1.1.1 I/O Port Alternate Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 1.1.2 I/O Port Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 1.2 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 1.3 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 3 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 3.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 3.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 3.2.1 Tra nsfer Of OSD Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 4 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
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ST92 195 ST92T195 ST92E195 - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST92195C and ST92195D microcontrollers are developed and manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Their performance derives from the use of a flexible 256-register programming model for ultrafast context switching and real-time event response. The intelligent on-chip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical application tasks to get the maximum use of core resources. The ST92195C/D MCU support low power consumption and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 ST9+ Core The advanced Core consists of the Central Processing Unit (CPU), the Register File and the Interrupt controller. The general-purpose registers can be used as accumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges. Two basic addressable spaces are available: the Memory space and the Register File, which includes the control and status registers of the onchip peripherals. 1.1.2 Power Saving Modes To optimize performance versus power consumption, a range of operating modes can be dynamically selected. Run Mode. This is the full speed execution mode with CPU and peripherals running at the maximum clock speed delivered by the Phase Locked Loop (PLL) of the Clock Control Unit (CCU). Wait For Interrupt Mode. The Wait For Interrupt (WFI) instruction suspends program execution until an interrupt request is acknowledged. During WFI, the CPU clock is halted while the peripherals and interrupt controller keep running at a frequency programmable via the CCU. In this mode, the power consumption of the device can be reduced by more than 95% (Low power WFI). Halt Mode. When executing the HALT instruction, and if the Watchdog is not enabled, the CPU and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). A reset is necessary to exit from Halt m ode. 1.1.3 I/O Ports Up to 28 I/O lines are dedicated to digital Input/ Output. These lines are grouped into up to five I/O Ports and can be configured on a bit basis under software control to provide timing, status signals, timer and output, analog inputs, external interrupts and serial or parallel I/O. 1.1.4 TV Peripherals A set of on-chip peripherals form a complete system for TV set and VCR applications: Voltage Synthesis VPS/WSS Slicer Teletext Slicer Teletext Display RAM OSD 1.1.5 On Screen Display The human interface is provided by the On Screen Display module, this can produce up to 26 lines of up to 80 characters from a ROM of two 512-character sets. The character resolution is 10x10 dot. Four character sizes are supported. Serial attributes allow the user to select foreground and background colors, character size and fringe background. Parallel attributes can be used to select additional foreground and background colors and underline on a character by character basis. 1.1.6 Teletext and Display Storage RAM The internal Teletext and Display storage RAM can be used to store Teletext pages as well as Display parameters.
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ST92195 ST92T195 ST92E195 - GENERAL DESCRIPTION
INTRODUCTION (Cont'd) 1.1.7 Teletext, VPS and WSS Data Slicers The three on-board data slicers using a single external crystal are used to extract the Teletext, VPS and WSS information from the video signal. Hardware Hamming decoding is provided. 1.1.8 Voltage Synthesis Tuning Control 14-bit Voltage Synthesis using the PWM (Pulse Width Modulation)/BRM (Bit Rate Modulation) technique can be used to generate tuning voltages for TV set applications. The tuning voltage is output on one of two separate output pins. 1.1.9 PWM Output Control of TV settings can be made with up to eight 8-bit PWM outputs, with a maximum frequency of 23,437Hz at 8-bit resolution (INTCLK = 12 MHz). Low resolutions with higher frequency operation can be programmed. 1.1.10 Serial Peripheral Interface (SPI) The SPI bus is used to communicate with external devices via the SPI, or I²C bus communication standards. The SPI uses a single data line for data input and output. A second line is used for a synchronous clock signal. 1.1.11 Standard Timer (STIM) The ST92195C and ST92195D have one or two Standard Timer(s) that include a programmable 16-bit down counter and an associated 8-bit prescaler with Single and Continuous counting modes. 1.1.12 I²C Bus Interface The ST92195D versions have one I²C bus interface. The I²C bus is a synchronous serial bus for connecting multiple devices using a data line and a clock line. Multimaster and slave modes are supported. Up to two channels are supported. The I²C interface supports 7-bit addressing. It supports speeds of up to 800 KHz. Bus events (Bus busy, slave address recognised) and error conditions are automatically flagged in peripheral registers and interrupts are optionally generated. 1.1.13 Analog/Digital Converter (ADC) In addition there is a 4-channel Analog to Digital Converter with integral sample and hold, fast 5.75s conversion time and 6-bit guaranteed resolution.
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ST92 195 ST92T195 ST92E195 - GENERAL DESCRIPTION
INTRODUCTION (Cont'd) Figure 1. ST92195C/D Block Diagram
Up to 96 Kbytes ROM 256 or 512 bytes RAM Up to 8 Kbytes TRI TDSRAM MEMORY BUS I/O PORT 0
8
P0[7:0]
I/O PORT 2 I/O PORT 3 I/O PORT 4
6
P2[5:0]
4
P3[7:4]
256 bytes Register File 8/16-bit CPU
8
P4[7:0]
I/O PORT 5 DATA SLICER & ACQUISITION UNIT SYNC. EXTRACTION REGISTER BUS VPS/WSS DATA SLICER ADC
2
P5[1:0]
NMI INT[7:4] INT2 INT0
MMU Interrupt Management ST9+ CORE TXCF CVBS1
OSCIN OSCOUT RESET RESETO
RCCU 16-BIT TIMER/ WATCHDOG
WS CR WS CF CVBS2
SDO/SDI SCK
MCFM
SPI TIMING AND CLOCK CTRL VOLTAGE SYNTHESIS
AIN[4:1] EXTRG
VSYNC HSYNC/CSYNC CSO FREQ. PXFM MULTIP. R/G/B/FB TSLU HT
SYNC CONTROL ON SCREEN DISPLAY P WM D/A CONVERTER
VSO[2:1]
STOUT0 SDA1/SCL1 SDA2/SCL2
STANDARD TIMER 1) I²C 2)
PWM[7:0]
All alternate functions (Italic characters) are mapped on Ports 0, 2, 3, 4 and 5 Note 1: One standard timer on ST92195C devices, two standard timers on ST92195D devices Note 2: I²C available on ST92195D devices only
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ST92195 ST92T195 ST92E195 - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION Figure 2. 64-Pin Package Pin-Out
VDD P0.3 P0.4 P0.5 P0.6 P0.7 RESET P2.0/INT7 P2.1/INT5/AIN1 P2.2/INT0/AIN2 P2.3/INT6/VS01 P2.4/NMI P2.5/AIN3/INT4/VS02 OSCIN OSCOUT VDD GND AIN4/P0.2 P0.1 P0.0 CSO/RESET0/P3.7 P3.6 P3.5 P3.4 B G R FB SDA1/SDO/SDI/P5.1 SCL1/INT2/SCK/P5.0 VDD JTDO 1 64 48 16 32 VSS P4.7/PWM7/EXTRG/STOUT0 P4.6/PWM6 P4.5/PWM5/SDA2 P4.4/PWM4/SCL2 P4.3/PWM3/TSLU/HT P4.2/PWM2 P4.1/PWM1 P4.0/PWM0 VSYNC HSYNC/CSYNC AVDD1 PXFM JTRST0 GND N.C.
N.C. = Not connected
N.C. N.C. WSCF VPP/WSCR AVDD3 TEST0 MCFM JTCK TXCF CVBSO AVDD2 JTMS CVBS2 CVBS1 AGND N.C.
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ST92 195 ST92T195 ST92E195 - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont'd) Figure 3. 56-Pin Package Pin-Out
INT 7/P2.0 RESET P0.7 P0.6 P0.5 P0.4 P0.3 AIN4/P0.2 P0.1 P0.0 CSO/RESET 0/P3.7 P3.6 P3.5 P3.4 B G R FB SDA1/SDI/SDO/P5.1 SCL1/SCK/INT 2/P5.0 VDD J TD O WSCF VPP/WSCR AVDD3 TEST 0 MC FM JTCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P2.1/INT5/AIN1 P2.2/INT0/AIN2 P2.3/INT6/VS01 P2.4/NMI P2.5/AIN3/INT4/VS02 OSCIN OSCOUT P4.7/PWM7/EXTRG/ST OUT0 P4.6/PWM6 P4.5/PWM5/SDA2 P4.4/PWM4/SCL2 P4.3/PWM3/TSLU/HT P4.2/PWM2 P4.1/PWM1 P4.0/PWM0 VSYNC HSYNC/CSYNC AVDD1 P X FM JTRSTO GND AGND CVBS1 CVBS2 J TM S AVDD2 CVBSO TXCF
RESET Reset (input, active low). The ST9+ is initialised by the Reset signal. With the deactivation of RESET, program execution begins from the Program memory location pointed to by the vector contained in program memory locations 00h and 01h. R/G/B Red/Green/Blue. Video color analog DAC outputs. FB Fast Blanking. Video analog DAC output. VDD Main power supply voltage (5V10%, digital) WSCF, WSCR Analog pins for the VPS/WSS slicer . These pins must be tied to ground or not connected. VPP: On EPROM/OTP devices, the WSCR pin is replaced by V PP which is the programming voltage pin. V PP should be tied to GND in user mode. MCFM Analog pin for the display pixel frequency multiplier. OSCIN , OSCOUT Oscillator (input and output). These pins connect a parallel-resonant crystal (24MHz maximum), or an external source to the on-chip clock oscillator and buffer. OSCIN is the input of the oscillator inverter and internal clock generator; OSCOUT is the output of the oscillator inverter.
VSYNC Vertical Sync. Vertical video synchronisation input to OSD. Positive or negative polarity. HSYNC/CSYNC Horizontal/Composite sync. Horizontal or composite video synchronisation input to OSD. Positive or negative polarity. PXFM Analog pin for the Display Pixel Frequency Multiplier AVDD3 Analog V DD of PLL. This pin must be tied to VDD externally. GND Digital circuit ground. AGN D Analog circuit ground (must be tied externally to digital GND). CVBS1 Composite video input signal for the Teletext slicer and sync extraction. CVBS2 Composite video input signal for the VPS/ WSS slicer. Pin AC coupled. AVDD1, AVDD2 Analog power supplies (must be tied externally to AVDD3). TXCF Analog pin for the Teletext slicer line PLL. CVBSO, JTDO, JTCK Test pins: leave floating. TEST0 Test pins: must be tied to AVDD2. JTRST0 Test pin: must be tied to GND.
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+5V U1 P20 Y1 4Mhz C3 L1 10uH P47 P46 P45 P44 P43 P42 P41 P40 VSYNC HSYNC 39pF +5V C1 39pF
L2
10uH
PIN DESCRIPTION (Cont'd)
1F C2
R1
10k
P21 P22 P23 P24 P25
S1
D1
RST
1N4148
P07 P06 P05 P04 P03 P02 P01 P00 P37 P36 P35 P34 B G R FB P51 P50 C5 100nF 10F C7 C8 R2 5.6k 22pF 4.7nF C10
C4
10F
C6
100nF
C9
100nF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 P2.0/INT7 RESETN P0.7 P0.6 P0.5 P0.4 P0.3 P0.2/AIN4 P0.1 P0.0 P3.7/RESET0/CSO P3.6 P3.5 P3.4 B G R FB P5.1/SDI/SDO P5.0/SCK/INT2 VDD JTDO WSCF WSCR AVDD3 TEST0 MCFM JTCK SDIP56 470nF C12 C14 C15 CVBS 82pF 100nF 15k R4 2.2nF C16 P2.1/INT5/AIN1 P2.2/INT0/AIN2 P2.3/INT6/VS01 P2.4/NMI P2.5/AIN3/INT4/VS02 OSCIN OSCOUT P4.7/PWM7/EXTRG/STOUT P4.6/PWM6 P4.5/PWM5 P4.4/PWM4 P4.3/PWM3/TSLU/HT P4.2/PWM2 {92195} P4.1/PWM1 P4.0/PWM0 VSYNC HSYNC/CSYNC AVDD1 PXFM JTRST0 GND AGND CVBS1 CVBS2 JTMS AVDD2 CVBSO TXCF
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
C11
22pF
Figure 4. ST92195C/D Required External Components (56-pin package)
ST92195 ST92T195 ST92E195 - GENERAL DESCRIPTION
C13
4.7nF R3
5.6k
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P03 P04 P05 P06 P07
C5 C6 U1 VDD P0.3 P0.4 P0.5 P0.6 P0.7 RESETN INT7/P2.0 P2.1/INT5/AIN1 P2.2/INT0/AIN2 P2.3/INT6/VS01 P2.4/NMI P2.5/AIN3/INT4/VS02 OSCIN OSCOUT VDD 10uF 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 100nF
P02 P01 P00 P37 P36 P35 P34 {92195} B G R FB C7 P5.0
P20 P21 P22 P23 P24 P25
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 5. ST92195C/D Required External Components (64-pin package)
QFP64
NC NC WSCF WSCR AVDD3 TEST0 MCFM JTCK TXCF CVBSO AVDD2 JTMS CVBS2 CVBS1 AGND NC
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L1 10uH +5V D1 C3 100nF 1N4148 C2 S1 RST C4 39pF Y1 4 M hz 39pF P47 P46 P45 P44 P43 P42 P41 P40 C8 100nF VSYNC HSYNC 1 2 3 4 5 6 7 8 9 10 11 12 P5.1 13 14 15 16 VSS P0.2/AIN4 P0.1 P0.0 P3.7/RESET0/CSO P3.6 P3.5 P3.4 B G R FB P5.1/SDI/SDO P5.0/SCK/INT2 VDD JTDO GND EXTRG/SLOUT/P4.7/PWM7 P4.6/PWM6 P4.5/PWM5 P4.4/PWM4 HT/TSLU/P4.3/PWM3 P4.2/PWM2 P4.1/PWM1 P4.0/PWM0 VSYNC CSYNC/HSYNC AVDD1 PXFM JTRST0 GND NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 100nF R2 C12 C11 100nF C14 C15 R3 5.6k C17 2.2nF R4 15k C18 82pF C16 470nF CVBS 4.7nF 22pF 100nF C13 L2 10uF +5V 10uH 22pF C10 4.7nF C9 5.6k
R1
10k
C1
PIN DESCRIPTION (Cont'd)
ST92 195 ST92T195 ST92E195 - GENERAL DESCRIPTION
1F
ST92195 ST92T195 ST92E195 - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont'd) P0[7:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0] I/O Port Lines (Input/Output, TTL or CMOS compatible). 28 lines grouped into I/O ports, bit programmable as general purpose I/O or as Alternate functions (see I/O section).
Important: Note that open-drain outputs are for logic levels only and are not true open drain. 1.2.1 I/O Port Alternate Functions. Each pin of the I/O ports of the ST92195C/D may assume software programmable Alternate Functions (see Table 1).
Table 1. ST92195C/D I/O Port Alternate Function Summary
Port Name P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 Pin No. TQFP64 SDIP56 4 10 3 9 2 8 AIN4 63 7 62 6 61 5 60 4 59 3 57 1 INT7 AIN1 56 56 INT5 INT0 55 55 AIN2 All ports useable INT6 54 54 for general purVSO1 pose I/O (input, 53 53 NMI output or bidiAIN3 rectional) 52 52 INT4 VSO2 8 14 7 13 6 12 RESET0 5 11 CSO 40 42 PWM0 41 43 PWM1 42 44 PWM2 PWM3 43 45 TSLU HT General Purpose I/O Alternate Functions I/O I/O I I/O I/O I/O I/O I/O I I I I I I O I I I O I/O I/O I/O O O O O O O O O
A/D Analog Data Input 4
External Interrupt 7 A/D Analog Data Input 1 External Interrupt 5 External Interrupt 0 A/D Analog Data Input 2 External Interrupt 6 Voltage Synthesis Output 1 Non Maskable Interrupt Input A/D Analog Data Input 3 External Interrupt 4 Voltage Synthesis Output 2
Internal Reset Output Composite Sync output PWM Output 0 PWM Output 1 PWM Output 2 PWM Output 3 Translucency Digital Output Half-tone Output
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ST92 195 ST92T195 ST92E195 - GENERAL DESCRIPTION
Port Name P4.4 P4.5 P4.6 P4.7 All ports useable for general purpose I/O (input, output or bidirectional) General Purpose I/O Pin No. TQFP64 SDIP56 44 45 46 47 46 47 48 49 PWM4 SCL2 PWM5 SDA2 PWM6 EXTRG PWM7 STOUT0 INT2 SCK SCL1 SDO SDI SDA1 O I/O O I/O O I O O I O I/O O I I/O Alternate Functions PWM Output 4 I²C Channel 2 Serial Clock 1) PWM Output 5 I²C Channel 2 Serial Data 1) PWM Output 6 A/D Converter External Trigger Input PWM Output 7 Standard Timer 0 Output External Interrupt 2 SPI Serial Clock I²C Channel 1 Serial Clock 1) SPI Serial Data Out SPI Serial Data In I²C Channel 1 Serial Data 1)
P5.0
14
20
P5.1
13
19
Note 1: I²C available on ST92195D devices only. Table 2. I/O Port Styles
Pins P0[7:0] P2[5,4,3,2] P2[1,0] P3.7 P3[6,5,4] P4[7:0] P5[1:0] Weak Pull-Up no no no yes no no no Port Style Standard I/O Standard I/O Schmitt trigger Standard I/O Standard I/O Standard I/O Standard I/O Reset Values BID / OD / TTL BID / OD / TTL BID / OD / TTL AF / PP / TTL BID / OD / TTL BID / OD / TTL BID / OD / TTL
Legend:
AF= Alternate Function, BID = Bidirectional, OD = Open Drain PP = Push-Pull, TTL = TTL Standard Input Levels
How to Read this Table To configure the I/O ports, use the information in this table and the Port Bit Configuration Table in the I/O Ports Chapter on page 71. Port Style= the hardware characteristics fixed for each port line. Inputs: If port style = Standard I/O, either TTL or CMOS input level can be selected by software. If port style = Schmitt trigger, selecting CMOS or TTL input by software has no effect, the input will always be Schmitt Trigger. Weak Pull-Up = This column indicates if a weak pull-up is present or not.
If WPU = yes, then the WPU can be enabled/disable by software If WPU = no, then enabling the WPU by software has no effect Alternate Functions (AF) = More than one AF cannot be assigned to an external pin at the same time: An alternate function can be selected as follows. AF Inputs: AF is selected implicitly by enabling the corresponding peripheral. Exception to this are ADC analog inputs which must be explicitly selected as AF by software.
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ST92195 ST92T195 ST92E195 - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont'd) AF Outputs or Bidirectional Lines: In the case of Outputs or I/Os, AF is selected explicitly by software. Example 1: ADC trigger digital input AF: EXTRG, Port: P4.7, Port Style: Standard I/O. Write the port configuration bits (for TTL level): P4C2.7=1 P4C1.7=0 P4C0.7=1 Enable the ADC trigger by software as described in the ADC chapter. Example 2: PWM 0 output AF: PWM0, Port: P4.0 Write the port configuration bits (for output pushpull): P4C2.0=0 P4C1.0=1 P4C0.0=1 Example 3: ADC analog input AF: AIN1, Port : P2.1, Port style: does not apply to analog inputs Write the port configuration bits: P2C2.1=1 P 2 C 1 . 1 =1 P 2 C 0 . 1 =1
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ST92 195 ST92T195 ST92E195 - GENERAL DESCRIPTION
1.3 MEMORY MAP Internal ROM The ROM memory is mapped in two segments: segment 00h and segment 01h; It starts at address 0000h in MMU segment 00h.
Device ST92195C3/C4/C5 ST92195D5 ST92195C6 ST92195D6 ST92195C7 ST92195D7 ST92195C8 ST92195C9 Size 48K 56K 64K 84K 96K Start Address 00 0000h 00 0000h 00 0000h 00 0000h 00 0000h End Address 00 BFFFh 00 DFFFh 00 FFFFh 01 4FFFh 01 7FFFh
Internal RAM, 256 or 512 bytes The internal RAM is mapped in MMU segment 20h, from address FF00h to FFFFh or from FE00h to FFFFh. Internal TDSRAM The Internal TDSRAM is mapped starting at address 8000h in MMU segment 22h. It is a fully static memory.
Device ST92195C3 ST92195C4 ST92195C5/C6/C7/C8/C9 ST92195D5/D6/D7 Size 2K 6K 8K Start End Address Address 8000h 8000h 8000h 87FFh 97FFh 9FFFh
Figure 6. ST92195C/D Memory Map
229FFFh
max. 8 Kbytes TDSRAM
228000h
Reserved
22FFFFh 22C000h 22BFFFh 228000h 227FFFh
PAGE 91 - 16 Kbytes PAGE 90 - 16 Kbytes PAGE 89 - 16 Kbytes PAGE 88 - 16 Kbytes
SEGMENT 22h 64 Kbytes
Reserved
224000h 223FFFh
Reserved
220000h 21FFFFh
SEGMENT 21h 64 Kbytes
Reserved
Internal RAM 512 bytes 1)
Internal RAM 256 bytes 1)
20FFFFh
210000h 20FFFFh
PAGE 83 - 16 Kbytes
20C000h 20BFFFh
20FF00h 20FE00h
SEGMENT 20h 64 Kbytes
Reserved Reserved
PAGE 82 - 16 Kbytes
208000h 207FFFh
PAGE 81 - 16 Kbytes
204000h 203FFFh
Reserved
20 0 0h 01FFFFh
PAGE 80 - 16 Kbytes PAGE 3 - 16 Kbytes PAGE 2 - 16 Kbytes PAGE 1 - 16 Kbytes PAGE 0 - 16 Kbytes PAGE 3 - 16 Kbytes PAGE 2 - 16 Kbytes PAGE 1 - 16 Kbytes PAGE 0 - 16 Kbytes
Reserved 96 Kbytes 1) 84 Kbytes 1) 128K bytes 64 Kbytes 1)
017FFFh 014FFFh 00FFFFh 00DFFFh 00BFFFh
01C000h 01BFFFh 018000h 017FFFh
SEGMENT 1 64 Kbytes Internal ROM max. 32 Kbytes
014000h 013FFFh 010000h 00FFFFh 00C000h 00BFFFh
56 Kbytes 1) Internal ROM 48K bytes 1)
SEGMENT 0 64 Kbytes
Internal ROM max. 64 Kbytes
008000h 007FFFh 004000h 003FFFh 0 0 00h
Note 1: ROM and RAM sizes are device dependent
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ST92195 ST92T195 ST92E195 - GENERAL DESCRIPTION
1.4 REGISTER MAP The following pages contain a list of ST92195C/D registers, grouped by peripheral or function. Be very careful to correctly program both: The set of registers dedicated to a particular function or peripheral. Registers common to other functions. Table 3. Group F Pages Register Map
Register 0 R255 R254 SPI R253 R252 R251 R250 WD T R249 R248 R247 R246 Res R245 R244 R243 R242 R241 Res. R240 Note 1: Depending on device. See device summary on page 1. Port 0 Port 4 EXT INT Res. Port 5 Res. Res. Res. Port 2 WC R TSU Res. Res. Res STIM 1 1) MMU Res. Port 3 TCC Res. Res. 2 Res. Res. RCCU Res. (PLL) 3 6 11 21 32 33 Page 34 35 36 37 38 39 Res. VS 44 55 59 62
In particular, double-check that any registers with "undefined" reset values have been correctly initialised. Warning: Note that in the EIVR and each IVR register, all bits are significant. Take care when defining base vector addresses that entries in the Interrupt Vector table do not overlap.
VPS/ WSS
OSD Res.
ACQ
TDS RAM
PWM
Res.
MMU SYNC STIM 0 Res. I²C 1)
A/D
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ST92 195 ST92T195 ST92E195 - GENERAL DESCRIPTION
Table 4. Detailed Register Map
Group F Page Dec. Block Reg. No. R224 I/O Port 0:5 R226 R227 R228 R229 R230 R231 N/A R232 R233 Core R234 R235 R236 R237 R238 R239 R242 R243 INT R244 R245 R246 R247 0 WDT R248 R249 R250 R251 R252 SPI I/O Port 0 I/O 2 Port 2 I/O Port 3 R253 R254 R240 R241 R242 R248 R249 R250 R252 R253 R254 Register Name P0DR P2DR P3DR P4DR P5DR CICR FLAGR RP0 RP1 PPR MODER USPHR USPLR SSPHR SSPLR EITR EIPR EIMR EIPLR EIVR NICR WDTHR WDTLR WDTPR WDTCR WCR SPIDR SPICR P0C0 P0C1 P0C2 P2C0 P2C1 P2C2 P3C0 P3C1 P3C2 Description Port 0 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 5 Data Register Central Interrupt Control Register Flag Register Pointer 0 Register Pointer 1 Register Page Pointer Register Mode Register User Stack Pointer High Register User Stack Pointer Low Register System Stack Pointer High Reg. System Stack Pointer Low Reg. External Interrupt Trigger Register External Interrupt Pending Reg. External Interrupt Mask-bit Reg. External Interrupt Priority Level Reg. External Interrupt Vector Register Nested Interrupt Control Watchdog Timer High Register Watchdog Timer Low Register Watchdog Timer Prescaler Reg. Watchdog Timer Control Register Wait Control Register SPI Data Register SPI Control Register Port 0 Configuration Register 0 Port 0 Configuration Register 1 Port 0 Configuration Register 2 Port 2 Configuration Register 0 Port 2 Configuration Register 1 Port 2 Configuration Register 2 Port 3 Configuration Register 0 Port 3 Configuration Register 1 Port 3 Configuration Register 2 Reset Value Hex. FF FF FF FF FF 87 00 xx xx xx E0 xx xx xx xx 00 00 00 FF x6 00 FF FF FF 12 7F xx 00 00 00 00 00 00 00 00 00 00 68 56 29 31 31 33 33 35 35 35 35 56 57 57 57 58 58 80 80 80 80 81 182 182 68 Doc. Page
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ST92195 ST92T195 ST92E195 - GENERAL DESCRIPTION
Group F Page Dec. Block I/O Port 3 4 I/O Port 5 Reg. No. R240 R241 R242 R244 R245 R246 R240 R241 R242 R243 R244 R245 6 VPS/ WSS R246 R247 R248 R249 R250 R251 R252 R240 STIM0 11 STIM1 1) R241 R242 R243 R248 R249 R250 R251 R240 R241 R242 MMU 21 R243 R244 R248 R249 Ext.Mem. R246 Register Name P4C0 P4C1 P4C2 P5C0 P5C1 P5C2 VPSSR VPSD0R VPSD1R VPSD2R VPSD3R VPSD4R WSSDS0R WSSDS1R WSSDS2R VPSWSSCR WSSDS3R WSSDS4R WSSDS5R ST0HR ST0LR ST0PR ST0CR ST1HR ST1LR ST1PR ST1CR DPR0 DPR1 DPR2 DPR3 CSR ISR DMASR EMR2 Description Port 4 Configuration Register 0 Port 4 Configuration Register 1 Port 4 Configuration Register 2 Port 5 Configuration Register 0 Port 5 Configuration Register 1 Port 5 Configuration Register 2 VPS Status Register VPS Data Register 0 VPS Data Register 1 VPS Data Register 2 VPS Data Register 3 VPS Data Register 4 WSS Data and Status Register 0 WSS Data and Status Register 1 WSS Data and Status Register 2 VPS/WSS Control Register WSS Data and Status Register 3 WSS Data and Status Register 4 WSS Data and Status Register 5 Counter High Byte Register Counter Low Byte Register Standard Timer Prescaler Register Standard Timer Control Register Counter High Byte Register Counter Low Byte Register Standard Timer Prescaler Register Standard Timer Control Register Data Page Register 0 Data Page Register 1 Data Page Register 2 Data Page Register 3 Code Segment Register Interrupt Segment Register DMA Segment Register External Memory Register 2 Reset Value Hex. 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 FF FF FF 14 FF FF FF 14 xx xx xx xx 00 xx xx 0F 170 170 170 170 171 171 171 171 171 172 172 173 173 85 85 85 85 85 85 85 85 40 40 40 40 41 41 41 59 68 Doc. Page
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ST92 195 ST92T195 ST92E195 - GENERAL DESCRIPTION
Group F Page Dec. Block Reg. No. R240 R241 R242 R243 R244 R245 R246 32 OSD R247 R248 R249 R250 R251 R252 R253 R254 R255 R240 33 R241 R246 R247 R242 R243 R248 R249 34 ACQ R250 R251 R252 R253 R254 R255 SYNC 35 TSU R242 R243 R248 R249 R255 Register Name HBLANKR HPOSR VPOSR FSCCR HSCR NCSR CHPOSR CVPOSR SCLR SCHR DCM0R DCM1R TDPR DE0R DE1R DE2R DCR CAPVR TDPPR TDHSPR ACQAD1R ACQAD0R ACQPOR ACQMLR ACQNHRR ACQPRR ACQTQMR ACQHD2R ACQHD1R ACQHD0R SCCS0R SCCS1R TXSCR TXSLIR PASR Description Horizontal Blank Register Horizontal Position Register Vertical Position Register Full Screen Color Control Register Header & Status Control Register National Character Set Control Register Cursor Horizontal Position Register Cursor Vertical Position Register Scrolling Control Low Register Scrolling Control High Register Display Control Mode 0 Register Display Control Mode 1 Register TDSRAM Pointer Register Display Enable 0 Control Register Display Enable 1 Control Register Display Enable 2 Control Register Default Color Register Cursor Absolute Vertical Position Register TDSRAM Page Pointer Register TDSRAM Header/Status Pointer Register Acquisition Address Register 1 Acquisition Address Register 0 Acquisition Page Open Register Acquisition Magazine Locked Register Acquisition New Header Received Register Acquisition Packet Request Register Acquisition Teletext Quality Measure Register Acquisition Hamming Decoding Register 2 Acquisition Hamming Decoding Register 1 Acquisition Hamming Decoding Register 0 Sync Controller Control and Status Register 0 Sync Controller Control and Status Register 1 Teletext Slicer Control Register Teletext Slicer Initialization Register Pre-Amplifier and ADC Selection Register Reset Value Hex. 03 03 00 00 2A 00 00 00 00 00 00 00 00 FF FF xF 70 00 x0 x0 xx xx 00 00 00 00 00 xx xx xx 00 00 06 0B 00 Doc. Page 125 125 125 126 127 128 129 129 130 131 133 134 134 135 135 135 136 136 136 136 163 163 158 158 158 159 159 160 160 160 144 145 163 164 164
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ST92195 ST92T195 ST92E195 - GENERAL DESCRIPTION
Group F Page Dec. 36 Block Reg. No. R240 .. R255 R240 37 TDSRAM .. R255 R240 .. R247 38 R248 R250 R251 R252 R251 39 TCC R252 R253 R254 R240 R241 R242 R243 R244 R245 R251 55 RCCU R254 Register Name BUF0 .. BUF15 BUF16 .. BUF31 BUF32 .. BUF39 BUFC MTBSA1 MTBSA0 CONFIG PXCCR SLCCR MCCR SKCCR I²COAR I²CFQR I²CCTR I²CDR I²CSTR2 I²CSTR1 PCONF SDRATH TDSRAM Buffer Control Register Multi-byte Transfer Start Address Register 1 Multi-byte Transfer Start Address Register 0 TDSRAM Interface Configuration Register PLL Clock Control Register Slicer Clock Control Register Main Clock Control Register Skew Clock Control Register Own Address Register Frequency Register Control Register Data Register Status Register 2 Status Register 1 PLL Configuration Register Clock Slow Down Unit Ratio Register 40-byte buffer Description Reset Value Hex. xx .. xx xx .. xx xx .. xx 08 80 00 06 00 00 00 00 00 00 01 00 00 00 07 2x,4x or 00 92 91 91 93 68 68 67 67 on page 1891 89 190 191 192 192 193 63 63 91 Doc. Page
44
I²C 1)
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ST92 195 ST92T195 ST92E195 - GENERAL DESCRIPTION
Group F Page Dec. Block Reg. No. R240 R241 R242 R243 R244 R245 P WM 59 R246 R247 R248 R249 R250 R251 R252 VS R254 R255 R240 62 ADC R241 R242 Register Name CM0 CM1 CM2 CM3 CM4 CM5 CM6 CM7 ACR CCR PCTL OCPL OER VSDR1 VSDR2 ADDTR ADCLR ADINT Description Compare Register 0 Compare Register 1 Compare Register 2 Compare Register 3 Compare Register 4 Compare Register 5 Compare Register 6 Compare Register 7 Autoclear Register Counter Register Prescaler and Control Register Output Complement Register Output Enable Register Data and Control Register 1 Data Register 2 Channel i Data Register Control Logic Register AD Interrupt Register Reset Value Hex. 00 00 00 00 00 00 00 00 FF 00 0C 00 00 00 00 xx 00 01 Doc. Page 207 207 207 207 207 207 207 207 208 208 208 209 209 204 204 199 198 199
Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register description for details. Note 1: Depending on device. See device summary on page 1.
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ST92195 ST92T195 ST92E195 - DEVICE ARCHITECTURE
2 DEVICE ARCHITECTURE
2.1 CORE ARCHITECTURE The ST9 Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean formats; 14 addressing modes are available. Four independent buses are controlled by the Core: a 16-bit Memory bus, an 8-bit Register data bus, an 8-bit Register address bus and a 6-bit Interrupt/DMA bus which connects the interrupt and DMA controllers in the on-chip peripherals with the Core. This multiple bus architecture affords a high degree of pipelining and parallel operation, thus making the ST9 family devices highly efficient, both for numerical calculation, data handling and with regard to communication with on-chip peripheral resources. which hold data and control bits for the on-chip peripherals and I/Os. A single linear memory space accommodating both program and data. All of the physically separate memory areas, including the internal ROM, internal RAM and external memory are mapped in this common address space. The total addressable memory space of 4 Mbytes (limited by the size of on-chip memory and the number of external address pins) is arranged as 64 segments of 64 Kbytes. Each segment is further subdivided into four pages of 16 Kbytes, as illustrated in Figure 1. A Memory Management Unit uses a set of pointer registers to address a 22-bit memory field using 16-bit address-based instructions. 2.2.1 Register File The Register File consists of (see Figure 2): 2.2 MEMORY SPACES 224 general purpose registers (Group 0 to D, There are two separate memory spaces: registers R0 to R223) The Register File, which comprises 240 8-bit 6 system registers in the System Group (Group registers, arranged as 15 groups (Group 0 to E), E, registers R224 to R239) each containing sixteen 8-bit registers plus up to Up to 64 pages, depending on device configura64 pages of 16 registers mapped in Group F, tion, each containing up to 16 registers, mapped to Group F (R240 to R255), see Figure 3. Figure 7. Single Program and Data Memory Address Space
Address
3 FFFFFh 3F0000h 3 E FFFFh 3E0000h
Data 16K Pages
255 254 253 252 251 250 249 248 247
Code 64K Segments
63
62
up to 4 Mbytes
135 134 133 132
21FFFFh 210000h 20FFFFh
Reserved
33
02FFFF h 020000h 01FFFF h 010000h 00FFFF h 0 0 00h
11 10 9 8 7 6 5 4 3 2 1 0
2
1
0
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ST92 195 ST92T195 ST92E195 - DEVICE ARCHITECTURE
MEMORY SPACES (Cont'd) Figure 8. Register Groups
UP TO 64 PAGES P AG E 5 R2 5 5 P AGE 0
Figure 9. Page Pointer for Group F mapping
P AGE 63
255 240 F PA GE D REGISTERS 239 E S YS TE M REGISTERS 224 223 D C B A 9 8 7 6 5 4 3 2 1 0 0 15 0
R2 4 0 R 234 224 GEN ER AL P UR PO SE RE G I ST ER S R 224 PA GE POINTER
VA00432
R0
VA00433
Figure 10. Addressing the Register File
RE GIS TER FILE 255 240 F PA GE D REGISTERS 239 E S YS TE M REGISTERS 224 223 D C B A 9 8 7 6 5 4 3 2 1 0 0 15 0
VR 000118
G RO U P D R1 9 5 (R 0C3h) R2 0 7
( 1100) (0011) G R O UP C
R 195 R1 9 2 G R O UP B
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MEMORY SPACES (Cont'd) 2.2.2 Register Addressing Register File registers, including Group F paged registers (but excluding Group D), may be addressed explicitly by means of a decimal, hexadecimal or binary address; thus R231, RE7h and R11100111b represent the same register (see Figure 4). Group D registers can only be addressed in Working Register mode. Note that an upper case "R" is used to denote this direct addressing mode. Working Registers Certain types of instruction require that registers be specified in the form "rx", where x is in the range 0 to 15: these are known as Working Registers. Note that a lower case "r" is used to denote this indirect addressing mode. Two addressing schemes are available: a single group of 16 working registers, or two separately mapped groups, each consisting of 8 working registers. These groups may be mapped starting at any 8 or 16 byte boundary in the register file by means of dedicated pointer registers. This technique is described in more detail in Section 1.3.3, and illustrated in Figure 5 and in Figure 6. System Registers The 16 registers in Group E (R224 to R239) are System registers and may be addressed using any of the register addressing modes. These registers are described in greater detail in Section 1.3. Paged Registers Up to 64 pages, each containing 16 registers, may be mapped to Group F. These are addressed using any register addressing mode, in conjunction with the Page Pointer register, R234, which is one of the System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more registers on the same page are to be addressed in succession. Therefore if the Page Pointer, R234, is set to 5, the instructions: spp #5 ld R242, r4 will load the contents of working register r4 into the third register of page 5 (R242). These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9 devices. The number of these registers therefore depends on the peripherals which are present in the specific ST9 family device. In other words, pages only exist if the relevant peripheral is present. Table 5. Register File Organization
Hex. Address F0-FF E0-EF D0-DF C0-CF B0-BF A0-AF 90-9F 80-8F 70-7F 60-6F 50-5F 40-4F 30-3F 20-2F 10-1F 00-0F Decimal Address 240-255 224-239 208-223 192-207 176-191 160-175 144-159 128-143 112-127 96-111 80-95 64-79 48-63 32-47 16-31 00-15 General Purpose Registers Function Paged Registers System Registers Register File Group Group F Group E Group D Group C Group B Group A Group 9 Group 8 Group 7 Group 6 Group 5 Group 4 Group 3 Group 2 Group 1 Group 0
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2.3 SYSTEM REGISTERS The System registers are listed in Table 2 System Registers (Group E). They are used to perform all the important system settings. Their purpose is described in the following pages. Refer to the chapter dealing with I/O for a description of the PORT[5:0] Data registers. Table 6. System Registers (Group E)
R239 (EFh) R238 (EEh) R237 (EDh) R236 (ECh) R235 (EBh) R234 (EAh) R233 (E9h) R232 (E8h) R231 (E7h) R230 (E6h) R229 (E5h) R228 (E4h) R227 (E3h) R226 (E2h) R225 (E1h) R224 (E0h) SSPLR SSPHR USPLR USPHR MODE REGISTER PAGE POINTER REGISTER REGISTER POINTER 1 REGISTER POINTER 0 FLAG REGISTER CENTRAL INT. CNTL REG PORT5 DATA REG. PORT4 DATA REG. PORT3 DATA REG. PORT2 DATA REG. PORT1 DATA REG. PORT0 DATA REG.
Note: If an MFT is not included in the ST9 device, then this bit has no effect. Bit 6 = TLIP: Top Level Interrupt Pending. This bit is set by hardware when a Top Level Interrupt Request is recognized. This bit can also be set by software to simulate a Top Level Interrupt Request. 0: No Top Level Interrupt pending 1: Top Level Interrupt pending Bit 5 = TLI: Top Level Interrupt bit. 0: Top Level Interrupt is acknowledged depending on the TLNM bit in the NICR Register. 1: Top Level Interrupt is acknowledged depending on the IEN and TLNM bits in the NICR Register (described in the Interrupt chapter). Bit 4 = IEN: Interrupt Enable . This bit is cleared by interrupt acknowledgement, and set by interrupt return (iret). IEN is modified implicitly by iret, ei and di instructions or by an interrupt acknowledge cycle. It can also be explicitly written by the user, but only when no interrupt is pending. Therefore, the user should execute a di instruction (or guarantee by other means that no interrupt request can arrive) before any write operation to the CICR register. 0: Disable all interrupts except Top Level Interrupt. 1: Enable Interrupts Bit 3 = IAM: Interrupt Arbitration Mode. This bit is set and cleared by software to select the arbitration mode. 0: Concurrent Mode 1: Nested Mode. Bits 2:0 = CPL[2:0]: Current Priority Level. These three bits record the priority level of the routine currently running (i.e. the Current Priority Level, CPL). The highest priority level is represented by 000, and the lowest by 111. The CPL bits can be set by hardware or software and provide the reference according to which subsequent interrupts are either left pending or are allowed to interrupt the current interrupt service routine. When the current interrupt is replaced by one of a higher priority, the current priority value is automatically stored until required in the NICR register.
2.3.1 Central Interrupt Control Register Please refer to the "INTERRUPT" chapter for a detailed description of the ST9 interrupt philosophy. CEN TRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: E (System) Reset Value: 1000 0111 (87h)
7 GCEN TLIP TLI IEN IAM 0 CPL2 CPL1 CPL0
Bit 7 = GCEN: Global Counter Enable. This bit is the Global Counter Enable of the Multifunction Timers. The GCEN bit is ANDed with the CE bit in the TCR Register (only in devices featuring the MFT Multifunction Timer) in order to enable the Timers when both bits are set. This bit is set after the Reset cycle.
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SYSTEM REGISTERS (Cont'd) 2.3.2 Flag Register The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag register is automatically stored in the system stack area and recalled at the end of the interrupt service routine, thus returning the CPU to its original status. This occurs for all interrupts and, when operating in nested mode, up to seven versions of the flag register may be stored. FLAG REGISTER (FLAGR) R231- Read/Write Register Group: E (System) Reset value: 0000 0000 (00h)
7 C Z S V DA H 0 DP
decw), Test (tm, tmw, tcm, tcmw, btset). In most cases, the Zero flag is set when the contents of the register being used as an accumulator become zero, following one of the above operations. Bit 5 = S: Sign Flag. The Sign flag is affected by the same instructions as the Zero flag. The Sign flag is set when bit 7 (for a byte operation) or bit 15 (for a word operation) of the register used as an accumulator is one. Bit 4 = V: Overflow Flag. The Overflow flag is affected by the same instructions as the Zero and Sign flags. When set, the Overflow flag indicates that a two'scomplement number, in a result register, is in error, since it has exceeded the largest (or is less than the smallest), number that can be represented in two's-complement notation. Bit 3 = DA: Decimal Adjust Flag. The DA flag is used for BCD arithmetic. Since the algorithm for correcting BCD operations is different for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequent Decimal Adjust (da) operation can perform its function correctly. The DA flag cannot normally be used as a test condition by the programmer. Bit 2 = H: Half Carry Flag. The H flag indicates a carry out of (or a borrow into) bit 3, as the result of adding or subtracting two 8-bit bytes, each representing two BCD digits. The H flag is used by the Decimal Adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct BCD result. Like the DA flag, this flag is not normally accessed by the user. Bit 1 = Reserved bit (must be 0). Bit 0 = DP: Data/Program Memory Flag. This bit indicates the memory area addressed. Its value is affected by the Set Data Memory (sdm) and Set Program Memory (spm) instructions. Refer to the Memory Management Unit for further details.
Bit 7 = C: Carry Flag. The carry flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws). When set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations). The carry flag can be set by the Set Carry Flag (scf ) instruction, cleared by the Reset Carry Flag (rcf ) instruction, and complemented by the Complement Carry Flag (ccf) instruction. Bit 6 = Z: Zero Flag. The Zero flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws), Logical (and, andw, or, orw, xor, xorw, cpl), Increment and Decrement (inc, incw, dec,
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SYSTEM REGISTERS (Cont'd) If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include a Sdm instruction. Note that code is always pointed to by the Code Pointer (CSR). Note: In the current ST9 devices, the DP flag is only for compatibility with software developed for the first generation of ST9 devices. With the single memory addressing space, its use is now redundant. It must be kept to 1 with a Sdm instruction at the beginning of the program to ensure a normal use of the different memory pointers. 2.3.3 Register Pointing Techniques Two registers within the System register group, are used as pointers to the working registers. Register Pointer 0 (R232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with Register Pointer 1 (R233), to point to two separate 8-register spaces. For the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8register blocks. The values specified with the Set Register Pointer instructions refer to the blocks to be pointed to in twin 8-register mode, or to the lower 8-register block location in single 16-register mode. The Set Register Pointer instructions srp, srp0 and srp1 automatically inform the CPU whether the Register File is to operate in single 16-register mode or in twin 8-register mode. The srp instruction selects the single 16-register group mode and specifies the location of the lower 8-register block, while the srp0 and srp1 instructions automatically select the twin 8-register group mode and specify the locations of each 8-register block. There is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary in twin 8-register mode, or on a 16-register boundary in single 16register mode. The block number should always be an even number in single 16-register mode. The 16-register group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in the srp instruction. Avoid using odd block numbers, since this can be confusing if twin mode is subsequently selected. Thus: srp #3 will be interpreted as srp #2 and will allow using R16 ..R31 as r0 .. r15. In single 16-register mode, the working registers are referred to as r0 to r15. In twin 8-register mode, registers r0 to r7 are in the block pointed to by RP0 (by means of the srp0 instruction), while registers r8 to r15 are in the block pointed to by RP1 (by means of the srp1 instruction). Caution: Group D registers can only be accessed as working registers using the Register Pointers, or by means of the Stack Pointers. They cannot be addressed explicitly in the form "Rxxx".
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SYSTEM REGISTERS (Cont'd) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh)
7 RG4 RG3 RG2 RG1 RG0 RPS 0 0 0
POINTER 1 REGISTER (RP1) R233 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh)
7 RG4 RG3 RG2 RG1 RG0 RPS 0 0 0
Bits 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range 0 to 31) of the register block specified in the srp0 or srp instructions. In single 16-register mode the number indicates the lower of the two 8-register blocks to which the 16 working registers are to be mapped, while in twin 8-register mode it indicates the 8-register block to which r0 to r7 are to be mapped. Bit 2 = RPS: Register Pointer Selector. This bit is set by the instructions srp0 and srp1 to indicate that the twin register pointing mode is selected. The bit is reset by the srp instruction to indicate that the single register pointing mode is selected. 0: Single register pointing mode 1: Twin register pointing mode Bits 1:0: Reserved. Forced by hardware to zero.
This register is only used in the twin register pointing mode. When using the single register pointing mode, or when using only one of the twin register groups, the RP1 register must be considered as RESERVED and may NOT be used as a general purpose register. Bits 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range 0 to 31) of the 8-register block specified in the srp1 instruction, to which r8 to r15 are to be mapped. Bit 2 = RPS: Register Pointer Selector. This bit is set by the srp0 and srp1 instructions to indicate that the twin register pointing mode is selected. The bit is reset by the srp instruction to indicate that the single register pointing mode is selected. 0: Single register pointing mode 1: Twin register pointing mode Bits 1:0: Reserved. Forced by hardware to zero.
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SYSTEM REGISTERS (Cont'd) Figure 11. Pointing to a single group of 16 registers
REGISTER GROUP REGISTER FI LE 31 31 F 30 29 E 28 points to: 27 D 26 25 25 addressed by BLOCK 7 9 9 4 8 7 7 3 6 5 5 2 4 r15 3 1 2 r0 1 0 0 addressed by BLOCK 2 1 0 0 GROUP 1 2 r0 3 1 r7 GROUP 1 addressed by BLOCK 2 4 2 6 3 r8 8 r15 GROUP 3 4 26 27 D REGISTER POINTER 0 set by: 30 29 E 28 F REGISTER POINTER 0 & REGISTER POINTER 1 set by:
Figure 12. Pointing to two groups of 8 registers
REGISTER GROUP REGISTER FI LE
BLOCK NUMBER
BLOCK NUMBER
srp #2
instruction
srp0 #2
&
srp1 #7
instructions point to:
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SYSTEM REGISTERS (Cont'd) 2.3.4 Paged Registers Up to 64 pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9 devices. The number of these registers depends on the peripherals present in the specific ST9 device. In other words, pages only exist if the relevant peripheral is present. The paged registers are addressed using the normal register addressing modes, in conjunction with the Page Pointer register, R234, which is one of the System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more registers on the same page are to be addressed in succession. Thus the instructions: spp #5 ld R242, r4 will load the contents of working register r4 into the third register of page 5 (R242). Warning: During an interrupt, the PPR register is not saved automatically in the stack. If needed, it should be saved/restored by the user within the interrupt routine. PAGE POINTER REGISTER (PPR) R234 - Read/Write Register Group: E (System) Reset value: xxxx xx00 (xxh)
7 PP5 PP4 PP3 PP2 PP1 PP0 0 0 0
Management of the clock frequency, Enabling of Bus request and Wait signals when interfacing to external memory. MODE REGISTER (MODER) R235 - Read/Write Register Group: E (System) Reset value: 1110 0000 (E0h)
7
SSP USP DIV2 PRS2 PRS1
0
PRS0 BRQEN HIMP
Bit 7 = SSP: System Stack Pointer. This bit selects an internal or external System Stack area. 0: External system stack area, in memory space. 1: Internal system stack area, in the Register File (reset state). Bit 6 = USP: User Stack Pointer. This bit selects an internal or external User Stack area. 0: External user stack area, in memory space. 1: Internal user stack area, in the Register File (reset state). Bit 5 = DIV2: Crystal Oscillator Clock Divided by 2. This bit controls the divide-by-2 circuit operating on the crystal oscillator clock (CLOCK1). 0: Clock divided by 1 1: Clock divided by 2 Bits 4:2 = PRS[2:0]: CPUCLK Prescaler. These bits load the prescaler division factor for the internal clock (INTCLK). The prescaler factor selects the internal clock frequency, which can be divided by a factor from 1 to 8. Refer to the Reset and Clock Control chapter for further information. Bit 1 = BRQEN: Bus Request Enable. 0: External Memory Bus Request disabled 1: External Memory Bus Request enabled on BREQ pin (where available). Note: Disregard this bit if BREQ pin is not available. Bit 0 = HIMP: High Impedance Enable. When any of Ports 0, 1, 2 or 6 depending on device configuration, are programmed as Address and Data lines to interface external Memory, these lines and the Memory interface control lines (AS, DS, R/W) can be forced into the High Impedance
Bits 7:2 = PP[5:0]: Page Pointer. These bits contain the number (in the range 0 to 63) of the page specified in the spp instruction. Once the page pointer has been set, there is no need to refresh it unless a different page is required. Bits 1:0: Reserved. Forced by hardware to 0. 2.3.5 Mode Register The Mode Register allows control of the following operating parameters: Selection of internal or external System and User Stack areas,
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SYSTEM REGISTERS (Cont'd) state by setting the HIMP bit. When this bit is reset, it has no effect. Setting the HIMP bit is recommended for noise reduction when only internal Memory is used. If Port 1 and/or 2 are declared as an address AND as an I/O port (for example: P10... P14 = Address, and P15... P17 = I/O), the HIMP bit has no effect on the I/O lines. 2.3.6 Stack Pointers Two separate, double-register stack pointers are available: the System Stack Pointer and the User Stack Pointer, both of which can address registers or memory. The stack pointers point to the "bottom" of the stacks which are filled using the push commands and emptied using the pop commands. The stack pointer is automatically pre-decremented when data is "pushed" in and post-incremented when data is "popped" out. The push and pop commands used to manage the System Stack may be addressed to the User Stack by adding the suffix "u". To use a stack instruction for a word, the suffix "w" is added. These suffixes may be combined. When bytes (or words) are "popped" out from a stack, the contents of the stack locations are unchanged until fresh data is loaded. Thus, when data is "popped" from a stack area, the stack contents remain unchanged. Note: Instructions such as: pushuw RR236 or pushw RR238, as well as the corresponding pop instructions (where R236 & R237, and R238 & R239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by the push or pop instruction, thus corrupting their value. System Stack The System Stack is used for the temporary storage of system and/or control data, such as the Flag register and the Program counter. The following automatically push data onto the System Stack: Interrupts When entering an interrupt, the PC and the Flag Register are pushed onto the System Stack. If the ENC SR bit in the EMR2 register is set, then the Code Segment Register is also pushed onto the System Stack. Subroutine Calls When a call instruction is executed, only the PC is pushed onto stack, whereas when a calls instruction (call segment) is executed, both the PC and the Code Segment Register are pushed onto the System Stack. Link Instruction The link or linku instructions create a C language stack frame of user-defined length in the System or User Stack. All of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack. User Stack The User Stack provides a totally user-controlled stacking area. The User Stack Pointer consists of two registers, R236 and R237, which are both used for addressing a stack in memory. When stacking in the Register File, the User Stack Pointer High Register, R236, becomes redundant but must be considered as reserved. Stack Pointers Both System and User stacks are pointed to by double-byte stack pointers. Stacks may be set up in RAM or in the Register File. Only the lower byte will be required if the stack is in the Register File. The upper byte must then be considered as reserved and must not be used as a general purpose register. The stack pointer registers are located in the System Group of the Register File, this is illustrated in Table 2 System Registers (Group E). Stack Location Care is necessary when managing stacks as there is no limit to stack sizes apart from the bottom of any address space in which the stack is placed. Consequently programmers are advised to use a stack pointer value as high as possible, particularly when using the Register File as a stacking area. Group D is a good location for a stack in the Register File, since it is the highest available area. The stacks may be located anywhere in the first 14 groups of the Register File (internal stacks) or in RAM (external stacks). Note. Stacks must not be located in the Paged Register Group or in the System Register Group.
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SYSTEM REGISTERS (Cont'd) USER STACK POINTER HIGH REGISTER (USPHR) R236 - Read/Write Register Group: E (System) Reset value: undefined
7 USP15 USP14 USP13 USP12 USP11 USP10 USP9 0 U SP8
SYSTEM STACK POINTER HIGH REGISTER (SSPHR) R238 - Read/Write Register Group: E (System) Reset value: undefined
7 SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 0 SSP8
USER STACK POINTER LOW REGISTER (USPLR) R237 - Read/Write Register Group: E (System) Reset value: undefined
7 USP7 USP6 USP5 USP4 U SP3 USP2 USP1 0 USP0
SYSTEM STACK POINTER LOW REGISTER (SSPLR) R239 - Read/Write Register Group: E (System) Reset value: undefined
7 SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 0 SSP0
Figure 13. Internal Stack Mode
Figure 14. External Stack Mode
REGISTER FI LE STACK POINTER (LOW) F points to: F
REGISTER FI LE
STACK POINTER (LOW) & STACK POINTER (HIGH) point to: MEMORY
E STACK D
E
D
STACK 4 4
3
3
2
2
1
1
0
0
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2.4 MEMORY ORGANIZATION Code and data are accessed within the same linear address space. All of the physically separate memory areas, including the internal ROM, internal RAM and external memory are mapped in a common address space. The ST9 provides a total addressable memory space of 4 Mbytes. This address space is arranged as 64 segments of 64 Kbytes; each segment is again subdivided into four 16 Kbyte pages. The mapping of the various memory areas (internal RAM or ROM, external memory) differs from device to device. Each 64-Kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 Kbytes, the remaining locations in the 64-Kbyte segment are not used (reserved). Refer to the Register and Memory Map Chapter for more details on the memory map.
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2.5 MEMORY MANAGEMENT UNIT The CPU Core includes a Memory Management Unit (MMU) which must be programmed to perform memory accesses (even if external memory is not used). The MMU is controlled by 7 registers and 2 bits (ENCSR and DPRREM) present in EMR2, which may be written and read by the user program. These registers are mapped within group F, Page 21 of the Register File. The 7 registers may be Figure 15. Page 21 Registers sub-divided into 2 main groups: a first group of four 8-bit registers (DPR[3:0]), and a second group of three 6-bit registers (CSR, ISR, and DMASR). The first group is used to extend the address during Data Memory access (DPR[3:0]). The second is used to manage Program and Data Memory accesses during Code execution (CSR), Interrupts Service Routines (ISR or CSR), and DMA transfers (DMASR or ISR).
Page 21 FFh FEh FDh FCh FBh FAh F9h F8h F7h F6h F5h F4h F3h F2h F1h F0h EMR2 EMR1 CSR DPR3 DPR2 DPR1 DPR0 DMASR ISR R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240 MMU EM MMU MMU SSPLR SSPHR USPLR USPHR MODER PPR RP1 RP0 FLAGR CICR P5DR P4DR P3DR P2DR P1DR P0DR SSPLR SSPHR USPLR USPHR MODER PPR RP1 RP0 FLAGR CICR P5DR P4DR DPR3 DPR2 DPR1 DPR0
Relocation of P[3:0] and DPR[3:0] Registers
DMASR ISR EMR2 EMR1 CSR DPR3 DPR2 1 DPR0
DMASR ISR EMR2 EMR1 CSR P3DR P2DR P1DR P0DR
Bit DPRREM=0 (default setting)
Bit DPRREM=1
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2.6 ADDRESS SPACE EXTENSION To manage 4 Mbytes of addressing space, it is necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus translating a 16-bit virtual address into a 22-bit physical address. There are 2 different ways to do this depending on the memory involved and on the operation being performed. 2.6.1 Addressing 16-Kbyte Pages This extension mode is implicitly used to address Data memory space if no DMA is being performed. The Data memory space is divided into 4 pages of 16 Kbytes. Each one of the four 8-bit registers (DPR[3:0], Data Page Registers) selects a different 16-Kbyte page. The DPR registers allow access to the entire memory space which contains 256 pages of 16 Kbytes. Data paging is performed by extending the 14 LSB of the 16-bit address with the contents of a DPR register. The two MSBs of the 16-bit address are interpreted as the identification number of the DPR register to be used. Therefore, the DPR registers Figure 16. Addressing via DPR[3:0] are involved in the following virtual address ranges : D PR0: from 0000h to 3FFFh; D PR1: from 4000h to 7FFFh; D PR2: from 8000h to BFFFh; D PR3: from C000h to FFFFh. The contents of the selected DPR register specify one of the 256 possible data memory pages. This 8-bit data page number, in addition to the remaining 14-bit page offset address forms the physical 22-bit address (see Figure 10). A DPR register cannot be modified via an addressing mode that uses the same DPR register. For instance, the instruction "POPW DPR0" is legal only if the stack is kept either in the register file or in a memory location above 8000h, where DPR2 and DPR3 are used. Otherwise, since DPR0 and DPR1 are modified by the instruction, unpredictable behaviour could result.
MMU registers DPR0 DPR1 DPR2 DPR3
16-bit virtual address
00
01
10
11
2M
SB
8 bits
14 LSB
22-bit physical address
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ADDRESS SPACE EXTENSION (Cont'd) 2.6.2 Addressing 64-Kbyte Segments This extension mode is used to address Data memory space during a DMA and Program memory space during any code execution (normal code and interrupt routines). Three registers are used: CSR, ISR, and DMASR. The 6-bit contents of one of the registers CSR, ISR, or DMASR define one out of 64 Memory segments of 64 Kbytes within the 4 Mbytes address space. The register contents represent the 6 MSBs of the memory address, whereas the 16 LSBs of the address (intra-segment address) are given by the virtual 16-bit address (see Figure 11). 2.7 MMU REGISTERS The MMU uses 7 registers mapped into Group F, Page 21 of the Register File and 2 bits of the EMR2 register. Most of these registers do not have a default value after reset. 2.7.1 DPR[3:0]: Data Page Registers The DPR[3:0] registers allow access to the entire 4 Mbyte memory space composed of 256 pages of 16 Kbytes. 2.7.1.1 Data Page Register Relocation If these registers are to be used frequently, they may be relocated in register group E, by programming bit 5 of the EMR2-R246 register in page 21. If this bit is set, the DPR[3:0] registers are located at R224-227 in place of the Port 0-3 Data Registers, which are re-mapped to the default DPR's locations: R240-243 page 21. Data Page Register relocation is illustrated in Figure 9.
Figure 17. Addressing via CSR, ISR, and DMASR
MMU registers CSR DMASR ISR
16-bit virtual address
1 1 2 Fetching program instruction Data Memory accessed in DMA Fetching interrupt instruction or DMA access to Program Memory
2
3
6 bits
3
22-bit physical address
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MMU REGISTERS (Cont'd) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set.
7 0
DATA PAGE REGISTER 2 (DPR2) R242 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R226 if EMR2.5 is set.
7 0
DPR0_7 DPR0_6 DPR0_5 DPR0_4 DPR0_3 DPR0_2 DPR0_1 DPR0_0
DPR2_7 DP R2_6 DPR2_5 DPR2_4 DPR2_3 DPR2_2 DPR2_1 DPR2_0
Bits 7:0 = DPR0_[7:0]: These bits define the 16Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to extend the address during a Data Memory access. The DPR0 register is used when addressing the virtual address range 0000h-3FFFh. DATA PAGE REGISTER 1 (DPR1) R241 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R225 if EMR2.5 is set.
7 0
Bits 7:0 = DPR2_[7:0]: These bits define the 16Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR2 register is involved when the virtual address is in the range 8000h-BFFFh. DATA PAGE REGISTER 3 (DPR3) R243 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R227 if EMR2.5 is set.
7 0
DPR1_7 DPR1_6 DPR1_5 DPR1_4 DPR1_3 DPR1_2 DPR1_1 DPR1_0
DPR3_7 DP R3_6 DPR3_5 DPR3_4 DPR3_3 DPR3_2 DPR3_1 DPR3_0
Bits 7:0 = DPR1_[7:0]: These bits define the 16Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to extend the address during a Data Memory access. The DPR1 register is used when addressing the virtual address range 4000h-7FFFh.
Bits 7:0 = DPR3_[7:0]: These bits define the 16Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR3 register is involved when the virtual address is in the range C000h-FFFFh.
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MMU REGISTERS (Cont'd) 2.7.2 CSR: Code Segment Register This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruction has been executed (or ldpp, ldpd, lddp). Only the 6 LSBs of the CSR register are implemented, and bits 6 and 7 are reserved. The CSR register allows access to the entire memory space, divided into 64 segments of 64 Kbytes. To generate the 22-bit Program memory address, the contents of the CSR register is directly used as the 6 MSBs, and the 16-bit virtual address as the 16 LSBs. Note: The CSR register should only be read and not written for data operations (there are some exceptions which are documented in the following paragraph). It is, however, modified either directly by means of the jps and calls instructions, or indirectly via the stack, by means of the rets instruction. CODE SEGMENT REGISTER (CSR) R244 - Read/Write Register Page: 21 Reset value: 0000 0000 (00h)
7 0 0 CSR_5 CSR_4 CSR_3 CSR_2 CSR_1 0 CSR_0
ISR and ENCSR bit (EMR2 register) are also described in the chapter relating to Interrupts, please refer to this description for further details. Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = ISR_[5:0]: These bits define the 64Kbyte memory segment (among 64) which contains the interrupt vector table and the code for interrupt service routines and DMA transfers (when the PS bit of the DAPR register is reset). These bits are used as the most significant address bits (A21-16). The ISR is used to extend the address space in two cases: Whenever an interrupt occurs: ISR points to the 64-Kbyte memory segment containing the interrupt vector table and the interrupt service routine code. See also the Interrupts chapter. During DMA transactions between the peripheral and memory when the PS bit of the DAPR register is reset : ISR points to the 64 K-byte Memory segment that will be involved in the DMA transaction. 2.7.4 DMASR: DMA Segment Register DMA SEGMENT REGISTER (DMASR) R249 - Read/Write Register Page: 21 Reset value: undefined
7 D MA SR_5 DMA SR_4 DMA SR_3 D MA SR_2 DMA SR_1 0 D MA SR_0
Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = CSR_[5:0]: These bits define the 64Kbyte memory segment (among 64) which contains the code being executed. These bits are used as the most significant address bits (A21-16). 2.7.3 ISR: Interrupt Segment Register INTERRUPT SEGMENT REGISTER (ISR) R248 - Read/Write Register Page: 21 Reset value: undefined
7 0 0 0 ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0
0
0
Bits 7:6 = Reserved, keep in reset state. Bits 5:0 = DMASR_[5:0]: These bits define the 64Kbyte Memory segment (among 64) used when a DMA transaction is performed between the peripheral's data register and Memory, with the PS bit of the DAPR register set. These bits are used as the most significant address bits (A21-16). If the PS bit is reset, the ISR register is used to extend the addres s .
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MMU REGISTERS (Cont'd) Figure 18. Memory Addressing Scheme (example)
4M bytes
3FFFFFh
16K
294000h
DPR3 DPR2 DPR1 DPR0 16K 16K 20C000h 20 0 0h 1FFFFFh 240000h 23FFFFh
64K DMASR
040000h 03FFFFh 030000h 020000h
ISR CSR
64K 16K 64K
010000h 00C000h 0 0 00h
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2.8 MMU USAGE 2.8.1 Normal Program Execution Program memory is organized as a set of 64Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, calls and rets instructions, which automatically modify the CSR, must be used to jump across segment boundaries. Writing to the CSR is forbidden during normal program execution because it is not synchronized with the opcode fetch. This could result in fetching the first byte of an instruction from one memory segment and the second byte from another. Writing to the CSR is allowed when it is not being used, i.e during an interrupt service routine if ENC SR is reset. Note that a routine must always be called in the same way, i.e. either always with call or always with calls, depending on whether the routine ends with ret or rets. This means that if the routine is written without prior knowledge of the location of other routines which call it, and all the program code does not fit into a single 64-Kbyte segment, then calls/rets should be used. In typical microcontroller applications, less than 64 Kbytes of RAM are used, so the four Data space pages are normally sufficient, and no change of DPR [3:0] is needed during Program execution. It may be useful however to map part of the ROM into the data space if it contains strings, tables, bit maps, etc. If there is to be frequent use of paging, the user can set bit 5 (DPRREM) in register R246 (EMR2) of Page 21. This swaps the location of registers DPR [3:0] with that of the data registers of Ports 03. In this way, DPR registers can be accessed without the need to save/set/restore the Page Pointer Register. Port registers are therefore moved to page 21. Applications that require a lot of paging typically use more than 64 Kbytes of external memory, and as ports 0, 1 and 2 are required to address it, their data registers are unused. 2.8.2 Interrupts The ISR register has been created so that the interrupt routines may be found by means of the same vector table even after a segment jump/call. When an interrupt occurs, the CPU behaves in one of 2 ways, depending on the value of the ENCSR bit in the EMR2 register (R246 on Page 21). If this bit is reset (default condition), the CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, the ISR is used instead of the CSR, and the interrupt stack frame is kept exactly as in the original ST9 (only the PC and flags are pushed). This avoids the need to save the CSR on the stack in the case of an interrupt, ensuring a fast interrupt response time. The drawback is that it is not possible for an interrupt service routine to perform segment calls/jps : these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code size of all interrupt service routines is thus limited to 64 Kbytes. If, instead, bit 6 of the EMR2 register is set, the ISR is used only to point to the interrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and the flags, and then the CSR is loaded with the ISR. In this case, an iret will also restore the CSR from the stack. This approach lets interrupt service routines access the whole 4-Mbyte address space. The drawback is that the interrupt response time is slightly increased, because of the need to also save the CSR on the stack. Compatibility with the original ST9 is also lost in this case, because the interrupt stack frame is different; this difference, however, would not be noticeable for a vast majority of programs. Data memory mapping is independent of the value of bit 6 of the EMR2 register, and remains the same as for normal code execution: the stack is the same as that used by the main program, as in the ST9. If the interrupt service routine needs to access additional Data memory, it must save one (or more) of the DPRs, load it with the needed memory page and restore it before completion. 2.8.3 DMA Depending on the PS bit in the DAPR register (see DMA chapter) DMA uses either the ISR or the DMASR for memory accesses: this guarantees that a DMA will always find its memory segment(s), no matter what segment changes the application has performed. Unlike interrupts, DMA transactions cannot save/restore paging registers, so a dedicated segment register (DMASR) has been created. Having only one register of this kind means that all DMA accesses should be programmed in one of the two following segments: the one pointed to by the ISR (when the PS bit of the DAPR register is reset), and the one referenced by the DMASR (when the PS bit is set).
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3 INTERRUPTS
3.1 INTRODUCTION The ST9 responds to peripheral and external events through its interrupt channels. Current program execution can be suspended to allow the ST9 to execute a specific response routine when such an event occurs, providing that interrupts have been enabled, and according to a priority mechanism. If an event generates a valid interrupt request, the current program status is saved and control passes to the appropriate Interrupt Service Routine. The ST9 CPU can receive requests from the following sources: On-chip peripherals External pins Top-Level Pseudo-non-maskable interrupt According to the on-chip peripheral features, an event occurrence can generate an Interrupt request which depends on the selected mode. Up to eight external interrupt channels, with programmable input trigger edge, are available. In addition, a dedicated interrupt channel, set to the Top-level priority, can be devoted either to the external NMI pin (where available) to provide a NonMaskable Interrupt, or to the Timer/Watchdog. Interrupt service routines are addressed through a vector table mapped in Memory. Figure 19. Interrupt Response
n
3.2 INTERRUPT VECTORING The ST9 implements an interrupt vectoring structure which allows the on-chip peripheral to identify the location of the first instruction of the Interrupt Service Routine automatically. When an interrupt request is acknowledged, the peripheral interrupt module provides, through its Interrupt Vector Register (IVR), a vector to point into the vector table of locations containing the start addresses of the Interrupt Service Routines (defined by the programmer). Each peripheral has a specific IVR mapped within its Register File pages. The Interrupt Vector table, containing the addresses of the Interrupt Service Routines, is located in the first 256 locations of Memory pointed to by the ISR register, thus allowing 8-bit vector addressing. For a description of the ISR register refer to the chapter describing the MMU. The user Power on Reset vector is stored in the first two physical bytes in memory, 0 0 00h and 0000 01h. The Top Level Interrupt vector is located at addresses 0004h and 0005h in the segment pointed to by the Interrupt Segment Register (ISR). With one Interrupt Vector register, it is possible to address several interrupt service routines; in fact, peripherals can share the same interrupt vector register among several interrupt channels. The most significant bits of the vector are user programmable to define the base vector address within the vector table, the least significant bits are controlled by the interrupt module, in hardware, to select the appropriate vector. Note: The first 256 locations of the memory segment pointed to by ISR can contain program code. 3.2.1 Divide by Zero trap The Divide by Zero trap vector is located at addresses 0002h and 0003h of each code segment; it should be noted that for each code segment a Divide by Zero service routine is required. Warning. Although the Divide by Zero Trap operates as an interrupt, the FLAG Register is not pushed onto the system Stack automatically. As a result it must be regarded as a subroutine, and the service routine must end with the RET instruction (not IRET ).
NORMAL PROGRAM FLOW
INTERRUPT SERVICE ROUTINE
INTERRUPT
CLEAR PENDING BIT
IRET INSTRUCTION
VR001833
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INTERRUPT VECTORING (Cont'd) 3.2.2 Segment Paging During Interrupt Routines The ENCSR bit in the EMR2 register can be used to select between original ST9 backward compatibility mode and ST9+ interrupt management mode. ST9 Backward Compatibility Mode (ENCSR = 0) If ENCSR is reset, the CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, ISR is used instead of CSR, and the interrupt stack frame is identical to that of the original ST9: only the PC and Flags are pus hed. This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring a faster interrupt response time. It is not possible for an interrupt service routine to perform inter-segment calls or jumps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code segment size for all interrupt service routines is thus limited to 64K bytes. ST9+ Mode (ENCSR = 1) If ENCSR is set, ISR is only used to point to the interrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and flags, and CSR is then loaded with the contents of ISR. In this case, iret will also restore CSR from the stack. This approach allows interrupt service routines to access the entire 4 Mbytes of address space. The drawback is that the interrupt response time is slightly increased, because of the need to also save CSR on the stack. Full compatibility with the original ST9 is lost in this case, because the interrupt stack frame is different .
ENCSR Bit 0 1 Mode ST9 Compatible ST9+ Pushed/Popped PC, FLAGR, PC, FLAGR Registers CSR Max. Code Size 64KB No limit for interrupt Within 1 segment Across segments service routine
3.3 INTERRUPT PRIORITY LEVELS The ST9 supports a fully programmable interrupt priority structure. Nine priority levels are available to define the channel priority relationships: The on-chip peripheral channels and the eight external interrupt sources can be programmed within eight priority levels. Each channel has a 3bit field, PRL (Priority Level), that defines its priority level in the range from 0 (highest priority) to 7 (lowest priority). The 9th level (Top Level Priority) is reserved for the Timer/Watchdog or the External Pseudo Non-Maskable Interrupt. An Interrupt service routine at this level cannot be interrupted in any arbitration mode. Its mask can be both maskable (TLI) or non-maskable (TLNM). 3.4 PRIORITY LEVEL ARBITRATION The 3 bits of CPL (Current Priority Level) in the Central Interrupt Control Register contain the priority of the currently running program (CPU priority). CPL is set to 7 (lowest priority) upon reset and can be modified during program execution either by software or automatically by hardware according to the selected Arbitration Mode. During every instruction, an arbitration phase takes place, during which, for every channel capable of generating an Interrupt, each priority level is compared to all the other requests (interrupts or DMA). If the highest priority request is an interrupt, its PRL value must be strictly lower (that is, higher priority) than the CPL value stored in the CICR register (R230) in order to be acknowledged. The Top Level Interrupt overrides every other priority. 3.4.1 Priority Level 7 (Lowest) Interrupt requests at PRL level 7 cannot be acknowledged, as this PRL value (the lowest possible priority) cannot be strictly lower than the CPL value. This can be of use in a fully polled interrupt environment. 3.4.2 Maximum Depth of Nesting No more than 8 routines can be nested. If an interrupt routine at level N is being serviced, no other Interrupts located at level N can interrupt it. This guarantees a maximum number of 8 nested levels including the Top Level Interrupt request.
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PRIOR ITY LEVEL ARBITRATION (Cont'd) 3.4.3 Simultaneous Interrupts If two or more requests occur at the same time and at the same priority level, an on-chip daisy chain, specific to every ST9 version, selects the channel with the highest position in the chain, as shown in Table 7. on page 46 Table 7. Daisy Chain Priority for the ST92195C/D
Highest Position INTA0 INTA1 INTB0 INTB1 INTC0 INTC1 INTD0 INTD1 INT0/WDT Standard Timer 0 INT2/SPI AD Converter/I²C INT4/SYNC (EOFVBI) INT5/SYNC (FLDST) INT6/Standard Timer 1 INT7
Lowest Position
3.4.4 Dynamic Priority Level Modification The main program and routines can be specifically prioritized. Since the CPL is represented by 3 bits in a read/write register, it is possible to modify dynamically the current priority value during program execution. This means that a critical section can have a higher priority with respect to other interrupt requests. Furthermore it is possible to prioritize even the Main Program execution by modifying the CPL during its execution. See Figure 20 on page 46 Figure 20. Example of Dynamic priority level modification in Nested Mode
INTERRUPT 6 HAS PRIORITY LEVEL 6 Priority Level CPL is set to 7 4 by MAIN program ei INT6 MAIN CPL is set to 5 CPL6 > CPL5: 6 INT6 pending 7 5
INT 6 CPL=6 MAIN CPL=7
3.5 ARBITRATION MODES The ST9 provides two interrupt arbitration modes: Concurrent mode and Nested mode. Concurrent mode is the standard interrupt arbitration mode. Nested mode improves the effective interrupt response time when service routine nesting is required, depending on the request priority levels.
The IAM control bit in the CICR Register selects Concurrent Arbitration mode or Nested Arbitration M ode. 3.5.1 Concurrent Mode This mode is selected when the IAM bit is cleared (reset condition). The arbitration phase, performed during every instruction, selects the request with the highest priority level. The CPL value is not modified in this mode. Start of Interrupt Routine The interrupt cycle performs the following steps: All maskable interrupt requests are disabled by clearing CICR.IEN. The PC low byte is pushed onto system stack. The PC high byte is pushed onto system stack. If ENCSR is set, CSR is pushed onto system stack. The Flag register is pushed onto system stack. The PC is loaded with the 16-bit vector stored in the Vector Table, pointed to by the IVR. If ENCSR is set, CSR is loaded with ISR contents; otherwise ISR is used in place of CSR until iret instruction. End of Interrupt Routine The Interrupt Service Routine must be ended with the iret instruction. The iret instruction executes the following operations: The Flag register is popped from system stack. If ENCSR is set, CSR is popped from system stack. The PC high byte is popped from system stack. The PC low byte is popped from system stack. All unmasked Interrupts are enabled by setting the CICR.IEN bit. If ENCSR is reset, CSR is used instead of ISR. Normal program execution thus resumes at the interrupted instruction. All pending interrupts remain pending until the next ei instruction (even if it is executed during the interrupt service routine). Note: In Concurrent mode, the source priority level is only useful during the arbitration phase, where it is compared with all other priority levels and with the CPL. No trace is kept of its value during the ISR. If other requests are issued during the interrupt service routine, once the global CICR.IEN is re-enabled, they will be acknowledged regardless of the interrupt service routine's priority. This may cause undesirable interrupt response sequences.
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ARBITRATION MODES (Cont'd) Examples In the following two examples, three interrupt requests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service routine. Example 1 In the first example, (simplest case, Figure 21 on page 47) the ei instruction is not used within the interrupt service routines. This means that no new interrupt can be serviced in the middle of the current one. The interrupt routines will thus be serviced one after another, in the order of their priority, until the main program eventually resumes.
Figure 21. Simple Example of a Sequence of Interrupt Requests with: - Concurrent mode selected and - IEN unchanged by the interrupt routines
0 Priority Level of Interrupt Request
INT ERRUPT 2 HAS PRIORITY LEVEL 2 INT ERRUPT 3 HAS PRIORITY LEVEL 3 INT ERRUPT 4 HAS PRIORITY LEVEL 4 INT ERRUPT 5 HAS PRIORITY LEVEL 5
1
2
INT 2 CPL = 7 INT 3 CPL = 7 INT 2 INT 3 INT 4 INT 5 ei CPL = 7 INT 4 CPL = 7
3
4
5
6 INT 5 7 MAIN CPL is set to 7 MAIN CPL = 7
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ARBITRATION MODES (Cont'd) Example 2 In the second example, (more complex, Figure 22 on page 48), each interrupt service routine sets Interrupt Enable with the ei instruction at the beginning of the routine. Placed here, it minimizes response time for requests with a higher priority than the one being serviced. The level 2 interrupt routine (with the highest priority) will be acknowledged first, then, when the ei instruction is executed, it will be interrupted by the level 3 interrupt routine, which itself will be interrupted by the level 4 interrupt routine. When the level 4 interrupt routine is completed, the level 3 interrupt routine resumes and finally the level 2 interrupt routine. This results in the three interrupt serv-
ice routines being executed in the opposite order of their priority. It is therefore recommended to avoid inserting the ei instruction in the interrupt service routine in Concurrent mode. Use the ei instruction only in nested mode. WARN ING: If, in Concurrent Mode, interrupts are nested (by executing ei in an interrupt service routine), make sure that either ENCSR is set or CSR=ISR, otherwise the iret of the innermost interrupt will make the CPU use CSR instead of ISR before the outermost interrupt service routine is terminated, thus making the outermost routine fail.
Figure 22. Complex Example of a Sequence of Interrupt Requests with: - Concurrent mode selected - IEN set to 1 during interrupt service routine execution
0 Priority Level of Interrupt Request
INT ERRUPT 2 HAS PRIORITY LEVEL 2 INT ERRUPT 3 HAS PRIORITY LEVEL 3 INT ERRUPT 4 HAS PRIORITY LEVEL 4 INT ERRUPT 5 HAS PRIORITY LEVEL 5
1
2
INT 2 CPL = 7
INT 2 CPL = 7 INT 3 CPL = 7 ei INT 4 CPL = 7 INT 5 CPL = 7 INT 3 CPL = 7
3 INT 2 INT 3 INT 4 INT 5 ei 6 INT 5 7 MAIN CPL is set to 7 CPL = 7 ei
ei
4
5
ei
MAIN CPL = 7
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ARBITRATION MODES (Cont'd) 3.5.2 Nested Mode The difference between Nested mode and Concurrent mode, lies in the modification of the Current Priority Level (CPL) during interrupt processing. The arbitration phase is basically identical to Concurrent mode, however, once the request is acknowledged, the CPL is saved in the Nested Interrupt Control Register (NICR) by setting the NICR bit corresponding to the CPL value (i.e. if the CPL is 3, the bit 3 will be set). The CPL is then loaded with the priority of the request just acknowledged; the next arbitration cycle is thus performed with reference to the priority of the interrupt service routine currently being executed. Start of Interrupt Routine The interrupt cycle performs the following steps: All maskable interrupt requests are disabled by clearing CICR.IEN. CPL is saved in the special NICR stack to hold the priority level of the suspended routine. Priority level of the acknowledged routine is stored in CPL, so that the next request priority will be compared with the one of the routine currently being serviced. The PC low byte is pushed onto system stack. The PC high byte is pushed onto system stack. If ENCSR is set, CSR is pushed onto system stack. The Flag register is pushed onto system stack. The PC is loaded with the 16-bit vector stored in the Vector Table, pointed to by the IVR. If ENCSR is set, CSR is loaded with ISR contents; otherwise ISR is used in place of CSR until iret instruction.
Figure 23. Simple Example of a Sequence of Interrupt Requests with: - Nested mode - IEN unchanged by the interrupt routines
Priority Level of Interrupt Request 0 INT 0 CPL=0 CPL6 > CPL3: INT6 pending
INTERRUPT 0 HAS PRIORITY LEVEL 0 INTERRUPT 2 HAS PRIORITY LEVEL 2 INTERRUPT 3 HAS PRIORITY LEVEL 3 INTERRUPT 4 HAS PRIORITY LEVEL 4 INTERRUPT 5 HAS PRIORITY LEVEL 5 INTERRUPT 6 HAS PRIORITY LEVEL 6
1 INT0 2 INT 2 CPL=2
INT6 INT 3 CPL=3
INT 2 CPL=2
3 INT2 INT3 INT4 INT 5 CPL=5
INT2 INT 4 CPL=4
4
5 ei 6 INT5 7
CPL2 < CPL4: Serviced next
INT 6 CPL=6 MAIN CPL=7
MAIN CPL is set to 7
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ARBITRATION MODES (Cont'd) End of Interrupt Routine The iret Interrupt Return instruction executes the following steps: The Flag register is popped from system stack. If ENCSR is set, CSR is popped from system stack. The PC high byte is popped from system stack. The PC low byte is popped from system stack. All unmasked Interrupts are enabled by setting the CICR.IEN bit. The priority level of the interrupted routine is popped from the special register (NICR) and copied into CPL. If ENCSR is reset, CSR is used instead of ISR, unless the program returns to another nested routine. The suspended routine thus resumes at the interrupted instruction. Figure 23 on page 49 contains a simple example, showing that if the ei instruction is not used in the interrupt service routines, nested and concurrent modes are equivalent. Figure 24 |
