製品概要
概要
The EVLSTGAP3S3IF is a half-bridge evaluation board designed to evaluate the STGAP3S3IF isolated single gate driver.
The STGAP3S3IF is characterized by 3 A current capability, rail-to-rail outputs, and optimized UVLO and DESAT protection thresholds for IGBTs, which makes the device optimal for high-power motor drivers in industrial applications.
The gate driver has a single output pin and an internal Miller CLAMP, which optimizes positive and negative gate spikes' suppression during fast commutations in half-bridge topologies.
The board is supplied by the 5 V VAUX connection, which fed the isolated DC-DC converters for the low-side and high-side driving sections. The gate drivers can be directly supplied by VAUX if a 5 V MCU is used, or by the onboard linear regulator if a 3.3 V MCU is used. The PWM and Reset inputs can be easily controlled through dedicated connectors while diagnostic outputs are connected to an onboard LED.
Device protection features (Desaturation and Miller clamp) are connected to the recommended network on the board and can be easily evaluated through the board test points.
Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross-conduction in case of controller malfunction.
The device allows implementing negative gate driving, and the onboard isolated DC-DC converters allow working with optimized driving voltage for IGBTs.
The EVLSTGAP3S3IF board allows evaluating all of the STGAP3S3IF features while operating with a bus voltage up to 650 V.
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特徴
- Board
- Half-bridge configuration
- High-voltage rail up to 650 V (limited by the IGBT’s and capacitor’s rating)
- STGP10M65DF2 IGBTs: 650 V, 10 A
- Compatible with 5 V and 3.3 V MCUs
- VDD logic supplied by onboard-generated 3.3 V or VAUX = 5 V
- Onboard isolated DC-DC converters to supply high-side and low-side gate drivers, fed by VAUX = 5 V, with 5.4 kVpk maximum isolation
- Easy jumper selection of driving voltage configuration:+15/0 V; +15/-4.7 V; +12/0 V; +12/-4.7 V
- Fault LED indicators
- Maximum working voltage across isolation: 650 V
- RoHS compliant
- STGAP3S3IF device
- Driver current capability: 3 A source/sink @ 25 °C
- 75 ns input-output propagation delay
- Internal Miller CLAMP
- UVLO function
- Desaturation protection
- Gate driving voltage up to 32 V
- Negative gate driving voltage
- 3.3 V, 5 V TTL/CMOS inputs with hysteresis
- Temperature shutdown protection
- Reinforced galvanic isolation:Isolation voltage VISO = 5.7 kVRMS (UL 1577)Transient overvoltage VIOTM = 8 kVPEAK (IEC 60747-17)Max. repetitive isolation voltage VIORM = 1.2 kVPEAK (IEC 60747-17)
- Board
品質 & 信頼性
| 製品型番 | マーケティング･ステータス | パッケージ | グレード | RoHSコンプライアンスグレード | WEEE Compliant | Longevity Commitment | Longevity Starting Date | 材料宣誓書** |
|---|---|---|---|---|---|---|---|---|
| EVLSTGAP3S3IF | 量産中 交換品交換品 | CARD | インダストリアル | Ecopack1 | - | - | - | |
EVLSTGAP3S3IF
Package:
CARDMaterial Declaration**:
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サンプル & 購入
| 製品型番 | 製品ステータス | Budgetary Price (US$)*/Qty | STから購入 | Order from distributors | パッケージ | 梱包形態 | RoHS | 原産国 | ECCN（米国） | ECCN（EU） | サプライヤ | コア製品 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| EVLSTGAP3S3IF | | | distributors 販売代理店に在庫がない場合は、STのセールス･オフィスまでお問い合わせください |
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EVLSTGAP3S3IF 量産中
販売代理店に在庫がない場合は、STのセールス･オフィスまでお問い合わせください
（*）概算用の参考価格（US$）です。現地通貨でのお見積りについては、STのセールス･オフィスまたは販売代理店までお問い合わせください。