製品概要
概要
The STiDP888 is a high-speed Dual LVDS/Quad LVDS to an internal DisplayPort converter IC targeted for the interconnection between a TV controller SOC and a panel TCON. STiDP888 is a VESA iDP compliant device, implementing a single link internal DisplayPort output comprising four Main Link lanes and HPD, which operates without a sideband channel. This device supports the standard iDP link rate of 3.24 Gbps per lane with a total link bandwidth of 12.96 Gbps, allowing interface connectivity from TV SoC to a wide range of panels up to FHD 120 Hz and 10 bits per color. The advanced pre-emphasis technology built in this device offers robust performance over FFC and UTP type cables.
The STiDP888 supports RGB video color formats with color depth of 10 and 8 bits. This device offers LVDS input interface configurable to map a wide range of pixel data mapping from TV SoCs, such as JEIDA, non-JEIDA, and VESA types. The Quad LVDS interface supports video signals up to 400 MHz pixel rate with flexible channel and lane swapping options. In Dual LVDS configuration, STiDP888 can support up to 300 MHz pixel rate.
The STiDP888 is designed to operate in standalone mode (without any programming from an external microcontroller) with default configuration of four-lane DP output and QLVDS input with non-JEIDA mapping. However, the device is configurable from an external microcontroller through I2C host interface for custom configuration.
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特徴
- Internal DisplayPort (iDP) transmitter
- Compliant with iDP specification
- 3.24 Gbps per lane
- 1, 2, or 4 lanes
- HPD pulse handling as per iDP standard
- Supports video timings up to 1920 x 1080 (FHD) 120 Hz/10-bit color
- Interface compatibility with wide range of TV SoCs
- Quad LVDS interface up to 100 MHz per channel (400 MHz pixel rate)
- High speed dual-link LVDS up to 150 MHz per channel (300 MHz pixel rate)
- Supports JEIDA, non-JEIDA, VESA pixel pixel data mappings
- Supports Asynchronous Scrambler Seed Reset (ASSR) for premium contents transmission
- Configurable through I2C host interface
- Supports Spread Spectrum for EMI/RFI reduction
- Robust interoperability – supports FFC and UTP type cables; full programmability of voltage swing and pre-emphasis levels
- Low power operation; 20 mW standby
- パッケージ
- 164 LFBGA (12 x 12 mm/0.8 mm pitch)
- HF and RoHS compliant
- Power supply voltages
- 3.3 V I/O; 1.2 V core
- ESD
- 2 KV HBM, 200 V MM, 600V CDM
- Internal DisplayPort (iDP) transmitter
回路ダイアグラム
EDAシンボル / フットプリント / 3Dモデル
STマイクロエレクトロニクス - STiDP888
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