The STM32H745/755 lines offer the performance of the Cortex-M7 core (with double-precision floating point unit) running up to 480 MHz and the Cortex-M4 core (with single-precision floating point unit) running up to 240 MHz while reaching two times better dynamic power consumption (Run mode) versus the STM32F7 lines.
Performance
At 480 MHz fCPU on the Cortex-M7 and 240 MHz on the Cortex-M4, the STM32H745/755 lines deliver a total of 3220 CoreMark / 1327 DMIPS performance executing from Flash memory, with 0-wait states thanks to its L1 cache or the ART. The DSP instructions and the double-precision FPU enlarge the range of addressable applications. External memory can be used with no performance penalty thanks to the L1 cache (16 Kbytes +16 Kbytes of I-cache and D-cache) on the Cortex-M7 or the ART (Adaptive Real Time accelerator) on the Cortex-M4.
Security
The Secure Firmware Install and Secure Boot – Secure Firmware Upgrade (available in Q3’2019) can be used to perform the initial programming of the device in a secured manner, or to perform a secured field upgrade of the code. These services are only available with STM32H755 devices embedding a crypto/hash processor.
Power efficiency:
The multi-power domain architecture allows the different power domains to be set in low-power mode to optimize the power efficiency. In addition to the on-chip SMPS featuring voltage scaling to supply the core in different voltage ranges during Run and Stop modes, the device also embeds a USB regulator to supply the embedded physical layer (PHY) and a backup regulator.
- 275 µ/MHz typical @VDD = 3.3 V and 25 °C in Run mode (peripherals off)
- 2.95 µA in Standby mode (low-power mode)
Graphics
The new LCD-TFT controller interface with dual-layer support takes advantage of the Chrom‑ART Accelerator™. This graphics accelerator creates content twice as fast as the core alone. As well as efficient 2-D raw data copy, additional functions are supported by the Chrom-ART Accelerator such as image format conversion or image blending (image mixing with a defined level of transparency). As a result, the Chrom-ART Accelerator™ boosts graphics content creation and saves the processing bandwidth of the MCU core for the rest of the application. In addition, the STM32H745/755 lines embed a JPEG hardware accelerator for fast JPEG encoding and decoding, off-loading the CPUs which remain available for other tasks.
Integration
- Audio: Two dedicated audio PLLs, three full-duplex I²S interfaces, a new serial audio interface (SAI) supporting time-division multiplex (TDM) mode and a DFSDM (Digital filters for sigma-delta modulators or MEMS microphone).
- Up to 35 communication interfaces including four USARTs in addition to four UARTs running at up to 12.5 Mbit/s, one low-power UART, six SPIs running at up to 100 Mbit/s, four I²C interfaces running at up to 1 MHz with a new optional digital filter capability, two FD-CAN, two SDIO, USB 2.0 full-speed device/host/OTG controller with an on-chip PHY and a USB 2.0 high-speed/full-speed device/host/OTG controller, on-chip full-speed PHY and ULPI, Ethernet MAC, SPDIF-IN, HDMI-CEC, camera interface, single wire protocol interface and MDIO slave.
- Analog: Two 12-bit DACs, three fast ADCs reaching 16-bit maximum resolution (3.6 Msamples/s), 22 16- and 32-bit timers running at up to 480 MHz on the 16-bit high-resolution timer. Easily extendable memory range using the flexible memory controller with a 32-bit parallel interface, and supporting Compact Flash, SRAM, PSRAM, NOR, NAND and SDRAM memories or using the Dual-mode Quad-SPI to execute code from external serial Flash memory. An analog true random number generator.
The STM32H7x5 provides from 1 to 2 Mbytes of Flash memory, 1 Mbyte of SRAM with a scattered architecture: 192 Kbytes of TCM RAM (including 64 Kbytes of ITCM RAM and 128 Kbytes of DTCM RAM for time-critical routines and data), 64, 288 or 512 Kbytes of user SRAM, and 4 Kbytes of SRAM in backup domain to keep data in the lowest power modes and 144- to 240-pin packages in BGA and LQFP profiles.
The STM32H7x5 embeds a SMPS to scale down the supply voltage and generate the appropriate voltage for the core. Thanks to the improved power conversion efficiency of the SMPS, the STM32H7x5 offers the possibility to sustain extended ambient temperature up to 125 °C on selected devices. The SMPS can also be used to supply external circuitry. The SMPS can also be combined with the LDO for specific use cases.
The STM32H755 integrates a crypto/hash processor providing hardware acceleration for AES-128, -192 and -256 encryption, with support for GCM and CCM, Triple DES, and hash (MD5, SHA-1 and SHA-2) algorithms. The STM32H755 also enables SFI and SB-SFU security services to authenticate and protect your software IPs while performing initial programming or firmware upgrades in the field.
ビデオ
The STM32Cube.AI is an extension pack of the widely used STM32CubeMX configuration and code generation tool enabling AI on STM32 Arm® Cortex®-M-based microcontrollers.
Get in depth knowledge with STM32 microcontrollers On Line Trainings
More and more devices have complex graphical user interfaces - much like smartphones - and ST's range of STM32 microcontrollers has a host of features which can be leveraged on a huge range of devices. We are constantly innovating to give you the performance you need!
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STM32H755BI
High-performance and DSP with DP-FPU, Arm Cortex-M7 + Cortex-M4 MCU with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, large set of peripherals including a Crypto accelerator, with security services support, SMPS
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STM32H745BI
High-performance and DSP with DP-FPU, Arm Cortex-M7 + Cortex-M4 MCU with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, large set of peripherals, SMPS
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STM32H745XG
High-performance and DSP with DP-FPU, Arm Cortex-M7 + Cortex-M4 MCU with 1MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, large set of peripherals, SMPS
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STM32H745XI
High-performance and DSP with DP-FPU, Arm Cortex-M7 + Cortex-M4 MCU with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, large set of peripherals, SMPS
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STM32H755XI
High-performance and DSP with DP-FPU, Arm Cortex-M7 + Cortex-M4 MCU with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, large set of peripherals including a Crypto accelerator, with security services support, SMPS
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STM32H745ZG
High-performance and DSP with DP-FPU, Dual core Arm Cortex-M7+ Cortex-M4 MCU with 1MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, large set of peripherals, SMPS
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STM32H745IG
High-performance and DSP with DP-FPU, Arm Cortex-M7 + Cortex-M4 MCU with 1MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, large set of peripherals, SMPS
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STM32H755II
High-performance and DSP with DP-FPU, Arm Cortex-M7 + Cortex-M4 MCU with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, large set of peripherals including a Crypto accelerator, with security services support, SMPS
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STM32H745ZI
High-performance and DSP with DP-FPU, Dual core Arm Cortex-M7+ Cortex-M4 MCU with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, large set of peripherals, SMPS
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STM32H745II
High-performance and DSP with DP-FPU, Arm Cortex-M7 + Cortex-M4 MCU with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, large set of peripherals, SMPS
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STM32H745BG
High-performance and DSP with DP-FPU, Arm Cortex-M7 + Cortex-M4 MCU with 1MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, large set of peripherals, SMPS
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STM32H755ZI
High-performance and DSP with DP-FPU, Arm Cortex-M7 + Cortex-M4 MCU with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, large set of peripherals including a Crypto accelerator, with security services support, SMPS
