The SPEAr310 is a member of the SPEAr family of embedded MPUs, optimized for telecom applications. It is based on the powerful ARM926EJ-S processor (up to 333 MHz), widely used in applications where high computation performance is required.
In addition, SPEAr310 has an MMU that allows virtual memory management -- making the system compliant with advanced operating systems, like Linux. It also offers 16 KB of data cache, 16 KB of instruction cache, JTAG and ETM (embedded trace macro-cell) for debug operations.
A full set of peripherals allows the system to be used in many applications, some typical applications being routers, switches and gateways as well as remote apparatus control and metering concentrators.
C3 Cryptographic accelerator
2 x USB 2.0 Host USB 2.0 Device 1 x fast Ethernet MII port 4 x fast Ethernet SMII ports 1 x SSP Synchronous serial peripheral (SPI, Microwire or TI protocol) with 4 chip selects 1 x I2C 1 x fast IrDA interface 6 x UART interface 1x TDM/E1 HDLC interface with 128/32 timeslots per frame respectively 2x RS485 HDLC ports
- ARM926EJ-S 333 MHz core
- Dynamic power-saving features
- High-performance 8-channel DMA
32 KB ROM and 8 KB internal SRAM LPDDR-333/DDR2-666 external memory interface Serial Flash Memory interface (SMI) Flexible static memory controller (FSMC) up to 16-bit data bus width, supporting NAND Flash External memory interface (EMI) up to 32- bit data bus width, supporting NOR Flash and FPGAs
- Miscellaneous functions
Integrated real time clock, watchdog, and system controller 8-channel 10-bit ADC, 1 Msps JPEG CODEC accelerator Six 16-bit general purpose timers with programmable prescaler, 4 capture inputs Up to 102 GPIOs with interrupt capability
- Configurable peripheral functions multiplexed on 102 shared I/Os
|LFBGA 289 15x15x1.7||インダストリアル||Ecopack2|
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