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SPC560D30L3

量産中
Education
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32-bit Power Architecture MCU for Automotive Body and Gateway Applications

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製品概要

概要

These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices designed to be central to the development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control and seat control applications. This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology and designed specifically for embedded applications.
The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the Power Architecture technology and only implements the VLE (variable-length encoding) APU (auxiliary processing unit) and provides improved code density. It operates at speed of up to 48 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with the user’s implementations.
The device platform has a single level of memory hierarchy and can support a wide range of on-chip static random access memory (SRAM) and internal flash memory.

  • 特徴

    • AEC-Q100 qualified
    • High-performance up to 48 MHz e200z0h CPU
      • 32-bit Power Architecture® technology CPU
      • Variable length encoding (VLE)
    • Memory
      • Up to 256 KB Code Flash with ECC
      • Up to 64 (4x16) KB Data Flash with ECC
      • Up to 16 KB SRAM with ECC
    • Interrupts
      • 16 priority levels
      • Non-maskable interrupt (NMI)
      • Up to 38 external interrupts including 18 wakeup lines
    • 16-channel eDMA
    • GPIOs: 45 (LQFP64), 79 (LQFP100)
    • Timer units
      • 4-channel 32-bit periodic interrupt timers
      • 4-channel 32-bit system timer module
      • System watchdog timer
      • 32-bit real-time clock timer
    • 16-bit counter time-triggered I/Os
      • Up to 28 channels with PWM/MC/IC/OC
      • 5 independent counters
      • 27-channels with ADC trigger capability
    • 12-bit analog-to-digital converter (ADC) with up to 33 channels
      • Up to 61 channels via external multiplexing
      • Individual conversion registers
      • Cross triggering unit (CTU)
    • Dedicated diagnostic module for lighting
      • Advanced PWM generation
      • Time-triggered diagnostics
      • PWM-synchronized ADC measurements
    • Communications interfaces
      • 1 FlexCAN interface (2.0B active) with32 message buffers
      • 3 LINFlex/UART, 1 with DMA capability
      • 2 DSPI
    • Clock generation
      • 4 to 16 MHz fast external crystal oscillator
      • 16 MHz fast internal RC oscillator
      • 128 kHz slow internal RC oscillator
      • Software-controlled FMPLL
      • Clock monitoring unit
    • Exhaustive debugging capability
      • Nexus1 on all packages
      • Nexus2+ available on emulation device (SPC560B64B2-ENG)
    • On-chip CAN/UART bootstrap loader
    • Low power capabilities
      • Several low power mode configurations
      • Ultra-low power standby with RTC, SRAM and CAN monitoring
      • Fast wakeup schemes
    • Single 5 V or 3.3 V supply
    • Operates in ambient temperature range of-40 to 125 °C
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