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  • The C65SPACE is fabricated on a proprietary 65nm, 7 metal layers CMOS process intended for use with a core voltage of 1.2V ±0.10V.The ST standard-cells, memories and PLL have been designed and characterized to be compatible with each other.

    Key Features

    • プロセス
      • STMicroelectronics C65SPACE (65nm CMOS)
      • 3.3V IO gate oxide GO2 (5nm)
      • 1.2V core gate oxide GO1 (1.8nm), triple VT transistors
      • 7 copper metallization,5 thin and 2 thick
      • Low-K inter-metallic dielectrics for thin metal layers
      • High density SRAMs
      • Compatible with flip-chip and wire bonding packaging
    • Radiations
      • SEL-free up to LET = 60Mev/mg/cm2 at 125°C Tj and Vdd max
      • SEE hardened library
      • Tested up to a total dose of 300 krads (Si)
    • Reliability
      • Library cells models with 20 years aging
      • Transistor models including aging alteration
      • ESD better than:
        • 2kV in HBM (Class 2 / MIL-STD-883H)
        • 150V in MM
        • 250V in CDM
    • ライブラリオファー
      • Comprehensive library of standard logic with PVT and aging corners models
      • IO pad libraries provide interfaces at 3.3V +/-0.30V, 2.5V+/-0.25V and 1.8V +/-0.15V
      • High speed IO Pad LVDS supplied at 2.5V +/-0.25V up to 650Mbps
      • Cold sparing IOs with single/double row support
      • Memories generation: single port SRAM, ROM, Dual port SRAMs, BIST library, EDAC library
      • Wide-range PLLs 1.2GHz with multi-phase outputs
      • 6.25Gbit/s high speed serial links (HSSL)
    • Design flow
      • An ST customized design flow (RTL to GDS) invoking commercial solutions (Synopsys, Cadence, Mentor…) is available for partners and certified design houses:
        • Front-End kit from RTL to gates based
        • SiPKit for IO ring generation
        • FFKit for place and route
        • SignOffKit for final verification before tape-out
      • For customer owned tools (COT) flow, ST provides the C65SPACE design platform along with the DRM and sign-off kit.

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製品型番
概要
技術
Agency Qualification
Agency Generic Spec
ECCN (US)
Country of Origin
販売代理店からオーダー
STからオーダー
C65SPACE Rad hard 65nm CMOS technology platform for space applications 65nm ESA ESCC2269000 - - 販売代理店に在庫がない場合は、STのセールスオフィスまでお問い合わせください

C65SPACE

概要

Rad hard 65nm CMOS technology platform for space applications

技術

65nm

Agency Qualification

ESA

Agency Generic Spec

ESCC2269000

ECCN (US)

-

Country of Origin

-

(*) Suggested Resale Price per unit (USD) for BUDGETARY USE ONLY. For quotes, prices in local currency, please contact your local ST Sales Office  or our Distributors

推奨コンテンツ

関連アプリケーション

00 ファイルがダウンロード用に選択されています

技術文書

    • 概要 バージョン サイズ アクション
      DB2500
      Rad hard 65nm CMOS technology platform for space applications
      1.0
      60.54 KB
      PDF
      DB2500

      Rad hard 65nm CMOS technology platform for space applications

関連資料

    • 概要 バージョン サイズ アクション
      List of recent ST technical papers on rad-hard technology
      135.39 KB
      PDF

      List of recent ST technical papers on rad-hard technology

製品型番 製品ステータス パッケージ グレード RoHSコンプライアンスグレード Material Declaration**
C65SPACE
アクティブ
- インダストリアル -

C65SPACE

Package:

-

Material Declaration**:

Marketing Status

アクティブ

Package

-

Grade

Industrial

RoHS Compliance Grade

-

(**) The Material Declaration forms available on st.com may be generic documents based on the most commonly used package within a package family. For this reason, they may not be 100% accurate for a specific device. Please contact our sales support for information on specific devices.