製品概要
概要
The SR5E1x MCU family has been designed to meet the enhanced digital control and high-performance analog requested by the new wide band gap power technologies, silicon carbide and GAN, from power conversion applications such as on-board charger and DC/DC converters as well as advanced motor control like traction inverter applications.
SR5E1x also offers superior real-time and safe performance with highest ASIL-D capability, security cryptographic services (HSM) and high efficiency OTA reprogramming capability.
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特徴
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- AEC-Q100 automotive qualification on going
- SR5 high-performance analog MCUs offering:
- Digital and analog high-frequency control requested by new wide-bandgap technologies (Silicon Carbide and Gallium Nitride)
- Superior real-time and functional safety performance (ASIL-D capability)
- Built-in fast and cost optimized OTA (over-the-air) reprogramming capability (with built-in dual image storage)
- High-speed security cryptographic services (HSM)
- Cores
- 2x 32-bit Arm® Cortex®M7 with double-precision FPU, L1 cache and DSP instructions
- Split-lock configuration, allowing either 2 cores in parallel or 1 core in lockstep configuration
- 2 DMA engines in lockstep configuration
- 2x 32-bit Arm® Cortex®M7 with double-precision FPU, L1 cache and DSP instructions
- Memories
- Up to 2 MB on-chip Flash memory with read while write support
- 1920 KB code Flash memory split in two banks allowing 960 KB OTA reprogramming support
- 160 KB HSM dedicated code Flash memory
- 96 KB data Flash memory (64 KB + 32 KB dedicated to HSM)
- 488 KB on-chip general-purpose SRAM:
- 2x 32 KB instruction TCM + 2x 64 KB data TCM
- 256 KB system RAM
- 40 KB HSM dedicated system RAM
- Up to 2 MB on-chip Flash memory with read while write support
- Security: hardware security module (HSM)
- On-chip high-performance security module with dedicated RAM and Flash
- Based on Cortex®M0+ core
- Hardware accelerator for symmetric cryptography
- Safety: comprehensive new generation ASIL-D safety concept
- State of the art safety measures at all level of the architecture for most efficient implementation of ISO26262 ASIL-D functionalities
- FCCU for collection and reaction to failure notifications with enhanced configurability
- Memory error management unit (MEMU) for collection and reporting of error events in memories
- Cyclic redundancy check (CRC) unit
- Enhanced peripherals for fast control loop capability
- 12 Timers:
- 2x HRTIM (high-resolution and complex waveform builder)
- 2x advanced control timers
- 2x 32-bit + 4x 16-bit general purpose timers
- 2x basic timers
- Enhanced analog-to-digital converter system with:
- 5 SAR analog converters
- 2 sigma-delta analog converters
- Digital-to-analog converters (DAC)
- 2 buffered external channels
- 8 unbuffered internal channels
- 8 comparators
- Hardware accelerator
- 1x CORDIC for trigonometric functions acceleration
- 12 Timers:
- Communication interfaces
- 4 modular controller area network (MCAN) modules, all supporting flexible data rate (ISO CAN-FD)
- 3 UART modules with LIN functionality
- 4 serial peripheral interface (SPI) modules, 2 multiplexed with I²S interfaces
- 2 I²C modules
- Advanced debug and trace for high-performance automotive application development
- Built around Arm® CoreSightTM-600
- Debug interface: Arm® CoreSightTM JTAG (IEEE 1149.1) or SWD
- Embedded trace FIFO for both on- and off-chip tracing
- Trace port for off-chip tracing: parallel trace port configurable from 1 to 8 data lines
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