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SR5 E1 line of Stellar electrification MCUs, 32-bit Arm Cortex M7 automotive MCU 2x cores, 2 MB Flash, rich analog, high-resolution timer, HSM, ASIL-D

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Product overview


The SR5E1E3, SR5E1E5, SR5E1E7 MCU family has been designed to meet the enhanced digital control and high-performance analog requested by the new wide bandgap power technologies, silicon carbide and GAN, from power conversion applications such as on-board charger and DC/DC converters as well as advanced motor control like traction inverter applications.

SR5E1E3, SR5E1E5, SR5E1E7 also offer superior real-time and safe performance with the highest ASIL-D capability, security cryptographic services (HSM) and high efficiency OTA reprogramming capability.

  • All features

      • AEC-Q100 automotive qualification on going
      • SR5 high-performance analog MCUs offering:
        • Digital and analog high-frequency control requested by new wide-bandgap technologies (silicon carbide and gallium nitride)
        • Superior real-time and functional safety performance (ASIL-D capability)
        • Built-in fast and cost-optimized OTA (over-the-air) reprogramming capability (with built-in dual-image storage)
        • High-speed security cryptographic services (HSM)
    • Cores
      • 2× 32-bit Arm® Cortex®‑M7 with double-precision FPU, L1 cache and DSP instructions running at up to 300 MHz to reach 1284 DMIPS/2.14 DMIPS/MHz/Core (Dhrystone 2.1)
        • Split-lock configuration, allowing either 2 cores in parallel or 1 core in lockstep configuration
      • 2 DMA engines in lockstep configuration
    • Memories
      • Up to 2 MB on-chip flash memory with read while write support
        • 1920 KB code flash memory split in two banks allowing 960 KB OTA reprogramming support
        • 160 KB HSM dedicated code flash memory
      • 96 KB data flash memory (64 KB + 32 KB dedicated to HSM)
      • 488 KB on-chip general-purpose SRAM:
        • 2× 32 KB instruction TCM + 2× 64 KB data TCM
        • 256 KB system RAM
        • 40 KB HSM dedicated system RAM
    • Security: hardware security module (HSM)
      • On-chip high-performance security module with EVITA medium support with dedicated RAM and flash memory
      • Based on Cortex®‑M0+ core running at up to 150 MHz
      • Hardware accelerator for symmetric cryptography
    • Safety: comprehensive new generation ASIL-D safety concept
      • State of the art safety measures at all level of the architecture for most efficient implementation of ISO26262 ASIL-D functionalities
      • FCCU for collection and reaction to failure notifications with enhanced configurability
      • Memory error management unit (MEMU) for collection and reporting of error events in memories
      • Cyclic redundancy check (CRC) unit
    • Enhanced peripherals for fast control loop capability
      • 12 Timers:
        • 2× HRTIM (high-resolution and complex waveform builder): 12× 16-bit counters, up to 102 ps resolution, 24 PWM in total
        • 2× 16-bit 6-channel advanced control timers, with up to 12× PWM, in total
        • 2× 32-bit general purpose timers, with up to 8× IC/OC/PWM or pulse counter and quadrature encoder input in total
        • 4× 16-bit general purpose timers, with up to 11× PWM, 2 of which paired, in total
        • 2× 16-bit basic timers
      • Enhanced analog-to-digital converter system with:
        • 5 separate 12-bit SAR analog converters, 8 channels each. Sampling rate up to 2.5 MSPS in single mode, 5 MSPS in dual mode
        • 2 separate 16-bit sigma-delta analog converters
      • 12-bit digital-to-analog converters (DAC)
        • 2 buffered external channels 1 MSPS
        • 8 unbuffered internal channels 15 MSPS
      • 8 rail-to-rail analog comparators, 50 ns propagation delay
      • Hardware accelerator
        • 1× CORDIC for trigonometric functions acceleration
    • Communication interfaces
      • 4 modular controller area network (MCAN) modules, all supporting flexible data rate (ISO CAN-FD)
      • 3 UART modules with LIN functionality
      • 4 serial peripheral interface (SPI) modules, 2 multiplexed with I²S interfaces
      • 2 I²C modules
    • Advanced debug and trace for high-performance automotive application development
      • Built around Arm® CoreSight™-600
      • Debug interface: Arm® CoreSight™ JTAG (IEEE 1149.1) or SWD
      • 4 KB embedded trace FIFO for both on- and off-chip tracing
      • Trace port for off-chip tracing: parallel trace port configurable from 1 to 8 data lines
    • Others
      • Power efficiency management, through separate power modes for any selected cores, peripherals or memories
      • Boot assist flash (BAF) supports factory programming using a serial loader through CAN or UART
      • Junction temperature range -40 °C to 150 °C
      • Integrated power supply scheme:
        • Integrated internal SMPS regulator
        • 3.3 V supply & GPIOs

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STMicroelectronics - SR5E1E3

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