STM32MP215D

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製品概要

主な利点

メインライン版OpenSTLinuxディストリビューション

STM32MPUファミリと互換性のあるOpenSTLinuxソフトウェア。OpenSTLinux拡張パッケージを適用することで、追加コンポーネントを使用可能。

市場優位性の確保を支援するDDR3L

DDR4/LPDDR4に加え、STM32MP2シリーズはDDR3Lメモリもサポートしているため、2025年半ば以降に見られるDDR4/LPDDR4の供給不足や価格高騰といった状況下でも、競争力のある価格設定と安定した供給を維持できます。

概要

STM32MP21xA/D devices are based on the high-performance core Arm® Cortex®-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex®‑A35 processor includes a 32-Kbyte L1 instruction cache, a 32-Kbyte L1 data cache, and a 128-Kbyte L2 cache. The Cortex®‑A35 processor uses a highly efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.

STM32MP21xA/D devices also embed a Cortex®-M33 32-bit RISC core operating at up to 300 MHz frequency. The Cortex®-M33 core features a floating-point unit (FPU) single precision which supports Arm® single-precision data-processing instructions, and data types. The Cortex®-M33 supports a full set of DSP instructions, TrustZone®, and a memory protection unit (MPU) which enhances application security.

STM32MP21xA/D devices provide an external SDRAM interface supporting external memories up to 4 Gbytes, 16‑bit DDR3L up to 800 MHz, 16‑bit LPDDR4, or DDR4 up to 800 MHz.

The devices incorporate high-speed embedded memories: 456 Kbytes of internal SRAM (including 256-Kbyte AXI SYSRAM), one bank of 64 Kbytes of AHB SRAM, 128 Kbytes of AHB SRAM in backup domain, and 8 Kbytes of SRAM in backup domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, a 32-bit multi-AHB bus matrix, and a 128/64-bit multilayer AXI interconnect supporting access to internal and external memories.

Each device offers two ADCs, a low-power secure RTC, 12 general-purpose 16-bit timers, four general-purpose 32‑bit timers, two PWM timers for motor control, five low-power timers, two true random number generator (RNG).

The devices support four multifunction digital filters (MDF)

特徴
Includes ST state-of-the-art patented technology.

Cores

64-bit single-core Arm^® Cortex^®-A35
Up to 1.5 GHz
32-Kbyte I + 32-Kbyte D level 1 cache for each core
128-Kbyte level 2 cache
Arm^® NEON™ and Arm^® TrustZone^®

32-bit Arm^® Cortex^®-M33 with FPU/MPU
Up to 300 MHz
L1 16-Kbyte I / 16-Kbyte D
Arm^® TrustZone^®

メモリ

External DDR memory up to 4 Gbytes
DDR3L-1600 16-bit
DDR4-1600 16-bit
LPDDR4-1600 16-bit

456-Kbyte internal SRAM: 256-Kbyte AXI SYSRAM, 64-Kbyte AHB SRAM, 128-Kbyte AHB SRAM with ECC in backup domain, 8-Kbyte SRAM with ECC in backup domain

One Octo-SPI memory interfaces

Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs, and SLC NAND memories with up to 8-bit ECC

Security/safety

TrustZone^® peripherals, active tamper, environmental monitors, display secure layer, hardware accelerators

Complete resource isolation framework

Reset and power management

1.71 to 1.95 V and 2.7/3.0 to 3.6 V multiple section I/O supply

POR, PDR, PVD, and BOR

On-chip LDO and power-switches for RETRAM, BKPSRAM, and VSW

Dedicated supplies for Cortex^®-A35

Internal temperature sensor

Low-power modes: Sleep, Stop, and Standby

DDR memory retention in Standby mode

Controls for PMIC companion chip

Low-power consumption

Clock management

Internal oscillators: 64 MHz HSI, 16 MHz MSI, 32 kHz LSI

External oscillators: 16-48 MHz HSE, 32.768 kHz LSE

Up to 7× PLLs with fractional mode

General-purpose inputs/outputs

Up to 123 secure I/O ports with interrupt capability
Up to six wake-up inputs
Up to seven tamper input pins + 5 active tampers output pins

Interconnect matrix

Bus matrices
128-, 64-, 32-bit STNoC interconnect, up to 600 MHz
32-bit Arm^® AMBA^® AHB interconnect, up to 300 MHz
3 DMA controllers to unload the CPU

48 physical channels in total

3× dual master port, high-performance, general-purpose, direct memory access controller (HPDMA), 16 channels each

Up to 37 communication peripherals

3× I²C FM+ (1 Mbit/s, SMBus/PMBus^®)

3× I³C (12.5 Mbit/s)

3× UART + 4× USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI) + 1× LPUART

6× SPI (50 Mbit/s, including 3 with full duplex I²S audio class accuracy via internal audio PLL or external clock)(+1 with OCTOSPI + 4 with USART)

4× SAI (stereo audio: I²S, PDM, SPDIF Tx)

SPDIF Rx with four inputs

3× SDMMC up to 8-bit (SD/e•MMC™/SDIO)

Up to 2× CAN controllers supporting CAN FD protocol, out of which one supports time-triggered CAN (TTCAN)

1× USB 2.0 high-speed Host with embedded 480 Mbits/s PHY

1× USB 2.0 high-speed dual role data with embedded 480 Mbits/s PHY

Up to 2× Gigabit Ethernet interfaces
TSN, IEEE 1588v2 hardware, MII/RMII/RGMII

Camera interface #1 (5 Mpixels at 30 fps)
MIPI CSI-2^®, 2× data lanes up to 2.5 Gbit/s each
8- to 16-bit parallel, up to 120 MHz
RGB, YUV, JPG, RawBayer with light ISP
Lite-ISP, demosaicing, downscaling, cropping, 3 pixel pipelines

Camera interface #2 (1 Mpixels at 15 fps)
8- to 14-bit parallel, up to 80 MHz
RGB, YUV, JPG
Cropping

Digital parallel interface up to 16-bit input or output

5 analog peripherals

2 × ADCs with 12-bit max. resolution (up to 5 Msps each, up to 23 channels)

Internal temperature sensor (DTS)

1× multifunction digital filter (MDF) with up to 4 channels/4 filters

Internal (VREFBUF) or external ADC reference V_REF+

Graphics

LCD-TFT controller, up to 24-bit // RGB888
Up to FHD (1920 × 1080) at 60 fps
3 layers including a secure layer
YUV support

Up to 28 timers and 5 watchdogs

4× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

2× 16-bit advanced motor control timers

10× 16-bit general-purpose timers (including 2 basic timers without PWM)

5× 16-bit low-power timers

Secure RTC with subsecond accuracy and hardware calendar

4 Cortex^®-A35 system timers (secure, nonsecure, virtual, hypervisor)

2× SysTick Cortex^®-M33 timer (secure, nonsecure)

5× watchdogs (4× independent and 1× window)

Hardware acceleration

ECDSA verification with SCA

2x HASH (SHA-1, SHA-224, SHA-256, SHA3), HMAC

2x true random number generator

CRC calculation unit

Debug mode

Arm^® CoreSight™ trace and debug: SWD and JTAG interfaces

12288-bit fuses including 96-bit unique ID

All packages are ECOPACK2 compliant
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ハードウェアモデル (1)

	タイトル	バージョン	更新日
ZIP	STM32MP2 Series DDR memory routing guidelines examples	6.0	05 May 2025	ZIP	05 May 2025 STM32MP2 Series DDR memory routing guidelines examples 6.0

System View Description (1)

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ZIP	STM32MP2 System View Description	1.2	05 May 2025	ZIP	05 May 2025 STM32MP2 System View Description 1.2

IBIS models (1)

	タイトル	バージョン	更新日
ZIP	STM32MP2x IBIS models	3.3	15 Oct 2025	ZIP	15 Oct 2025 STM32MP2x IBIS models 3.3

BSDL files (1)

	タイトル	バージョン	更新日
ZIP	STM32MP2 BSDL files	3.0	15 Oct 2025	ZIP	15 Oct 2025 STM32MP2 BSDL files 3.0

品質 & 信頼性

製品型番	マーケティング･ステータス	パッケージ	グレード	RoHSコンプライアンスグレード	Longevity Commitment	Longevity Starting Date
STM32MP215DAL3	量産中	VFBGA 361 10x10X1.0 P 0.5 mm	インダストリアル	Ecopack2	-	-
STM32MP215DAM3	量産中	TFBGA 289 14x14x1.2 P 0.8 mm	インダストリアル	Ecopack2	-	-
STM32MP215DAN3	量産中	VFBGA 273 11x11x1.0 P 0.5 mm	インダストリアル	Ecopack2	-	-
STM32MP215DAO3	量産中	VFBGA 225 8x8x1.0 P 0.5 mm	インダストリアル	Ecopack2	-	-