Dual-Interface Secure Microcontroller from STMicroelectronics Boosts Safety and Convenience in Contactless Banking and e-Identification ApplicationsGeneva / 17 Jul 2019
Featuring the latest 40nm Flash process as well as enhanced RF technologies, the STMicroelectronics ST31P450 dual-interface secure microcontroller delivers exceptional robustness and performance for contactless applications in banking, identity, transportation, and pay-television.
The ST31P450 is built on the proven 32-bit Arm® SecurCore® SC000™ secure processor and meets ISO 7816 and ISO 14443 Type A smart-card and contactless standards. It supports the full range of MIFARE® libraries including MIFARE Classic®, MIFARE Plus®, and MIFARE DESFire®. ST’s 40nm Flash technology creates an ultra-small die for dual-interface use cases such as banking and, with security-enhancing properties, increases safety and fraud prevention.
Upgraded RF performance ensures ultra-reliable wireless connections for faster, easier contactless transactions. In addition, the ST31P450 features new low-power cryptographic engines that minimize the energy budget and ensure superior product performance at low RF-field strength while executing cryptographic operations. The ST31P450 also comes with optimized loading firmware that makes life easier for card provisioners, offering post-issuance capability.
ST31P450 secure microcontroller, and its associated cryptographic libraries, are expected to achieve Common Criteria EAL5+, as well as EMVCo and CUP (China UnionPay) certifications within the coming months.
The ST31P450, with 450KByte non-volatile memory (NVM) and 10KByte RAM on-chip, is in production now.
Please visit www.st.com/ST31P450 for further information.
MIFARE, MIFARE Classic, MIFARE Plus and MIFARE DESFire are registered trademarks of NXP B.V. and are used under license.
The STM32G4 Series combines a 32-bit Arm® Cortex®-M4 core (with FPU and DSP instructions) running at 170 MHz combined with 3 different hardware accelerators: ART Accelerator™, CCM-SRAM routine booster and mathematical accelerators.
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