Arm® Cortex®-M0+ in a nutshell

The Arm® Cortex®-M0+ is the most energy-efficient Arm® processor available for embedded applications with design constraints. It features one of the smallest silicon footprint and minimal code size to allow developers to achieve 32-bit performance at 16 and 8-bit price points. The low gate count of the processor enables deployment in applications where simple functions are required.

The Cortex®-M0+ brings additional features to the Arm® Cortex®-M0: as well as performance improvements in the CPU (2.46 CoreMark®/MHz compared to 2.33 CoreMark® for the M0 core), Cortex®-M0+ integrates a Memory Protection Unit (MPU), a single cycle I/O interface and a Micro Trace Buffer (MTB).

Key features of Cortex®-M0+ core

arm cortex m0 plus
  • Architecture Armv6-M
  • Bus interface AHB-lite, Von Neumann bus architecture with optional single cycle I/O interface
  • Thumb/Thumb-2 subset instruction support
  • 2-stages pipeline
  • Optional 8 regions MPU with sub-regions and background region
  • Bit banding implementation
  • Non-maskable interrupt + 1 to 32 physical interrupts
  • Wakeup interrupt controller
  • Hardware single-cycle (32x32) multiply
  • Several sleep modes, with integrated Wait For Interrupt (WFI) a Wait for Event (WFE) plus sleep on exit capability, sleep and deep sleep signals
  • Several retention modes are available depending on the implementation
  • JTAG and Serial Wire Debug ports with up to 4 breakpoints and 2 watchpoints
  • Optional Micro Trace Buffer

Key advantages of Arm® Cortex®-M0+ MCUs

The small footprint of the core allows it to be used as a single core in small devices, but also as an additional embedded companion core when specific hardware isolation or task partitioning is required.

The Cortex®-M0+ core does not impact the trade-off to be made among the elements of the typical MCU architecture based on I/Os, analog and non-volatile memories. The bus size (8, 16 or 32 bits) is therefore no longer relevant when partitioning MCU portfolios.

M0+ microcontrollers are widely used and offer high benefits in entry-level applications. They meet computing performance requirements and their basic architecture allows M0+ MCUs to reach ultra-low power performance in applications where the number of switching gates is minimized. The Cortex®-M0 core reduces noise emissions and meets performance requirements using an optimal clock speed.

The dynamic power of the core ranges from 5 to 50µW/MHz depending on the technology used. However, the core itself is not representative of the overall power consumption of a device and is not the only factor to take into account. So, it is important to carefully read product datasheets.

The Thumb instruction set is a subset of the Cortex-M family. It eases the scalability of the portfolio by re-using validated software brick for any Cortex-M products.

The Memory Protection Unit (MPU) manages the CPU's access to the memory and ensures a task does not accidentally corrupt the memory or the resources used by other active tasks. The MPU is usually controlled by a RTOS. If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. The kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed.

Arm® Cortex®-M0+ based STM32 Microcontrollers

STMicroelectronics combined the Arm® Cortex®-M0+ core with its unique proprietary low power analog peripherals for applications requiring low power and high-performance control and processing.

Explore STM32 MCU based solutions

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