In-person event

DAC

June 22-25, 2025 in San Francisco, US

The global event for chips to systems.

30 On-stage. paper & poster presentations.

3 Insightful. gladiator sessions.

10+ Network. experts on site.

Shaping the next generation of electronics

The Design Automation Conference (DAC) offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors.

This year ST will demonstrate its innovative solutions and methodologies in the field of not only designs but also how to build them. ST's experts will share their visions in the new era of design and verification flows, helping engineers design and create state-of-the-art solutions and reach the market on time while ensuring the highest quality.

We have several paper and poster presentations on the agenda showcasing our latest research on a variety of focus areas. You will also find us at one Sky Talk and in the Gladiator Arena with three presentations. Follow our agenda below!

Join ST speakers and discover their visions in the new era of design and verification flows

Discover how integrating AI into R&D, deploying edge AI, and utilizing chiplets, while addressing sustainability, forms a comprehensive strategy for future advancements.

25 June | Sky talk

1.00 PM

AI booster for R&D, edge computing, chiplets, and sustainability

Speaker

Serge Nicoleau - Group Vice-President of Technology

23 June | Paper presentation

2.00 PM

Optimized digital design flow for embedded sensor applications using high level synthesis

Speaker

Savino Bellopede

23 June | Paper presentation

2.30 PM

A novel approach to generate random/constrained Non-Volatile-Memory content in a UVM environment

Speaker

Davide Sanalitro | Product Digital Verification expert

24 June | Paper presentation

3.30 PM

Enhancing verification throughput in random tests regression with a novel machine learning engine

Speaker

Davide Sanalitro | Product Digital Verification expert

24 June | Paper presentation

4.15 PM

Mitigation of functional power dissipation in parasitic scan shift test buffers

Speaker

Aradhana Kumari, Technical leader

24 June | Paper presentation

4.45 PM

Rom-based automotive boot code, in compliancy with functional safety and cybersecurity standards

Speaker

Anil Dwivedi | Senior Group Manager (Technology & Design Platform)

25 June | Paper presentation

11.00 AM

Energy efficient I3C IP subsystem for low-power IoT

Speaker

Aradhana Kumari, Technical leader

25 June | Paper presentation

11.30 AM

High figure of merit polyphase decimation core IP

Speaker

Ankur Bal | Director Technology R&D group

Poster sessions- June 22-25

Join ST experts for insightful DAC poster sessions.

22 June | Work-in-progress poster

6.00 PM

Early mismatch detection in analog layout using PLS netlist

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

23 June | Engineering track poster session

5.00 PM

Advanced APL modeling method for complex I/O buffer designs for accurate SoC IR drop analysis

Speaker

Anil Dwivedi | Senior Group Manager (Technology & Design Platform)

23 June | Engineering track poster session

5.00 PM

Circuit design and optimization methodology ensuring area optimized, robust and reliable I/O interface for wide range of application use

Speaker

Anil Dwivedi | Senior Group Manager (Technology & Design Platform)

23 June | Engineering track poster session

5.00 PM

IR-aware timing analysis using accurate DvD-PWL flow for advanced technology nodes

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

23 June | Engineering track poster session

5.00 PM

Timing-aware smart PG fill

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

24 June | Engineering track poster session

5.00 PM

A robust and efficient verification suite for AMS IP HDL models for streamlined SoC integration

Speaker

Anil Dwivedi | Senior Group Manager (Technology & Design Platform)

24 June | Engineering track poster session

5.00 PM

AI-ML meets SPICE to achieve 6-sigma accuracy: a revolution in statistical analysis

Speaker

Anil Dwivedi | Senior Group Manager (Technology & Design Platform)

24 June | Engineering track poster session

5.00 PM

Automated topology-based pin access checker for correct by construction standard cells design

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

24 June | Engineering track poster & Gladiator session

5.00 PM

Automated – BUS routing solution for efficient DRC clean TestChip Design

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

24 June | Engineering track poster

5.00 PM

Detection of functional and current related Bugs in SoC through full chip SPICE simulations (FCS)

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

24 June | Engineering track poster session

5.20 PM

Novel shift-left methodology for system power integrity analysis with early chip power model

Speaker

Lyubomir Kerachiv

25 June | Engineering track poster

12.15 PM