In-person event

DAC

July 25-29, 2026 in California, US

Visit DAC website

The global event for chips to systems.

20+ On-stage. paper & poster presentations.

2 Insightful. invited talks.

10+ Network. experts on site.

Shaping the next generation of electronics

The Design Automation Conference (DAC) brings together designers, researchers, tool developers, and vendors to learn, connect, and explore what’s next.

This year, ST will show how our solutions and methodologies help engineers not only design better systems, but build them more efficiently too. Our experts will share their perspective on the next generation of design and verification flows, with a focus on helping teams create advanced solutions, move faster to market, and maintain high quality.

We’ll also be presenting several papers and posters across a range of research topics. Explore the agenda below.

Join ST speakers and discover their visions in the new era of design and verification flows

Discover how multi-die integration and digitally assisted analog design are advancing heterogeneous AI architectures, from system integration to data conversion, test, and clocking.

29 July | Engineering Special Session | Invited talk

10.30 AM

From Datacenter to Physical World: Optimizing Multi-Die Integration for Heterogeneous AI Architectures

Speaker

Serge Nicoleau | Group Vice-President of Technology

28 July | Engineering Special Session | Invited talk

1.30 PM

Digitally Assisted Analog Techniques for Next‑Generation Data Converters, Test, and Clocking

Speaker

Ankur Bal | Director Technology R&D group

28 July | Paper presentation

11.30 AM

Scalable, Protocol-Agnostic Clockless In-Band Reset Architecture for Serial Link IPs in Multi-Domain SoCs

Speaker

Aradhana Kumari | Staff Engineer

29 July | Paper presentation

11.15 AM

Intelligent Clock Domain Crossing: Activity-Aware Synchronization for Low-PowerSoCs

Speaker

Aradhana Kumari | Staff Engineer

29 July | Paper presentation

10.30 AM

In-situ Architecture for Detecting and Mitigating Off-Chip Interface Attacks

Speaker

Archana Arya | Principal Engineer

29 July | Paper presentation

11.30 AM

No More Blind Spots: RTL Modeling of Metastability for CDC Verification

Speaker

Archana Arya | Principal Engineer

27 July | Paper presentation

2.00 PM

Leveraging AI/ML Techniques for Memory Circuit Performance Optimization: Insights from ASO.ai

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

29 July | Paper presentation

2.15 PM

Automated System for FPGA-Based SoC Prototyping

Speaker

Stefano Cumia

Poster sessions- July 25-29

Join ST experts for insightful DAC poster sessions.

27 July | Engineering track poster

5.00 PM

Leveraging AI/ML Techniques for Memory Circuit Performance Optimization: Insights from ASO.ai

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

27 July | Engineering track poster session

5.00 PM

Advancing CDC Formal Verification in Low-Power SoCs Using Power Intent and Smart Waiver Techniques

Speaker

David Vincenzoni

27 July | Engineering track poster session

5.00 PM

The new era of digital verification: a revolution driven by agentic AI acceleration

Speaker

Davide Sanalitro | Product Digital Verification expert

27 July | Engineering track poster session

5.00 PM

OoB Generator: A novel method to improve the productivity of RTL-to-Layout using Python

Speaker

Mario Blangiforti and Luca Pulvirenti

27 July | Engineering track poster session

5.00 PM

A Novel Automated Methodology Python Driven for Test Coverage Improvement via Fault Injection and Simulation

Speaker

Mario Blangiforti, Luca Perroni, Luca Pulvirenti

27 July | Engineering track poster session

5.00 PM

Matching Constraint Driven Synchronous Array Implementation for High-Performance ADCs

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

27 July | Engineering track poster session

5.00 PM

Innovative Multiplatform Framework Boosting 10BaseT Ethernet Verification for Next-Gen Automotive SoCs

Speaker

Archana Arya | Principal Engineer

28 July | Engineering track poster session

5.00 PM

A Compact Digital IP for FMCW Chirp Linearity Monitoring in Automotive Radar Systems

Speaker

Ankur Bal | Director Technology R&D group

28 July | Engineering track poster session

5.00 PM

An Adaptive Dynamic Power Reduction Technique for Digital Filters

Speaker

Ankur Bal | Director Technology R&D group

28 July | Engineering track poster session

5.00 PM

Scalable, Protocol-Agnostic Clockless In-Band Reset Architecture for Serial Link IPs in Multi-Domain SoCs

Speaker

Aradhana Kumari and Ankur Bal

28 July | Engineering track poster

5.00 PM

A Hybrid Simulation and Formal Verification Approach for Exhaustive Interrupt and Status Flag Verification

Speaker

Archana Arya | Principal Engineer

28 July | Engineering track poster

5.00 PM

Fully Automated On‑Chip Inductor Synthesis for High‑Frequency VCO with ML Based Optimization Flow

Speaker

Atul Bhargava | Senior Group Manager & Senior Member of Technical Staff

28 July | Engineering track poster session

5.20 PM

Channel Width Optimization for IR Drop Reduction in Advanced SoCs

Speaker

Govind Pal

28 July | Engineering track poster

5.00 PM

AI-Enabled Flow for Silicon Area Reduction and Design Closure

Speaker

Anil Yadav

28 July | Engineering track poster session

5.00 PM

Breaking Sequential Depth Barriers: An FSM-Driven Bridge for the Formal Verification of Virtually Address-Mapped Hardware Registers

Speaker

Ankur Bal | Director Technology R&D group

28 July | Engineering Poster Gladiator

3.00 PM

A Method to Automate the Conversion of .def File into .save.io One to Speed up the BE Digital Flow in Analog-on-Top Designs

Speaker

Luca Pulvirenti

28 July | Engineering track poster session

5.00 PM