Arm® Cortex®-M0 in a nutshell
The Arm® Cortex®-M0 is the smallest Arm® processor available, with a very small silicon area, low gate count, low power and minimal code footprint. Suitable for analog and mixed signal devices, it allows microcontroller suppliers to offer 32-bit performance at 16- and 8-bit price points. It is ideal for highly embedded applications.
Key features of Arm® Cortex®-M0 core
- Armv6-M architecture
- Bus interface AHB-lite, Von Neumann bus architecture
- Thumb/Thumb-2 subset instruction support
- 3-stages pipeline
- Bit banding implementation
- Non-maskable interrupt + 1 to 32 physical interrupts
- Wakeup interrupt controller
- Hardware single-cycle ((32x32) multiply
- Several sleep modes, with integrated Wait For Interrupt (WFI) and Wait for Event (WFE) plus sleep on exit capability, sleep and deep sleep signals
- Several retention modes are available depending on the implementation
- JTAG and Serial Wire Debug ports with up to 4 breakpoints and 2 watchpoints
Key advantages of Arm® Cortex®-M0 MCUs
The small footprint of the core allows it to either be used as a single core in small devices or as an additional embedded companion core when specific hardware isolation or task partitioning is required. Thanks to the advancements in silicon manufacturing technologies, the lithography process moved from 180 to 90nm and lower, and the core silicon real-estate now reaches 0.03mm² in 90nm lithography.
The Cortex®-M0 core does not impact the trade-off to be made among the elements of the typical MCU architecture based on I/Os, analog and non-volatile memories. The bus size (8, 16 or 32 bits) is therefore no longer relevant when partitioning MCU portfolios.
M0-based microcontrollers are widely used and offer high benefits in entry-level applications. They meet computing performance requirements and their basic architecture allows M0 MCUs to reach ultra-low-power performance in applications where the number of switching gates is minimized. The Cortex®-M0 core reduces noise emissions and meets performance requirements using an optimal clock speed.
The dynamic power of the core ranges from 5 to 50µW/MHz, depending on the technology used. However, the core itself is not representative of the overall power consumption of a device and is not the only factor to take into account. It is therefore important to carefully read product datasheets.
The Thumb instruction set is a subset of the Cortex®-M family. It eases the scalability of the portfolio by re-using validated software bricks for any Cortex®-M products.
Microcontrollers based on the Arm® Cortex®-M0
STMicroelectronics combined the Arm® Cortex®-M0 core with its unique proprietary low power analog peripherals for applications requiring cost-efficient and low power control and processing.
|Single Core Series||Speed (MHz)||Performance (CoreMark)||Flash (kB)||RAM (kB)||Power Supply (V)||Packages||Connectivity||Analog|
|STM32F0||48||106||16 to 256||4 to 32||1.65 to 3.6||LQFP32/48/64/100, TSSOP20, UFBGA64/100, UFQFPN28/32/48, WLCSP25 to 64||USART, SPI, I2C, CAN, USB||Yes|
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Exceptional 32-bit performance with low power consumption
Smallest footprint and lowest power requirements of Cortex-M processors
Smallest Arm® processor available
Highest performance Cortex-M processor
Control and performance for mixed signal devices
Ideal blend of real-time determinism, efficiency and security