How to make solar inverters safer with AI arc detection
DC arcs are a major cause of fires in photovoltaic plants. With strings reaching 1500 V / 20 A, an undetected arc can destroy equipment or start a fire, while a false alarm forces a mandatory shutdown and costly downtime. The STM32H7P brings AI-based arc fault detection into a single microcontroller, checking 20 inverter channels in about 7 ms with a low CPU load. Inverter makers get detection that learns from real field data, with a simpler, lower-cost design.
Application domains:
- Commercial and industrial solar inverters
- Small commercial buildings
- Residential solar installations
Approach
In a solar installation, an arc fault happens when current jumps across a damaged cable or a loose connection. Inverter manufacturers need arc fault detection that is both safe, catching real arcs, and reliable, avoiding false trips. Standards such as UL 1699B and GB/T 39750-2021 require a shutdown when an arc is detected, so every false alarm means downtime and maintenance.
Until now, the industry has relied on two approaches, each with clear limits:
- Rule-based detection uses hand-tuned filters and thresholds. It's simple and light on compute, but it struggles in real conditions: inverter switching noise (36/72 kHz) masks the arc signature, and changes in weather, aging or installation mean rewriting and re-tuning the code.
- Multi-chip architectures chain external ADCs, a dedicated DSP for the detection algorithm, and a host MCU. They add BOM cost, take more PCB area, and make integration complex.
The STM32H7P takes a more adaptive approach. A neural network learns arc signatures directly from real field data, and is simply retrained when conditions change instead of being rewritten. The whole detection chain runs on one chip: the HSP (Hardware Signal Processor) prepares the signal and the NPU runs the inference, leaving the CPU almost free.
Key benefits of this edge AI approach:
- One chip instead of several: lower system cost, simpler integration and faster development.
- Learns from the field: the model is retrained on new data when conditions change, instead of re-tuning rules.
- Built for many channels: the same model is reused for each channel, with 20 channels on a single STM32H7P.
- Fast reaction: about 7 ms end to end for 20 channels.
- Low CPU load, as the NPU and HSP are working in parallel to manage most of the compute.
- Built to limit missed arcs and false trips: the neural network learns to separate the arc signature from inverter noise, where fixed thresholds struggle.
Application overview
Each monitored DC channel goes through the same detection chain, entirely inside the STM32H7P.
1. Measure the current
Standard current sensors or current transformers measure the DC current on each monitored channel. The ADC samples each signal at 100 to 350 kS/s per channel, with DMA moving the data without loading the CPU.
2. Prepare the signal
For each channel, the HSP pre-processes the signal: FFT, normalization and quantization. This turns the raw current into the frequency content where the arc signature appears.
3. Detect the arc
The NPU runs a neural network that classifies each channel as arc or no arc.
4. Act
The CPU handles the application logic, the interface with the host, and the rapid shutdown (RSD) that makes the installation safe when an arc is detected.
Technical details
Detecting an arc means recognizing a complex signature in the frequency content of the current. A neural network trained on labeled arc and non-arc data learns to separate this signature from inverter noise.
To bring this intelligence into the inverter, the trained model is quantized and converted into MCU-ready code, then runs on the NPU of the STM32H7P. This efficiency is what makes the solution scale: the same model is reused for every channel, so a single STM32H7P monitors 20 channels on the NUCLEO-H7P5II board.
Sensor
Capturing clean arc signals is the key to reliable detection, so ST provides an end-to-end acquisition chain. The STEVAL-AFCI1 board (available soon) integrates analog filtering to remove the inverter switching-frequency peak, an MCU, and a USB link to a PC for datalogging. Recorded data can then be replayed as an analog signal to the NUCLEO-H7P5II board, to test the AFCI application on real field data.
Model and results
Dataset:
- Arc fault detection dataset: 7,000 current waveforms recorded by ST on a controlled test bench, each labeled arc or normal operation
Model:
- Task: binary classification (arc / no arc) per channel, on the pre-processed frequency content of the current
- Compact CNN and dense model families, from the STM32 AI Model Zoo
Results:
- Measured on the NUCLEO-H7P5II board (STM32H7P at 520 MHz), at 350 kS/s per channel
- NPU inference: 53 µs per channel
- HSP pre-processing: ~106 µs per channel
- End-to-end latency: ~7 ms for 20 channels (~4 ms signal capture window + ~2.8 ms to process all 20 channels + CPU margin, with HSP and NPU working in parallel)
Resources
Software tools
- STM32Cube AI Studio, for neural network conversion and deployment
- ST Edge AI Core command-line interface
Documentation
Resources
Optimized with STM32Cube AI Studio
STM32Cube AI Studio is a desktop tool designed to evaluate, optimize and compile neural network models for STM32 microcontrollers. It fully supports compilation for the Neural-ART Accelerator neural processing unit (NPU). It replaces the X-CUBE-AI in the ST AI product offering to cover new STM32 devices.
Most suitable for STM32H7P Series
The STM32 family of 32-bit microcontrollers based on the Arm Cortex®-M processor is designed to offer new degrees of freedom to MCU users. It offers products combining very high performance, real-time capabilities, digital signal processing, low-power / low-voltage operation, and connectivity, while maintaining full integration and ease of development.