SPC56 L Line MCUs

SPC564L and SPC56EL 32-bit MCUs are based on the Power Architecture core and are designed to cover a wide range of automotive applications that must meet ISO 26262 up to the most stringent ASIL-D level with a single MCU.

The key functions required to achieve automotive integrity level D (ASIL-D) with a single MCU are two fully independent cores, replication of key components (such as cores in lock-step mode, crossbar, eDMA, MPU, temperature sensors), centralized fault collection and control unit, built-in logic and memory self test, CRC unit, ECC protected memories, voltages and clock-failure detection.

ST’s L (Leopard) line devices feature:

•Two high-performance e200z4d cores with FPU and DSP capability
•768-Kbyte to 2-Mbyte Flash memory with ECC
•96-Kbyte and 192-Kbyte RAM memory
•An optimized peripheral set for safety and motor-control applications, supporting up to two brushless 3-phase motors