The X-CUBE-PERF-H7 firmware aims to demonstrate the performance of the STM32H7x3 architecture with its Cortex®-M7 able to run at 400 MHz, and its instruction and data caches that unleash core performance with 0-wait-state-like execution from different memories, either internal or external, scattered across different domains (D1, D2, and D3) and accessed by the core either through the TCM buses or the AXIM bus.
The firmware is provided with several project configurations for the STM32H743I-EVAL evaluation board. Each project allows the execution of application code and data storage in different memory locations such as internal memories as well as external memories located in different domains (D1, D2 and D3). Firmware results demonstrate that performance is almost the same when internal memories or external memories or different domains are used for code execution or data storage. An FFT use case (provided by the CMSIS library) is proposed as an example with several toolchains: Keil® (MDK-ARM), IAR™ (EWARM), and System Workbench (SW4STM32). It can easily be ported to any other toolchain.
- STM32H7x3 performance demonstrator
- Code execution and data storage in different memory locations
- Instruction cache (I-Cache)
- Data cache (D-Cache)
- D1, D2, and D3 domains
- AXI and AHB bus matrices