STM32F7 series of very high-performance MCUs with Arm® Cortex®-M7 core
Taking advantage of ST’s ART Accelerator™ as well as an L1 cache, STM32F7 microcontrollers deliver the maximum theoretical performance of the Cortex-M7 core, regardless if code is executed from embedded Flash or external memory: 1082 CoreMark /462 DMIPS at 216 MHz fCPU.
Smart architecture with new peripheral set
The STM32F7 series unleashes the Cortex-M7 core:
- AXI and multi-AHB bus matrixes for interconnecting core, peripherals and memories
- Up to 16 Kbytes +16 Kbytes of I-cache and D-cache
- Up to 2 Mbytes of embedded Flash memory, with Read-While-Write capability on certain devices
- Two general-purpose DMA controllers and dedicated DMA controllers for Ethernet (on some variants), high-speed USB On-The-Go interfaces and the Chrom-ART graphic accelerator (on some variants)
- Peripheral speed is independent from CPU speed (dual clock support) allowing system clock changes without any impact on peripheral operations
- Even more peripherals, such as two serial audio interfaces (SAI) with SPDIF output support, three I²S half-duplex interfaces with SPDIF input support, two USB OTG interfaces with dedicated power supply and Dual-mode Quad-SPI Flash memory interface
- Large SRAM with a scattered architecture:
- Up to 512 Kbytes of universal data memory, including up to 128 Kbytes of Tightly-Coupled Memory for Data (DTCM) for time critical data handling (stack, heap...)
- 16 Kbytes of Tightly-Coupled Memory for Instructions (ITCM) for time-critical routines
- 4 Kbytes of backup SRAM to keep data in the lowest power modes
- Protected code execution feature (PC-ROP) on some variants
- On-chip USB high-speed PHY on some variants
- 7 CoreMark/mW at 1.8 V
- 100 µA typical current consumption in Stop mode with all context and SRAM saved
- Cortex-M7 is backwards compatible with the Cortex-M4 instruction set. Read more about the benefits of the 32-bit Arm Cortex-M7 processor here.
- STM32F7 series is pin-to-pin compatible with the STM32F4 series*
* Note: see datasheet for the specific case of 64- and 100-pin packages.
The STM32F7 optimizes the performance of the entire system by combining a set of brand new peripherals around the Cortex-M7 with a superior interconnect architecture with AXI and multi-layer AHB bus matrixes, multiple general-purpose and dedicated DMA controllers, a Chrom-ART graphic hardware accelerator as well as a JPEG accelerator on some variants.
Learn more about the STM32F7 series exiting features and high-performance form with the STM32F769I-DISCO discovery kit.