Fully Depleted Silicon On Insulator
ST introduced new innovations in silicon process technology that incrementally leverage existing manufacturing approaches. Fully Depleted Silicon On Insulator, or FD-SOI, is a planar process technology that delivers the benefits of reduced silicon geometries while actually simplifying the manufacturing process. Thanks to a tight electrostatic control of the transistor and the introduction of very innovative power management techniques, FD-SOI is a recognized as a lead technology for low power, RF and millimeter-wave applications. Associated with the high density PCM embedded non-volatile memory, ST offers a unique proposition for automotive applications.
In bulk technology, body biasing is very limited, due to parasitic current leakage and inefficiency at reduced transistor geometry. Thanks to the transistor construction in FD-SOI and its ultra-thin insulator layer, biasing is much more efficient. Also, the presence of the buried oxide allows the application of higher biasing voltages, resulting in breakthrough dynamic control of the transistor.
When polarization of the substrate is positive— “Forward Body Biasing” or FBB— the transistor can be switched faster.
This provides an extremely powerful technique to optimize performance and power consumption. Easy to implement, FBB can be modulated dynamically during the transistor operation, bringing a great flexibility for designers and letting them design their circuits to be faster when required and more energy efficient when performance isn’t as critical.
FD-SOI brings many advantages to analog designs. The total dielectric isolation of the channel allows for lower gate capacitance and leakage currents, as well as the benefit of latch-up immunity. Moreover, the absence of channel doping and pocket implants in the fully depleted transistor produce lower noise and higher gains (up to +15dB) when compared to bulk technologies.
All this translates to smaller and simpler analog circuits, with higher performance at lower operating power.
The improved electrostatic characteristics and dielectric isolation in FD-SOI bring two main advantages. First, it maintains competitive operation speed at low voltage. Then, it allows much more effective body biasing, providing profound control over the channel, with the ability to optimize passive and dynamic power consumptions.
Thanks to its ultra-thin body and buried oxide, by construction the FD-SOI technology exhibits high resilience against radiation errors, such as bit flip or latch-up, bringing additional reliability to high performance systems-on-chips, as well as area saving (e.g. simplifying ECC strategy for SRAMs).
Beyond the intrinsic benefits of FD-SOI technology, for 20+ years ST has been developing a whole set of techniques to design Rad-Hard circuits. Our long-standing expertise in radiation modeling, design and test allows the company to offer quasi-immune circuits aimed at highly demanding market segments such as safety, automotive ADAS, space, industrial, medical and networking.
Combined with ST’s patented “single well” bitcell architecture, FD-SOI dramatically improves SRAM memory performance, operating at low voltage and with extremely low leakage, while keeping similar read/write speed as conventional bulk SRAM.
ST has a broad offer to support designs in 28 nm FD-SOI with a variety of key design blocks available to designers.