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High-Performance Arm Cortex-M7 MCU, 600MHz, 64KB Bootflash, 620KB SRAM, with DSP, cache, USB HS PHY, NeoChrom GPU, TFT-LCD

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Product overview

Key Benefits

High performance

Max performance with 600 MHz bootflash MCU: execute real-time anywhere, with serial & parallel memory interfaces up to 200 MHz DTR.

Design freedom

Scale up and down on external memory with flexible memory architecture.

Best-in-class graphics

Leverage NeoChrom GPU and JPEG Codec with intelligent DMA Architecture for maximum graphics performance.


STM32H7Sxx8 devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 600 MHz. The Cortex -M7 core features a floating point unit (FPU) which supports Arm double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. The Cortex -M7 core includes 32 Kbytes of instruction cache and 32 Kbytes of data cache. STM32H7Sxx8 devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.

STM32H7Sxx8 devices incorporate high-speed embedded memories, 64 Kbytes of user flash memory and 128 Kbytes of system flash memory,and up to 620 Kbytes of RAM (including 128 Kbytes that can be shared between ITCM and AXI, including 64 Kbytes exclusively ITCM, including 128 Kbyte DTCM, including 64 Kbytes exclusively DTCM, including 32 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access. To improve application robustness, all memories feature error code correction (one error correction, two error detections).

The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC coprocessor for trigonometric functions). All the devices offer two ADCs, a low-power RTC, 4 general-purpose 32-bit timers, 7 general-purpose 16-bit timers including one PWM timer for motor control, five low-power timers, and a cryptographic acceleration cell (CRYP), Public key acceleration (PKA), a secure AES coprocessor (SAES) and a memory cipher engine (MCE) The devices support one digital filter for external sigma-delta modulators or digital microphone with voice activity detection. They also feature standard and advanced communication interfaces.

  • All features

    • Includes ST state-of-the-art patented technology
    • Core
      • 32-bit Arm® Cortex®-M7 CPU with MPU and DP-FPU, L1 cache: 32+32-Kbyte instruction and data cache allowing 0-wait state execution from embedded flash memory and external memories, frequency up to 600 MHz, 1284 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
    • Memories
      • 64 Kbytes of user flash memory that can be used for user code and/or external memory configuration.
      • SRAM: total 620 Kbytes (548 Kbytes with optional ECC activated) organized as follows:
        • 64+64 Kbytes minimum of instruction and data TCM RAM for critical real time instructions
        • 384 Kbytes AXI SRAM (128 Kbytes with optional remap to TCM RAM fully activated
        • 4 Kbytes of backup SRAM (available in the lowest-power modes)
      • Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, FRAM, SDR/LPSDR SDRAM, NOR/NAND memories
      • Up to 2x octo-SPI memory interfaces or 1 octo-SPI + 1 hexa-SPI with XiP, with support for serial PSRAM/NAND/NOR, HyperRAM™/ HyperFlash™ frame formats running at up to 200 MHz
      • 2x SD/SDIO/MMC interfaces
    • 2x DMA controllers to offload the CPU
      • 2 × dual-port DMAs with FIFO and linked listed support
    • Security and cryptography
      • PSA level 2 and SESIP level 3 certified (under certification)
      • Flexible life cycle scheme with debug authentication based on certificate or password (debug reopening/regression support)
      • Root of trust thanks to unique boot entry and secure hide protection area (HDP)
      • Secure firmware installation / update (SFI/SFU) thanks to embedded root secure services (RSS)
      • Secure data storage with hardware unique key (HUK)
      • 2 AES coprocessors including one withDPA resistance
      • Public key accelerator, DPA resistant with ECC verification feature only.
      • On-the-fly encryption/decryption of serial and parallel external memories
      • HASH hardware accelerator
      • True random number generator, NIST SP800-90B compliant
      • 96-bit unique ID
      • 1 Kbyte OTP (one-time programmable)
      • Active tampers
      • Hardware secure storage (dedicated secure flash area)
    • Graphics
      • NeoChrom graphic processor (GPU2D) accelerating any angle rotation, scaling and perspective correct texture mapping
      • Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation
      • Chrom-GRC (GFXMMU) allowing up to 20% of graphic resources optimization
      • Hardware JPEG codec
      • LCD-TFT controller supporting up to SVGA resolution
      • Flexible memory controller FMC8/16 for parallel displays supporting up to WSVGA
      • Digital camera parallel interface with pixel format conversion and cropping capabilities
    • Clock, reset and supply management
      • 1.71 V to 3.6 V application supply and I/O
      • POR, PVD and BOR
      • Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
      • Embedded regulator LDO to supply the VCORE and/or external circuitry
      • High power-efficiency SMPS step-down converter regulator to directly supply VCORE and/or external circuitry
      • Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
      • External oscillators: 4-50 MHz HSE, 32.768 kHz LSE
    • Low power
      • Sleep, Stop, and Standby modes
      • VBAT supply for RTC, 32×32-bit backup registers
    • Analog
      • 2x12-bit ADC, up to 5 MSPS in 12-bit, up to 17 channels
    • Audio digital filters (ADF)
      • 2 microphones /1 filter
      • Voice activity detector (VAD) support
    • Up to 152 I/O ports with interrupt capability
    • Mathematical acceleration
      • CORDIC for trigonometric functions acceleration
    • 23 timers
      • Sixteen 16-bit (including 5 x low power 16-bit timer available in stop mode, one graphic timer), four 32-bit timers, 2x watchdogs, 1x SysTick timer
      • RTC with sub-second and hardware calendar with calibration (to be verified)
    • Debug mode
      • Authenticated debug and flexible device lifecycle
      • SWD and JTAG interfaces
      • ETM with 2-Kbyte embedded trace buffer
    • Up to 35 communication interfaces
      • 3× I2C FM+ (SMBus/PMBus™)
      • 1x I3C interface (muxed with one I2C)
      • Up to 3 USARTs/4 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 2x LPUART
      • 6 SPIs with 4 with muxed duplex I2S and 3x USART configured in synchronous mode (9 SPIs)
      • 2x SAI (serial audio interface)
      • 2× FD-CAN
      • 16-bit parallel slave synchronous interface
      • SPDIF-IN interface, HDMI-CEC
      • Ethernet MAC interface with DMA controller
      • 1 USB Type-C®/USB power delivery controller
      • 1 USB OTG full-speed with embedded PHY
      • 1 USB OTG high-speed with embedded PHY
    • ECOPACK2 compliant packages

Circuit Diagram

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Quality and Reliability

Part Number Marketing Status Package Grade RoHS Compliance Grade Material Declaration**
UFBGA 144 10x10x0.6 P 0.8 mm Industrial Ecopack2



UFBGA 144 10x10x0.6 P 0.8 mm

Material Declaration**:

Marketing Status



UFBGA 144 10x10x0.6 P 0.8 mm



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(**) The Material Declaration forms available on may be generic documents based on the most commonly used package within a package family. For this reason, they may not be 100% accurate for a specific device. Please contact our sales support for information on specific devices.

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