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The STM32H750 Value line of microcontrollers offers the performance of the Arm® Cortex®-M7 core (with double-precision floating point unit) running up to 480 MHz. By trimming the embedded Flash memory to the essential, developers benefit from the lowest price point ever for the STM32H7 series.


At 480 MHz fCPU, microcontrollers from the STM32H750 Value line deliver 2400 CoreMark /1027 856 DMIPS performance executing from Flash memory, with 0-wait states thanks to its L1 cache. The digital signal processor (DSP) instruction set and the double-precision floating-point unit (FPU) enlarge the range of addressable applications. External memory can be used with no performance penalty thanks to the L1 cache (16 Kbytes of I-cache + 16 Kbytes of D-cache).


The STM32H750 MCUs integrate a crypto/hash processor providing hardware acceleration for AES-128, -192 and -256 encryption, with support for GCM and CCM, Triple DES, and hash (MD5, SHA-1 and SHA-2) algorithms.
The STM32H750 also enable Secure Firmware Install (SFI) embedded security services to authenticate and protect your software IPs while performing initial programming.

Power efficiency

The multi-power domain architecture allows the different power domains to be set in low-power mode to optimize the power efficiency. In addition to the main regulator featuring voltage scaling to supply the core in different voltage ranges during Run and Stop modes, the device also embeds a USB regulator to supply the embedded physical layer (PHY) and a backup regulator.

The maximum junction temperature supported is up to 125 °C, allowing to leverage the full core and peripheral performance even when the ambient temperature increases.

  • 275 µ/MHz typical @VDD = 3.3 V and 25 °C in Run mode (peripherals off)
  • 2.95 µA in Standby mode (low-power mode)


The new LCD-TFT controller interface with dual-layer support takes advantage of the Chrom-ART Accelerator™. This graphics accelerator creates content twice as fast as the core alone. As well as efficient 2-D raw data copy, additional functions are supported by the Chrom-ART Accelerator such as image format conversion or image blending (image mixing with some transparency). As a result, the Chrom-ART Accelerator boosts graphics content creation and saves the processing bandwidth of the MCU core for the rest of the application. In addition, the STM32H50 Value line embeds a JPEG hardware accelerator for fast JPEG encoding and decoding, off-loading the CPU which remains available for other tasks.

Embedded peripherals

  • Audio: Two dedicated audio PLLs, three full-duplex I²S interfaces, a new serial audio interface (SAI) supporting time-division multiplex (TDM) mode and a DFSDM (digital filters for sigma-delta modulators or MEMS microphone).
  • Up to 35 communication interfaces including four USARTs in addition to four UARTs running at up to 12.5 Mbit/s, one low-power UART, six SPIs running at up to 100 Mbit/s, four I²C interfaces running at up to 1 MHz with a new optional digital filter capability, two FD-CAN, two SDIO, USB 2.0 full-speed device/host/OTG controller with an on-chip PHY and a USB 2.0 high-speed/full-speed device/host/OTG controller, on-chip full-speed PHY and ULPI, Ethernet MAC, SPDIF-IN, HDMI-CEC, camera interface, single-wire protocol interface and MDIO slave.
  • Analog: Two 12-bit DACs, three fast ADCs reaching 16-bit maximum resolution (3.6 Msamples/s), 22 16- and 32-bit timers running at up to 400 MHz on the 16-bit high-resolution timer. Easily extendable memory range using the flexible memory controller with a 32-bit parallel interface, and supporting Compact Flash, SRAM, PSRAM, NOR, NAND and SDRAM memories or using the Dual-mode Quad-SPI to allow code execution from an external serial Flash memory. An analog true random number generator.

The STM32H750 Value line MCUs provide 128 Kbytes of Flash memory, 1 Mbyte of SRAM with a scattered architecture: 192 Kbytes of TCM RAM (including 64 Kbytes of ITCM RAM and 128 Kbytes of DTCM RAM for time-critical routines and data), up to 512 Kbytes of user SRAM, and 4 Kbytes of SRAM in the backup domain to keep data in the lowest power modes and LQFP100, UFBGA176 and TFBGA240 packages.

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